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363 results about "Middle level" patented technology

Underpants Type Disposable Diaper Cover

[Problem] An underpants type disposable diaper cover capable of firmly holding an absorbent pad.
[Means for Solving Problems] In an underpants type disposable diaper cover comprising a front body part (F) and a back body part (B) which are formed in such a manner as to be continuous with each other at a crotch portion and both side portions, thereby creating a waist opening (23) and a pair of right and left leg openings, and an absorbent pad (10) which is detachably attached to an inner surface thereof, a plurality of waist portion-elastic members (24) are spaced, reaching from one side to the other side, in a longitudinal direction along the waist opening (23) in the front and back body parts (F, B), a plurality of curved elastic members (26, 28) are spaced without intersecting each other in each of the front and back body parts (F, B), which extend from an upper level with respect to a middle level in a longitudinal direction on one side in a lateral direction, to an upper level with respect to a middle level in the longitudinal direction on the other side in the lateral direction, and extend so as to be curved toward the crotch portion with increasing closeness to a central portion in the lateral direction; and a curved portion of at least one of the curved elastic members (28) is configured in the front body part (F) as to pass on both sides with respect to an upper end portion of the attached absorbent pad.
Owner:DAIO PAPER CORP

Method, device and terminal for determining identity identification of human face in human face image

The invention provides a method, device and terminal for determining an identity identification of a human face in a human face image. The method includes the step of obtaining an original characteristic vector of the human face image, selecting k candidate vectors from a human face image database according to the original characteristic vector, choosing a matching vector of the original characteristic vector from the k candidate vectors, and determining an identity identification, recorded in the human face image database, of the matching vector as the identity identification of the human face in the human face image according to the matching vector of the original characteristic vector. According to the method, device and terminal, low-lever human face characteristic vectors and middle-level characteristic vectors formed by interacting with self-correlation and mutual-correlation submatrixes in a combined Bayesian probability matrix are stored in the human face image database, the middle-level characteristic vectors contain characteristic vectors of human faces and information interacting with the self-correlation and mutual-correlation submatrixes in the combined Bayesian probability matrix, and efficiency and accuracy of human face identification can be improved.
Owner:HUAWEI TECH CO LTD

RGB-D salient object detection method based on foreground and background optimization

The invention discloses an RGB-D salient object detection method based on foreground and background optimization. The method comprises the following steps: initial foreground modeling is performed based on low-level feature contrast, and a superpixel-level initial salient figure is obtained; a middle-level aggregation processing is performed on the superpixel-level initial salient figure, and a middle-level salient figure is obtained; a high-level prior is introduced in the middle-level salient figure to improve the detection effect, and a foreground probability is generated; edge connectivity mixing depth information is calculated, and the edge connectivity is converted into a background probability; the foreground probability and the background probability are optimized, and a objective function is obtained; the objective function is solved, a optimal salient figure is obtained, and the detection of a salient object is realized. According to the invention, a optimization framework based on foreground and background measurement and the depth information of a scene is fully utilized by the invention, a high recall rate can be obtained, and the accuracy is high; the method can accurately position the salient object in different scenes and different sizes of objects and can also obtain nearly equal salience values in the target object.
Owner:TIANJIN UNIV

Method for detecting region of interest in complicated natural environment

The invention relates to a method for detecting a region of interest, called ROI for short, from bottom to top based on combination of low-level image information and middle-level image information. The method for detecting the region of interest comprises the steps that firstly, an angular point is detected through the Harris operator, so that a convex hull boundary is obtained, and a middle-level information saliency map is calculated according to a convex hull area and a superpixel clustering result; secondly, an image which is originally in the RGB space is converted into the CIELab space, and filtering is conducted on the image through a Gaussian difference filter, so that a low-level information saliency map is obtained; finally, weight fusion is conducted on the low-level image information and the middle-level image information so that a saliency map of the image can be obtained. According to the method for detecting the region of interest, through the combination of the middle-level image information calculated through superpixel clustering and the low-level image information calculated through filtration of the difference filter, accurate positioning of the region of interest in the complicated natural environment is achieved, and the edge of a detected object of interest is clear; meanwhile, background noise can be effectively restrained, and the applicability is high.
Owner:山邮数字科技(山东)有限公司

Block level routing architecture in a field programmable gate array

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16x16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3x3 switch matrix. A second side of each EB 3x3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3x3 switch matrix may be coupled to the leads on the second side of second EB3x3 switch matrix by BC criss-cross extension.
Owner:ACTEL CORP

Dynamic quality detection method for whole assembly of automobile products

InactiveCN103245513AEnsure the quality level of mechanical assemblyVehicle testingAutomotive productFrequency response
The invention relates to a dynamic quality detection method for whole assembly of automobile products. The method comprises the following steps: N assembly welding or bolt junction points between the chassis component and the automobile body component of the automobile product are selected as standard detection points, and the dynamic rigidity of the assembly coupling junction interface where the N detection points are located form a complex matrix (Kd); excitation test is performed on the positions of the standard detection points, the matrix element of a frequency response function of test signals is recorded, and a standard value (Kd)0 is calculated; excitation test is performed on the automobile products of the same model number, the evaluation index value (Kd)n of the nth detected automobile product is calculated, the absolute value of difference value between the evaluation index value (Kd)n and the standard value (Kd)0 is calculated according to the formula that delta = |(Kd)n - (Kd)0 |; and if the ith diagonal entry magnitude of the absolute value is smaller than a reference value, the dynamic quality of the ith welding of the automobile product is regarded as excellent, otherwise, the dynamic quality of the ith welding of the automobile product is regarded as poor or moderate-level. Through the dynamic quality detection method, the dynamic quality of the machine assembly of the automobile products can be directly detected and evaluated.
Owner:JINAN UNIVERSITY

Block symmetrization in a field programmable gate array

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I / O blocks on the periphery. On each of the four sides of a B16x16 tile, and also associated with each of the I / O blocks is a freeway routing channel. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF . Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of DFF, and symmetrized with the output of the DFF to form first and second outputs of each of the clusters.
Owner:MICROSEMI SOC

Multilevel semantic feature-based face feature extraction method and recognition method

The invention discloses a multilevel semantic feature-based face feature extraction method and recognition method. The method includes the following steps that: 1) organ areas of each image in a facial image set A are divided; 2) bottom-level features of each organ are extracted and clustered; two clusters are extracted from clustering results and are adopted as positive and negative samples, and the positive and negative samples are trained in a paired combination manner such that a classifier set can be obtained, and the results of discrimination which is performed on the bottom-level features by the classifier set are united so as to obtain the middle-level features of the organ; the images in the A are the classified according to tags; any two classifications are selected from classification results of the tags and are adopted as positive and negative samples, and the positive and negative samples are trained in a paired combination manner such that a classifier set can be obtained, and the results of classification and discrimination which are performed on all the middle-level features in the A by the classifier set are united so as to obtain high-level features of the tags; the bottom-level features, the middle-level features and the high-level features are adopted to construct face features of the images; face features Vq are generated for any image q to be searched; and the face features Vq are matched with the face features in the A, and query results are returned. With the multilevel semantic feature-based face feature recognition method and recognition method adopted, recognition accuracy and stability can be improved.
Owner:BEIJING KUANGSHI TECH
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