4 results about "Processor array" patented technology

A method and system for unloading configuration data in a reconfigurable processor array comprises a bus system, and array of processor units connected to bus system, the processor units in the array including configuration data stores to store unit files comprising plurality of subfiles of configuration data particular to corresponding processor units. A configuration unload controller is connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to plurality of the processor units in array to unload the unit files particular to corresponding processor units, the unit files each comprising plurality of ordered sub-files, receiving sub-files via bus system from the array of process units, and assembling an unload configuration file by arranging the received subfiles in memory according to the process unit of the unit file of which the subfile is a part, and order of the subfile in unit file.

The present invention relates to a method and control system for a vehicle warning system belonging to a system comprising an array of external cameras connected in communication with the vehicle. To this end, the method is implemented by an array of processors in the system and comprises receiving (51) image data representing an image of the vehicle's roof from at least one camera in the array of external cameras, and detecting (52) an object on the roof by an object detection model based on the image data. Warning data is transmitted (53) to the vehicle when an object is present on the vehicle's roof, and the vehicle warning system is controlled (54) based on the warning data received by the vehicle. Figure 5

Disclosed herein is a graph streaming neural network processing system comprising a first processor array, a second processor, and a thread scheduler. The thread scheduler dispatches a thread of a first node to the first processor array or the second processor, wherein the thread is executed to generate output data comprising a data unit stored in a private data buffer of the second processor. The thread scheduler determines that the data unit is sufficient for executing a thread of a second node. The second node is dependent on the output data generated by execution of a plurality of threads of the first node. Upon determining that the data unit is sufficient, the thread scheduler dispatches the thread of the second node. The thread scheduler determines to dispatch a subsequent thread of the first node for execution when a predefined threshold buffer size is available on the private data buffer.

A data processing system includes compile time logic configured to generate configuration files for applications executing on reconfigurable processors, and execution flow logic configured to manage execution with conditional breakpoint capabilities. The system provides state inspection interfaces for examining processor state, memory contents, and application variables during stopped execution. Runtime logic executes configuration files with support for conditional breakpoints triggered by runtime data values, performance metrics, or error conditions. The system enables multi-processor synchronization with coordinated breakpoint handling across processor arrays, dynamic reconfiguration of processor configurations during stopped execution, and performance profiling at breakpoint locations. Breakpoint conditions can be defined at multiple granularity levels for computational graphs and dataflow applications. The system supports interactive debugging with step-through execution control and real-time modification of execution parameters.