41 results about "Processor array" patented technology

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

A system for integrated data provenance and reconciliation across heterogeneous financial systems, the system includes: a data ingestion module implemented as a hardware interface and configured with high-throughput adapters for structured and unstructured data ingestion from multiple heterogeneous financial subsystems, including bank ledgers, securities trading platforms, risk management databases, and regulatory reporting systems; a schema harmonization processing unit consisting of a dedicated FPGA (Field Programmable Gate Array) structure configured to perform real-time schema alignment, metadata normalization, and semantic mapping across different data models; a lineage tracking processor array implemented on application-specific integrated circuits (ASICs) and configured to encode dataflow transitions into a graph-encoded structure in which each node represents a transformation and each edge represents a dependency; a reconciliation computation cluster unit embodied as a set of graphics processing units (GPUs) configured to execute parallelized reconciliation techniques, anomaly detection routines, and balance verification processes between transformed financial records and reference records; a cryptographic verification unit comprising secure key storage hardware, quantum-resistant encryption modules, and tamper-resistant enclaves configured to generate, anchor, and verify cryptographic signatures for provenance and reconciliation events; a secure storage subsystem configured in a WORM (write-once, read-many) configuration with hardware-based integrity locks for storing immutable provenance and reconciliation logs; a controller with a dedicated visualization processor configured to generate interactive dashboards and drill-down analyses of lineage charts and voting results; and a modular chassis structure consisting of a high-speed backplane interconnect, secure power distribution modules, and tamper-evident enclosures, enabling the system to achieve real-time scalability, hardware-level security, and auditability of financial data flows across heterogeneous infrastructures.

Embodiments relate to a system for solving partial differential equations. The system receives a problem to be solved comprising a partial differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using an array of point processors. Each point processor comprises an ALU and a register file, and is configured to receive data corresponding to a respective node of a domain and generate a value for the node for a next time step, based upon instructions received over time via an instruction stream.

The invention discloses an RTL code simulation method and device, a storage medium, a computer program product, a server and a system.The RTL code simulation method comprises the steps that a to-be-simulated RTL code is obtained; in response to a simulation acceleration mode selected as a periodic accurate simulation acceleration mode, decomposing the RTL code into a plurality of sub-modules, and performing feature extraction on each sub-module; configuring an FPGA (Field Programmable Gate Array) according to the respective characteristics of the plurality of sub-modules so as to configure hardware resources on the FPGA into an initial processor array matched with the plurality of sub-modules; and mapping the RTL code into an instruction stream, and downloading the instruction stream to the initial processor array for simulation, wherein the instruction stream is generated according to an instruction set used by the initial processor array. Therefore, the processor array can be reconstructed, free switching of multiple simulation modes is realized, and the simulation efficiency and the simulation flexibility are improved.

A method of processing electrical data and signals which comprises locating a site with a geothermal hot water resource which feeds hot water to an on-site heat engine that drives an on-site electricity generator which provides electrical power to an array of microprocessors, located in an enclosure structure, that processes data transmitted from a remote location at high speeds. The processed data is transmitted back to the remote locations at high speeds.

A method and system for unloading configuration data in a reconfigurable processor array comprises a bus system, and array of processor units connected to bus system, the processor units in the array including configuration data stores to store unit files comprising plurality of subfiles of configuration data particular to corresponding processor units. A configuration unload controller is connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to plurality of the processor units in array to unload the unit files particular to corresponding processor units, the unit files each comprising plurality of ordered sub-files, receiving sub-files via bus system from the array of process units, and assembling an unload configuration file by arranging the received subfiles in memory according to the process unit of the unit file of which the subfile is a part, and order of the subfile in unit file.

The invention relates to a hybrid reconfigurable computing chip based on encryption and decryption computing and computer equipment. The method comprises the following steps: acquiring a first prime number and a second prime number, and determining a public key and an Euler function value according to the first prime number and the second prime number; the public key comprises a public key index and a modulus; performing linear operation in a private key calculation process by using the public key index and the Euler function value to obtain a first calculation result; outputting a first calculation result to a Boolean processor calculation core of a fine-grained reconfigurable architecture through a processing unit array data transmission unit and a Boolean processor array data transmission unit in sequence, so that the Boolean processor calculation core performs structured operation in a private key calculation process by using the first calculation result and an Euler function value, and a private key is obtained and output to the coarse-grained calculation core through the Boolean processor array data transmission unit and the processing unit array data transmission unit in sequence. By adopting the method, the key calculation efficiency can be improved.

Method (500) which exhibits: Selecting a hybrid parallelism technique (140) for distributing the operational load of a layer of a neural network across an array (200, 600) of processors (110, 155), wherein each processor in the array of processors can transfer data to neighboring processors in a first direction (610) and in a second direction (605); and Assigning tasks corresponding to the layer of the neural network to the array of processors using the selected hybrid parallelism technique (145), wherein the hybrid parallelism technique includes the use of a first parallelism technique when data is transferred between processors in the array of processors in the first direction (610), and the use of a second, different parallelism technique when data is transferred between processors in the array of processors in the second direction (605).

A processor (100) has: an instruction memory (114) configured to store processor instructions; a data memory (120) configured to store processor data representing an array, the array comprising a plurality of data elements; a controller (102); and an instruction pipeline (104). The instruction pipeline includes: a load stage circuit (126) configured to load array elements from the data memory; a comparison stage circuit (128) configured to compare the array elements to a reference value; a storage stage circuit (130) configured to store a result set comprising a result of the comparison of the array element with the reference value; and a loop hit detection stage circuit (132) configured to determine whether any of the set of results is associated with a hit for the reference value.

A method and apparatus for constructing a canonical data structure for a module of a multiprocessor array (MPA) chip. The normative data structure includes: parameters for combining a plurality of register transfer language (RTL) templates for sub-modules of the module into RTL description of the module; the parameter combination module is used for combining a plurality of test bench templates for corresponding sub-modules into parameters of the test bench for the modules; the combination module is used for combining a plurality of physical design script templates for corresponding sub-modules into parameters of physical design scripts for the modules; and / or for constructing parameters of an API for a module based on a set of functional criteria for module operation. The RTL description, the test bench, the physical design script, and / or the API will be built and stored in memory for designing and manufacturing the module.

The invention provides an unmanned aerial vehicle thrust line measuring device and method based on an inertial measurement unit, and the device comprises a measuring cylinder installation connecting seat which comprises a circular bottom plate and an annular side wall, and also comprises a tubular connecting piece which comprises a first section and a second section which are connected with each other, the circular bottom plate is provided with a through hole, and the tubular connecting piece is fixed at the through hole; the PCB is installed in the connecting base, a processor, an IMU array and an external communication interface are arranged on the PCB, the IMU array is used for collecting the attitude angle of the measuring cylinder, and the processor is used for analyzing and processing data and outputting the data through the external communication interface; the upper cover is fixedly mounted on the connecting seat; the top end of the measuring cylinder is fixed to the second section of the connecting piece, the bottom end of the measuring cylinder is fixed to the unmanned aerial vehicle, the suspender sequentially penetrates through the measuring cylinder, the connecting piece and the upper cover, and the unmanned aerial vehicle is hung at the bottom end of the suspender. According to the invention, the automation of the measurement process is realized, the measurement data can be traced back, and the measurement efficiency and the measurement precision are improved.

The invention provides an NLM image processing method and device based on an FPGA. The method comprises the steps that an image to be processed is processed into an image matrix; inputting the image matrix into a pulsation processor array; the pulsation processor array acquires a difference index accumulated value and a reference index accumulated value of the required image according to the image matrix, and inputs the difference index accumulated value and the reference index accumulated value into a division unit; the division unit divides the reference index accumulated value by the difference value index accumulated value to obtain a filtering pixel value; and processing the image matrix of the to-be-processed image through the filtering pixel value to obtain an output image. According to the method, the resource overhead is reduced, the adder and the multiplier are multiplexed by performing decomposition operation on the NLM operator, and the hardware area overhead is reduced; the time sequence convergence is improved through the time sequence data, so that the NLM performs pipeline operation, the logic level is reduced, and the algorithm precision is improved.

The present invention discloses an out-of-order parallel maximum flow / minimum cut method implemented by a high-energy-efficiency FPGA. The present invention folds a single-layer large two-dimensional trellis graph into a multi-layer small trellis graph. This method has two advantages: the folded grid architecture can store and process a trellis graph whose size is much larger than the size of the processor array; this architecture also gives the two-dimensional processor array vertical freedom, allowing it to use the vertical freedom to improve the parallel potential of the architecture. The folded grid architecture proposed by the present invention enables a small-sized processor array to have the ability to process a trellis graph whose size is much larger than its own. At the same time, this folded grid architecture can utilize the axial symmetry of the folding to greatly reduce the cross-border transmission of data in the processor array, thereby reducing the additional overhead caused by data movement. The present invention also proposes an out-of-order parallel execution technology, which can fully tap the parallel potential in the folded grid architecture.

A system and method delivers field control operations through transform processor arrays and software modules executing mathematical framework via dedicated circuits extending integrated hardware-software architecture. Field management modules enable parameter monitoring through distributed sensor networks and adaptive algorithms within defined operational boundaries of 0.1-100 units. The system implements transform operations through secured processing paths and software control layers while maintaining control precision exceeding 99.999%. Transform execution units enable field control through configurable processor arrays and software optimization routines with deterministic timing requirements across multiple domains.

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

The present invention provides a multi-processor parallel processing method and apparatus for panoramic image stitching, which uses at least two parallel processors to synchronously process and stitch and then output the panoramic image. The method includes: dividing the panoramic image to be output into N regions, and allocating the image processing tasks of each processor; synchronously sending the data of multiple captured images to each processor; each processor parallelly processes the multiple captured images according to the image processing tasks to obtain output images; according to the order of the N regions of the panoramic image to be output, the processors respectively output the output images to the corresponding regions in the buffer; when all the output images are output to the buffer, the stitching of the panoramic image is completed. The apparatus includes an input image buffer, a processor array, and an output image buffer, and the processor array includes at least two parallel processors. The multi-processor parallel image stitching method designed by the present invention has the advantages of strong operability, scientific rationality, high efficiency and speed.

The invention provides a large model reasoning asynchronous scheduling method and device, and the method comprises the steps: receiving an input data load, and dividing the input data load into a first data subset and a second data subset; dividing a plurality of physical cores in the spatial processor array into a calculation partition and a communication partition; inputting the first data subset into a calculation partition, executing calculation processing and outputting a first intermediate result; performing converged communication and normalization processing on the first intermediate result in the communication partition to generate a first final result; when the communication partition processes the first intermediate result, inputting the second data subset into the calculation partition, executing calculation processing and outputting a second intermediate result; converged communication and normalization processing are continued to determine a second final result. According to the method, the tasks can be cooperatively scheduled in space and time, the communication overhead is remarkably reduced, and the reasoning throughput and efficiency of the data stream processor are improved.

Disclosed herein is a graph streaming neural network processing system comprising a first processor array, a second processor, and a thread scheduler. The thread scheduler dispatches a thread of a first node to the first processor array or the second processor, wherein the thread is executed to generate output data comprising a data unit stored in a private data buffer of the second processor. The thread scheduler determines that the data unit is sufficient for executing a thread of a second node. The second node is dependent on the output data generated by execution of a plurality of threads of the first node. Upon determining that the data unit is sufficient, the thread scheduler dispatches the thread of the second node. The thread scheduler determines to dispatch a subsequent thread of the first node for execution when a predefined threshold buffer size is available on the private data buffer.

The present invention relates to the field of multimedia technology, and discloses a synchronous control method and system for a distributed video image splicing large screen. The method includes the following steps: S1: Construct a distributed video image splicing synchronous control system; S2: Multiple video input nodes respectively send the collected video image signals to the local main control computer, so that the video stream frame rate and time stamp of the video signals displayed on each group of unit display screens of the array display device are kept synchronous; S3: Synchronously control multiple remotely and distributedly arranged main control computers, so that the video stream frame rate and time stamp sent to the video input nodes of each local cloud splicing front-end processor and the array display device are kept consistent. The present invention adopts a combination of software and hardware, and a combination of local and remote control to ensure that the time stamp of each frame of video is consistent, and solves the problems of dislocation and tearing caused by asynchronous display of the distributed video image splicing large screen.

An integrated semiconductor device including: a first level including single crystal silicon and logic circuits each include first transistors; a second level, disposed above the first level and includes arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a plurality of SerDes circuits; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate having an area greater than 1,000 mm2, and where the substrate includes at least one interconnect.

The invention discloses a method for parallel processing of a neural network model on a processor array, and the method comprises the steps: employing a mixed weight division strategy for the to-be-processed Transform neural network model, distributing the to-be-processed Transform neural network model to the processor array for parallel calculation, and carrying out the parallel calculation of the to-be-processed Transform neural network model in the processor array, dividing weight matrixes of query Wq, key Wk and Wv values in an attention module of the neural network model into different processor groups along a column direction, and dividing an output projection matrix Wo into the same processor group along a row direction; in the processor array, different expert networks in the feedforward network module are completely and uniformly distributed to each processor in the processor array, and a router weight matrix is copied to all processors. According to the method and the device, the neural network model calculation is efficiently mapped to the multi-chip system, and the method and the device have high parallel calculation efficiency.

The invention provides a rapid rooting method and device for double error correction BCH and RS code decoding, and the method comprises the steps: S1, pre-calculating elements of a finite field, and obtaining a binary matrix; step S2, converting the matrix into a row simplest shape, recording a corresponding row transformation matrix, and if yes; s3, inputting a row transformation matrix obtained through pre-calculation and all-zero row position information of the matrix through an input component, and converting elements into binary column vectors of the elements; s4, a judgment vector is calculated through the parallel processor array; s5, comparing the calculation result of the judgment vector with the position of the all-zero line of the matrix, and if the calculation result is the same as the position of the all-zero line of the matrix, outputting a root; if not, outputting no root. According to the optimized technical scheme, the calculation complexity of the rooting process and the occupation of resources and energy consumption are effectively reduced, the hardware design is simplified, and the rooting efficiency and adaptability are improved.

The utility model relates to the technical field of safety protection of information technology and physical infrastructure fusion, in particular to a digital twin safety system of a key infrastructure. The system is composed of a multi-source heterogeneous data acquisition module, a secure transmission module, a digital twin modeling engine, a security protection module and a visual interaction module. The multi-source heterogeneous data acquisition module is in butt joint with a target facility through a wired / wireless dual-mode communication interface; the secure transmission module is configured with a physically isolated data channel; the digital twin modeling engine comprises a parallel processor array and a storage medium; the safety protection module is provided with a bidirectional data bus which is respectively connected with the digital twin modeling engine and the visual interaction module; the visual interaction module comprises a display terminal and an alarm unit. According to the utility model, full-chain safety guarantee from physical perception to virtual protection is realized through cooperation of multiple modules.

A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

The present invention discloses a three-dimensional processor array reconstruction method based on a switch structure, which adopts a bottleneck surface exclusion method not used in existing three-dimensional array reconstruction technologies. The method constructs each adjacent surface using a logic array construction algorithm, calculates the constructible logic layer height between them, and marks and excludes the sub-array with the largest logic layer as the bottleneck surface. It compensates for the faulty units in the adjacent construction areas using its fault-free units, reducing the situation where fault-free units with lower heights cannot be utilized due to backtracking operations during the construction process, thereby improving the reconstruction efficiency of the processor array. Considering that reselecting processor units with higher heights to continue constructing the logic plane will result in some fault-free processor units not being utilized, the present invention limits the routing distance to 1 when constructing the logic array, thereby increasing the utilization rate of fault-free processor units in the array and increasing the scale of the reconstructed array.

Disclosed herein is a graph streaming neural network processing system comprising a first processor array, a second processor, and a thread scheduler. The thread scheduler dispatches a thread of a first node to the first processor array or the second processor, wherein the thread is executed to generate output data comprising a data unit stored in a private data buffer of the second processor. The thread scheduler determines that the data unit is sufficient for executing a thread of a second node. The second node is dependent on the output data generated by execution of a plurality of threads of the first node. Upon determining that the data unit is sufficient, the thread scheduler dispatches the thread of the second node. The thread scheduler determines to dispatch a subsequent thread of the first node for execution when a predefined threshold buffer size is available on the private data buffer.

Methods, systems, and apparatuses for graph streaming processing are disclosed. One method includes receiving, by a thread scheduler, a group of threads, calculating a resource requirement for execution of the group of threads, calculating resource availability in a plurality of processors of each of a plurality of processor arrays, dispatching the group of threads to a selected one of plurality of processors of processor arrays, scheduling a group load instruction for all threads of the group of threads, including loading into a group load register a subset of inputs of the input tensor for processing of each thread of the group of threads, wherein the group load register provides the subset of the inputs of the input tensor to the group of threads of the selected one of the plurality of processors, wherein all threads of the group of threads are synchronized when executing the group load instruction.

A Mixed Precision controller configured to operate in a High-Performance Computing, HPC, system, where the HPC system includes a high-precision processor array and a low-precision processor array. The Mixed Precision controller is configured to receive a system of partial differential equations and utilize the high-precision processor array and the low-precision processor array to solve the system of partial differential equations utilizing a fixed-point iterative scheme, g. The Mixed Precision controller is characterized in that the Mixed Precision controller is configured to utilize a defect correction term which is defined as the difference between a high-precision residual, RH, and a low-precision residual, RL, where the defect correction term is added to an independent constants vector of the system of partial differential equations. The use of the MP controller in the HPC system enables high-precision accuracy of final solution while reducing computational cost and overall execution time of non-linear partial differential equations.

The present invention relates to a method and control system for a vehicle warning system belonging to a system comprising an array of external cameras connected in communication with the vehicle. To this end, the method is implemented by an array of processors in the system and comprises receiving (51) image data representing an image of the vehicle's roof from at least one camera in the array of external cameras, and detecting (52) an object on the roof by an object detection model based on the image data. Warning data is transmitted (53) to the vehicle when an object is present on the vehicle's roof, and the vehicle warning system is controlled (54) based on the warning data received by the vehicle. Figure 5

Embodiments relate to a system for solving partial differential equations. The system receives problem packages corresponding to problems to be solved, each comprising at least a partial differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using an array of point processors. Each point processor comprises a series of tiles, each having a computational element and a router, and are configured and connected based on a discretized form of the partial differential equation, to allow each point processor to receive a node of the domain and generate a value for the node for a next time step. Because all the data and computational requirements of the point processors are determined at compile time, no dynamic scheduling needs to be performed, allowing for more efficient usage of computational resources.