Traffic management architecture

Abstract

An architecture for sorting incoming data packets in real time, on the fly, processes the packets and places them into an exit order queue before storing the packets. This is in contrast to the traditional way of storing first then sorting later and provides rapid processing capability. A processor generates packet records from an input stream and determines an exit order number for the related packet. The records are stored in an orderlist manager while the data portions are stored in a memory hub for later retrieval in the exit order stored in the manager. The processor is preferably a parallel processor array using SIMD and is provided with rapid access to a shared state by a state engine.

Description

FIELD OF THE INVENTION [0001] The present invention concerns the management of traffic, such as data and communications traffic, and provides an architecture for a traffic manager that surpasses known traffic management schemes in terms of speed, efficiency and reliability. BACKGROUND TO THE INVENTION [0002] The problem that modern traffic management schemes have to contend with is the sheer volume. Data arrives at a traffic handler from multiple sources at unknown rates and volumes and has to be received, sorted and passed on “on the fly” to the next items of handling downstream. Received data may be associated with a number of attributes by which priority allocation, for example, is applied to individual data packets or streams, depending on the class of service offered to an individual client. Some traffic may therefore have to be queued whilst later arriving but higher priority traffic is processed. A router's switch fabric can deliver packets from multiple ingress ports to one ...

AI Technical Summary

Benefits of technology

[0026] The sorting means preferably comprises a parallel processor, such as an array processor, more preferably a SIMD processor.

[0027] There may be further means to provide access for the parallel processors to shared state. A state engine may control access to the shared state.

Problems solved by technology

The problem that modern traffic management schemes have to contend with is the sheer volume.

However, more complex schemes are required in routes which provide Traffic Management.

This cannot be achieved if all traffic is buffered in the same FIFO queue.

In reality, system realisation is confounded by some difficult implementation issues: High line speeds can cause large packet backlogs to rapidly develop during brief congestion events.

This demands high data read and write bandwidth into memory.

The processing overhead of some scheduling and congestion avoidance algorithms is high.

Priority queue ordering for some (FQ) scheduling algorithms is a non-trivial problem at high speeds.

For the exceptionally large numbers of input queues (of the order 64 k) required for per-flow traffic handling, the first stage becomes unmanageably wide to a point that it becomes impractical to implement the required number of schedulers.

Alternatively, in systems which aggregate all traffic into a small number of queues parallelism between hardware schedulers cannot be exploited.

It then becomes extremely difficult to implement a single scheduler—even in optimised hardware—that can meet the required performance point.

The queue first, think later strategy often fails and data simply has to be jettisoned.

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