System and method for cognitive processing for data fusion

Abstract

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to and claims the benefit of the following copending and commonly assigned U.S. Provisional Patent Application: U.S. Patent Application No. 61 / 314,055, titled “Real Time Cognitive Computing Architecture for Data Fusion in a Dynamic Environment,” filed on Mar. 15, 2010; the entire contents of which is incorporated herein by reference.STATEMENT OF GOVERNMENT GRANT[0002]The invention described herein was made in the performance of work under a NASA contract, and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.BACKGROUND[0003]1. Field[0004]This disclosure relates to a system and method for real time cognitive processing for data fusion in a dynamic environment. More particularly, the present disclosure describes a method and system for real-time, adaptive, intelligent, low power, high productive and miniaturized processing using custom VLSI design f...

AI Technical Summary

Problems solved by technology

One draw back of the Von Neumann architecture is that it is slow, regardless of computer speed.

To deal with complex data fusion applications as required in military applications, particularly remote, real time applications related to the dynamic environment, the Von Neumann machine may not be effective for demands such as compactness, real time processing, adaptive system and low power.

The speed requirements may present a challenge for a digital computer and the architecture of a system as a whole.

Each sequential step requires a delay and processing time to digest data, and finally, the solution that is provided by the computer may no longer be valid.

However, neural network hardware is typically not as fully-programmable as a digital computer.

A neural network hardware implementation also has a two-fold problem: reliable learning techniques in limited weight space for learning network convergence in a parallel architecture (see, for example, T. A. Duong and Allen R. Stubberud, “Convergence Analysis Of Cascade Error Projection—An Efficient Learning Algorithm For Hardware Implementation,” International Journal of Neural System, Vol. 10, No. 3, pp.

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