130results about "Computing operations for multiplication/division" patented technology

Disclosed is a neural network computing device. The neural network computing device includes a neural network accelerator including an analog MAC, a controller controlling the neural network accelerator in one of a first mode and a second mode, and a calibrator that calibrating a gain and a DC offset of the analog MAC. The calibrator includes a memory storing weight data, calibration weight data, and calibration input data, a gain and offset calculator reading the calibration weight data and the calibration input data from the memory, inputting the calibration weight data and the calibration input data to the analog MAC, receiving calibration output data from the analog MAC, and calculating the gain and the DC offset of the analog MAC, and an on-device quantizer reading the weight data, receiving the gain and the DC offset, generating quantized weight data, based on the gain and the DC offset.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A simulation system and method for implementing a model based on an iterative neural network, the system comprising: a simulation vector-matrix multiplication circuit that encodes a weight matrix of the model based on the iterative neural network; and an analog non-linear circuit that encodes a non-linear function arranged in a feedback loop configured to return an output signal from the non-linear circuit as input to the vector-matrix multiplication circuit, wherein the system is configured to output a solution vector of values of the model based on the iterative neural network upon convergence of the system.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line (22) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I1, I2, I3) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I1, I2, I3) into the third line (26) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element (28) with a control terminal which is connected to the second line (24) of the corresponding column; wherein input voltages (U1, U2, U3) corresponding to components of the input vector are applied (110) to the first lines; wherein for each column: a ramp voltage (V1, V2, V3) is applied (120) to the second line assigned to the column, the level of which is increased with time (130); a total current is detected at the third line assigned to the column and a time period elapsed since a start time of the level increase of the corresponding ramp voltage is determined (150) until the magnitude of the total current reaches a certain current magnitude threshold (Ig) (140); and a component of the output vector corresponding to the column is determined (170) based on the elapsed time period (t1, t2, t3).

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

The invention relates to the technical field of semiconductors, and provides an arithmetic unit and method based on a ferroelectric field effect transistor and a storage and calculation switch array. The arithmetic unit comprises a 1F1R unit, a shared capacitor, a bit line and a word line; each column of 1F1R units comprises a plurality of 1F1R units which are arranged in parallel; each 1F1R unit comprises a first resistor and a ferroelectric field effect transistor, the first resistor comprises a first end and a second end, and the ferroelectric field effect transistor comprises a grid electrode, a source electrode and a drain electrode; the grid electrode of each ferroelectric field effect transistor is connected with the word line, the source electrode is connected with the second end of the first resistor, and the drain electrode is connected with the bit line; the shared capacitor comprises a first end and a second end, the first end of the first resistor of each column of 1F1R units is connected with the first end of the shared capacitor, and the second end of the shared capacitor is grounded. According to the scheme, compact and low-power-consumption memory operation can be realized, the energy consumption of the whole array is reduced on the basis of ensuring the energy efficiency, and meanwhile, a large-area coding and decoding circuit is avoided due to the single-bit data bit width.

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

The invention relates to the technical field of computers, and discloses a computer memory data processing system comprising a calculation task compiling module used for determining physical setting parameters according to a calculation task and generating a preset target evolution path; the physical calculation execution module is used for performing state evolution according to the physical setting parameters; the dynamic feedback control module is used for monitoring the actual evolution state and generating a calibration signal according to the deviation between the actual evolution state and a preset target evolution path so as to dynamically adjust driving; and the result decoding module is used for converting the steady-state physical quantity into a calculation result after the system reaches a stable equilibrium state. By constructing closed-loop feedback control, evolution deviation generated by non-ideal factors of a physical system is corrected in real time, it can be effectively guaranteed that actual state evolution of physical calculation accurately tends to a preset ideal path, and therefore the accuracy and reliability of data processing through the physical process are remarkably improved.

An analog-digital hybrid deep neural network computing device according to one embodiment includes a control unit, an analog processing unit, a digital processing unit, and a multi-channel bus, and in which the algorithm includes a plurality of layers for computation, and an analog MAC computation in an analog computing manner is performed for a first group of layers including one or more layers among the plurality of layers in the analog processing unit and a digital MAC computation in a digital computing manner is performed for a second group of layers, which is the remaining layers except for the first group of layers, in the digital processing unit.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] An arithmetic circuit having circuits MC and MCr, wherein circuit MC has a holding node nd1, and circuit MCr has a holding node nd1r. Circuits MC and MCr are electrically connected to input wirings X1L and X2L and wirings OL and OLB, respectively, and each of circuits MC and MCr holds first and second potentials corresponding to first data in its respective holding node. When a potential corresponding to second data is input to input wirings X1L and X2L, circuit MC outputs a current to one of wirings OL or OLB, and circuit MCr outputs a current to the other of wirings OL or OLB. The current that circuits MC and MCr output to wirings OL or OLB is determined according to the first and second potentials held in the holding nodes nd1 and nd1r.

An apparatus for performing vector x vector multiplication in the optical domain, the apparatus including: a plurality of optical signal generators, each optical signal generator arranged to emit a beam of light having a different respective carrier wavelength modulated by an input signal that models a respective variable of a vector of variables; one or more sets of optical modulator elements, each optical modulator element in each set arranged to receive the beam of light modulated by a different one of the input signals and to apply a corresponding weighting from the vector of weights to generate a weighted optical signal; each set of optical sensor elements of the sets; and one or more optical combiner elements arranged to direct each set of weighted optical signals onto a respective optical sensor element, thereby generating a respective output in the form of an analog electronic signal that sums the weighted optical signals of each set.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

The embodiment of the present specification provides a kind of matrix multiplication security calculation method and device, it is suitable for the multi-party security calculation architecture of two participants, one party holds matrix, another party holds vector, and the product of the security calculation of the matrix and vector is calculated.The embodiment of the present specification makes full use of the characteristics that efficient homomorphic encryption mode can process polynomial data under the multi-party security calculation architecture, and each matrix and vector is encoded as polynomial, and the polynomial corresponding to the product of the matrix and vector is determined based on polynomial multiplication, and then each dimension element in the product vector of the matrix and vector is extracted from the polynomial of multiplication result.The implementation can improve the efficiency of the matrix security multiplication operation based on homomorphic encryption.

To provide semiconductor and electronic devices with small circuit area and low power consumption. [Solution] The arithmetic circuit MAC1 is a circuit that performs a sum-of-products operation on a plurality of first data held in a plurality of memory cells described later and a plurality of input second data, and performs an activation function operation using the result of the sum-of-products operation, and comprises a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV. The memory cell array CA comprises memory cells AMx[1] to AMx[m] (where m is an integer of 1 or more), memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMR[1] to AMr[m]. In the memory cell array CA, each memory cell is arranged in a matrix of 2m rows and 2 columns.

A number of examples are described for providing an artificial neural network system with analog and digital arrays. In certain examples, the analog and digital arrays are coupled to shared bit lines. In other examples, the analog and digital arrays are coupled to separate bit lines.

A 3D compute in-memory accelerator system and method for efficient inference of Mixture of Experts (MoE) neural network models are provided. The system includes multiple compute in-memory cores, each including multiple hierarchies of in-memory computational cells. One or more hierarchies of in-memory computational cells correspond to expert submodels of the MoE model. One or more expert submodels are selected for activation propagation based on a function-based routing, and the corresponding hierarchies of experts are activated based on the function. In one embodiment, the function is a hash-based hierarchical selection function used for dynamic routing of input and output activations. In one embodiment, the function is applied to select a single expert or multiple experts using an input database or layer activation-based MoE for activation of a single hierarchical layer. Furthermore, the system can be configured as a multi-model system with single expert model selection or a multi-model system with multiple expert selection.

To provide a semiconductor device with a novel structure.SOLUTION: A calculation block 21_O includes a storage circuit part 30 that holds a plurality of pieces of first weight data, a calculation circuit 45, a first switch circuit (switch circuit 42), and a second switch circuit (switch circuit 44). The first switch circuit applies any of the pieces of first weight data to a first wire WOL. The second switch circuit applies any of the applied first weight data or second weight data applied to a second wire WEL to a first calculation circuit (calculation circuit 45). A calculation block 21_E includes a storage circuit part 30 that holds a plurality of pieces of second weight data, a second calculation circuit (calculation circuit 45), a third switch circuit (switch circuit 42), and a fourth switch circuit (switch circuit 44). The third switch circuit applies any of the pieces of second weight data to the second wire WEL. The fourth switch circuit applies any of the applied first weight data or the second weight data applied to the second wire to the second calculation circuit.SELECTED DRAWING: Figure 1

A fractional frequency synthesizer, a fractional PLL, and a method for generating a fractional frequency signal based on a reference signal are provided. An example fractional frequency synthesizer includes a multi-phase clock generator configured to generate a clock vector comprising a plurality of clock signals, each oscillating according to a fractional frequency in relation to the reference frequency and each clock signal offset by a phase offset. The fractional frequency synthesizer includes multi-phase divider circuitry configured to select a clock signal from the clock vector to generate a fractional frequency feedback signal. An accumulator configured to increment a count and a rollover detector configured to determine a rollover value associated with a rollover event on the accumulator are further included. A clock signal is selected based on the rollover value and the fractional frequency feedback signal is generated based at least in part on the selected clock signal.

A multiply-accumulate (MAC) computation circuit includes: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first analog-to-digital conversion (ADC) circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.

A device for performing matrix-vector multiplication of a matrix and a vector, the device comprising a memory crossbar array comprising: a plurality of row lines; a plurality of column lines; and a plurality of junctions disposed between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistance element and an access element for accessing the programmable resistance element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of a plurality of switching elements. The write-assist wires are connectable to the plurality of column lines via the plurality of switching elements.

To provide a semiconductor device which performs calculation by using a transistor having a large S value or operation in a subthreshold region of the transistor.SOLUTION: The transistor includes an oxide semiconductor layer having a channel formation region, a gate electrode having a region overlapping with the oxide semiconductor layer with an insulating layer interposed therebetween, and a first conductive layer having a region overlapping with the oxide semiconductor layer with a ferroelectric layer interposed therebetween. In particular, the ferroelectric layer has a crystal, and the crystal has a crystal structure that exhibits ferroelectricity.SELECTED DRAWING: Figure 1

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

Various mechanisms for performing sequential vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication for each bit order of values ​​in an input vector. The first vector-matrix multiplication operation for each bit order may generate an analog output. Each analog output generated by the vector-matrix multiplication may be converted to one or more digital bit values, and the one or more digital bit values ​​may be sent to a second vector-matrix multiplication operation.