199results about "Computing operations for multiplication/division" patented technology

Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes first computation in memory (CIM) cells configured as a first kernel for a neural network computation, the first set of CIM cells comprising one or more first columns and a first plurality of rows of a CIM array. The apparatus also include a second set of CIM cells configured as a second kernel for the neural network computation, the second set of CIM cells comprising the one or more first columns and a second plurality of rows of the CIM array. The first plurality of rows may be different than the second plurality of rows.

Disclosed are devices, systems, and methods for performing time-domain multiply-and-accumulate (MAC) computations. In some embodiments, an apparatus comprises first and second circuits. The first circuit is configured to (a) perform a first multiplication in response to a trigger signal, the first multiplication being a product of a first value and a second value, and (b) generate a completion signal, wherein the completion signal indicates completion of the first multiplication. The second circuit is coupled to the first circuit and is configured to (i) perform a second multiplication in response to the completion signal, the second multiplication being a product of a third value and a fourth value, and (ii) generate an output signal, wherein the output signal indicates completion of the second multiplication. An amount of elapsed time between the trigger signal and the generation of the output signal represents a sum of the first and second multiplications.

Disclosed is a neural network computing device. The neural network computing device includes a neural network accelerator including an analog MAC, a controller controlling the neural network accelerator in one of a first mode and a second mode, and a calibrator that calibrating a gain and a DC offset of the analog MAC. The calibrator includes a memory storing weight data, calibration weight data, and calibration input data, a gain and offset calculator reading the calibration weight data and the calibration input data from the memory, inputting the calibration weight data and the calibration input data to the analog MAC, receiving calibration output data from the analog MAC, and calculating the gain and the DC offset of the analog MAC, and an on-device quantizer reading the weight data, receiving the gain and the DC offset, generating quantized weight data, based on the gain and the DC offset.

A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple tiers of in-memory compute cells (106). One or more tiers of in-memory compute cells correspond to an expert sub-model of the MoE model. One or more expert sub¬ models are selected (106A) for activation propagation based on a function-based routing (115), the tiers of the corresponding experts being activated based on this function. In one embodiment, this function is a hash-based tier selection function used for dynamic routing of inputs and output activations. In embodiments, the function is applied to select a single expert or multiple experts with input data- based or with layer-activation-based MoEs for single tier activation. Further, the system is configured as a multi-model system with single expert model selection or with a multi-model system with multi-expert selection.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A simulation system and method for implementing a model based on an iterative neural network, the system comprising: a simulation vector-matrix multiplication circuit that encodes a weight matrix of the model based on the iterative neural network; and an analog non-linear circuit that encodes a non-linear function arranged in a feedback loop configured to return an output signal from the non-linear circuit as input to the vector-matrix multiplication circuit, wherein the system is configured to output a solution vector of values of the model based on the iterative neural network upon convergence of the system.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes a first arithmetic portion that performs a digital arithmetic operation and a second arithmetic portion that performs an analog arithmetic operation. In an arithmetic operation of a convolutional neural network, the first arithmetic portion executes an arithmetic operation of a convolution layer, and the second arithmetic portion executes an arithmetic operation of a fully connected layer. The convolution layer often uses the same filter value repeatedly; thus, the first arithmetic portion is configured to execute a plurality of product-sum operations at the same time with single input of the same filter value and with input of a plurality of pieces of data to be subjected to convolution processing. Since the fully connected layer needs weight coefficients as many as the product of the number of pieces of input data and the number of pieces of output data, the second arithmetic portion has a structure in which arithmetic cells arranged in a matrix retain the weight coefficients and the input data is transmitted in the row directions, whereby the output data is output in the column directions.

The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line (22) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I1, I2, I3) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I1, I2, I3) into the third line (26) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element (28) with a control terminal which is connected to the second line (24) of the corresponding column; wherein input voltages (U1, U2, U3) corresponding to components of the input vector are applied (110) to the first lines; wherein for each column: a ramp voltage (V1, V2, V3) is applied (120) to the second line assigned to the column, the level of which is increased with time (130); a total current is detected at the third line assigned to the column and a time period elapsed since a start time of the level increase of the corresponding ramp voltage is determined (150) until the magnitude of the total current reaches a certain current magnitude threshold (Ig) (140); and a component of the output vector corresponding to the column is determined (170) based on the elapsed time period (t1, t2, t3).

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

The invention relates to the technical field of semiconductors, and provides an arithmetic unit and method based on a ferroelectric field effect transistor and a storage and calculation switch array. The arithmetic unit comprises a 1F1R unit, a shared capacitor, a bit line and a word line; each column of 1F1R units comprises a plurality of 1F1R units which are arranged in parallel; each 1F1R unit comprises a first resistor and a ferroelectric field effect transistor, the first resistor comprises a first end and a second end, and the ferroelectric field effect transistor comprises a grid electrode, a source electrode and a drain electrode; the grid electrode of each ferroelectric field effect transistor is connected with the word line, the source electrode is connected with the second end of the first resistor, and the drain electrode is connected with the bit line; the shared capacitor comprises a first end and a second end, the first end of the first resistor of each column of 1F1R units is connected with the first end of the shared capacitor, and the second end of the shared capacitor is grounded. According to the scheme, compact and low-power-consumption memory operation can be realized, the energy consumption of the whole array is reduced on the basis of ensuring the energy efficiency, and meanwhile, a large-area coding and decoding circuit is avoided due to the single-bit data bit width.

To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.SOLUTION: A photonic neural network system 10 for convolving and adding frames of data includes a first sensor display device 14 and a second sensor display device 26. Each sensor display device comprises an array of transmit-receive modules. Each transmit-receive module comprises a light sensor element, a light transmitter element, and a memory bank. A radial modulator device 20 is positioned where transmission of light fields including frames of data are Fourier transformed. Filters implemented by modulator elements of the radial modulator device 20 convolve fields of light including the frames of data, which are then sensed on a pixel-by-pixel basis by the light sensor elements, which accumulate charges, thus sum pixel values of sequential convolved frames of data.SELECTED DRAWING: Figure 1

To detect anomalies in an excellent-accuracy and high-speed manner with a simplified configuration.SOLUTION: An anomaly detection device comprises an input unit, a reservoir unit, an output unit, and a determination unit. The input unit outputs a plurality of intermediary signals in accordance with a time-series input signal detected by observing an observation target device. The reservoir unit acquires the plurality of intermediary signals, and outputs a plurality of output signals each having a waveform having reproducibility in respect to a waveform of the input signal. The output unit generates a plurality of multiplication signals by multiplying output weights preset with respect to each of the plurality of output signals, and generates an integral signal obtained by time integration through adding up the plurality of multiplication signals. The determination unit determines whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a preset threshold, and outputs a determination signal representing a determination result. The output weights represent a positive prescribed value or a negative prescribed value, and are respectively set for the plurality of output signals.SELECTED DRAWING: Figure 2

The invention relates to the technical field of computers, and discloses a computer memory data processing system comprising a calculation task compiling module used for determining physical setting parameters according to a calculation task and generating a preset target evolution path; the physical calculation execution module is used for performing state evolution according to the physical setting parameters; the dynamic feedback control module is used for monitoring the actual evolution state and generating a calibration signal according to the deviation between the actual evolution state and a preset target evolution path so as to dynamically adjust driving; and the result decoding module is used for converting the steady-state physical quantity into a calculation result after the system reaches a stable equilibrium state. By constructing closed-loop feedback control, evolution deviation generated by non-ideal factors of a physical system is corrected in real time, it can be effectively guaranteed that actual state evolution of physical calculation accurately tends to a preset ideal path, and therefore the accuracy and reliability of data processing through the physical process are remarkably improved.

The present invention discloses a method, device, equipment, and storage medium for correcting the flatness of a DA chip. This method utilizes a lookup table approach to correct the flatness of each DA chip frequency point, making it more convenient and accurate. Using an FPGA to process the flatness algorithm effectively increases computational speed and correction accuracy. This method achieves precise flatness correction at each DA chip frequency point, improving hardware performance. For hardware platforms, it offers high operability and low power consumption. It is worthy of widespread adoption.

An analog-digital hybrid deep neural network computing device according to one embodiment includes a control unit, an analog processing unit, a digital processing unit, and a multi-channel bus, and in which the algorithm includes a plurality of layers for computation, and an analog MAC computation in an analog computing manner is performed for a first group of layers including one or more layers among the plurality of layers in the analog processing unit and a digital MAC computation in a digital computing manner is performed for a second group of layers, which is the remaining layers except for the first group of layers, in the digital processing unit.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

A semiconductor device capable of performing product-sum operations with reduced power consumption is provided. [Solution] A semiconductor device has first and second cells, a first circuit, and first to third wirings. Each of the first and second cells has a capacitance, and a first terminal of each capacitance is electrically connected to a third wiring. Each of the first and second cells has a function of flowing a current corresponding to a potential held at a second terminal of the capacitance to the first and second wirings. The first circuit is electrically connected to the first and second wirings, and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wire changes, the amount of current in the first wire changes from I1 to I3, and the amount of current in the second wire changes from I2 to I4, the first circuit generates a current of I1-I2-I3+I4. Note that the change in the third wire is achieved by first inputting a reference potential to the third wire, and then inputting a potential corresponding to internal data or information obtained by a sensor.

Provided is a semiconductor device that can retain data to be used for computation for a long period of time. The semiconductor device comprises a computation cell and a drive cell. The computation cell and the drive cell each include first to third transistors, first and second capacitor elements, and a first amplification circuit. A first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplification circuit, and a first terminal of the first capacitor element. A second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplification circuit, and a first terminal of the second capacitor element. The first amplification circuit functions as a buffer circuit that outputs an analog potential. Electric charge is replenished to the first terminal of the second capacitor element by the first amplification circuit on the basis of the electric potential of the first terminal of the first capacitor element, thereby preventing leakage current between the source and the drain of each of the first transistor and the second transistor.

Numerous embodiments are disclosed for an input circuit for an analog neural memory in a deep learning artificial neural network.

To provide configurable input blocks and output blocks and a physical layout for analog neural memory systems that utilize non-volatile memory cells.SOLUTION: In a vector by matrix multiplication (VMM) system 3400, input blocks 3409, 3410 can be configured to support different numbers of arrays 3401 to 3404 arranged in a horizontal direction, and output blocks 3411, 3412 can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.SELECTED DRAWING: Figure 34

A system comprises an analog resistive processing unit (RPU) system, and one or more processors. The analog RPU system comprises an array of RPU cells. The one or more processors are configured to: configure the analog RPU system to implement a convolutional neural network comprising a convolutional layer comprising at least one kernel matrix; program the at least one array of RPU cells to store a transformed kernel matrix which is generated by applying a first transformation process to the kernel matrix using a first predefined transformation matrix; and utilize the analog RPU system to perform an analog convolution operation by performing analog matrix-vector multiplication operations using the transformed kernel matrix and input vectors of a transformed data matrix, to thereby generate a transformed convolution output matrix, wherein the transformed data matrix is generated by applying a second transformation process to a data matrix using a second predefined transformation matrix.

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] An arithmetic circuit having circuits MC and MCr, wherein circuit MC has a holding node nd1, and circuit MCr has a holding node nd1r. Circuits MC and MCr are electrically connected to input wirings X1L and X2L and wirings OL and OLB, respectively, and each of circuits MC and MCr holds first and second potentials corresponding to first data in its respective holding node. When a potential corresponding to second data is input to input wirings X1L and X2L, circuit MC outputs a current to one of wirings OL or OLB, and circuit MCr outputs a current to the other of wirings OL or OLB. The current that circuits MC and MCr output to wirings OL or OLB is determined according to the first and second potentials held in the holding nodes nd1 and nd1r.

A memory - in - computing bit cell is provided, which includes a pair of cross - coupled inverters for storing stored bits. The memory - in - computing bit cell includes a logic gate for multiplying the stored bits by input vector bits. The logic gate includes FET transistors. The source terminal of the FET transistor is connected to the output node of the cross - coupled inverter, the gate terminal of the FET transistor is connected to the input vector bit, and the drain terminal of the FET transistor is connected to the first plate of a capacitor. The second plate of the capacitor is connected to a read bit line.