26results about "Computing operations for multiplication/division" patented technology

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

The embodiment of the present specification provides a kind of matrix multiplication security calculation method and device, it is suitable for the multi-party security calculation architecture of two participants, one party holds matrix, another party holds vector, and the product of the security calculation of the matrix and vector is calculated.The embodiment of the present specification makes full use of the characteristics that efficient homomorphic encryption mode can process polynomial data under the multi-party security calculation architecture, and each matrix and vector is encoded as polynomial, and the polynomial corresponding to the product of the matrix and vector is determined based on polynomial multiplication, and then each dimension element in the product vector of the matrix and vector is extracted from the polynomial of multiplication result.The implementation can improve the efficiency of the matrix security multiplication operation based on homomorphic encryption.

To provide semiconductor and electronic devices with small circuit area and low power consumption. [Solution] The arithmetic circuit MAC1 is a circuit that performs a sum-of-products operation on a plurality of first data held in a plurality of memory cells described later and a plurality of input second data, and performs an activation function operation using the result of the sum-of-products operation, and comprises a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV. The memory cell array CA comprises memory cells AMx[1] to AMx[m] (where m is an integer of 1 or more), memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMR[1] to AMr[m]. In the memory cell array CA, each memory cell is arranged in a matrix of 2m rows and 2 columns.

A multiply-accumulate (MAC) computation circuit includes: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first analog-to-digital conversion (ADC) circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.

A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

This invention relates to a method for generating the dot product of two floating-point vectors in semiconductor hardware. The method accesses the elements of the two vectors and performs multiplication in hardware. Before performing the multiplication, the exponents of the elements may be checked to determine if the result exceeds the range of a fixed-point accumulator; if so, the multiplication of that element is skipped. The elements that have been optionally checked are multiplied. The resulting product is converted to a fixed-point number and summed using an accumulator. The dot product hardware may be part of an integrated semiconductor implementation of a neural network.

A multiply-accumulator (MAC) circuit includes: a plurality of multipliers each comprising: a field-effect transistor configured to apply an intermediate voltage to a node; a pair of resistive devices having resistance values determined based on the intermediate voltage applied to one ends connected to the node and weight setting voltages applied to the other ends; and a capacitor configured to be charged and discharged with an electric charge by receiving a voltage generated in the node based on a combined resistance value of the pair of resistive devices and input voltages applied individually to the other ends of the pair of resistive devices in response to individual resistance values of the pair of resistive devices being determined; and an output line configured to output a voltage based on electric charges charged to and discharged from the plurality of multipliers.

To provide a word line decoder, a control gate decoder, a bit line decoder, a low voltage row decoder, and a high voltage row decoder and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system.SOLUTION: Combined word line and control gate decoder 4100 comprises: a PMOS transistor 4102; an NMOS transistor 4103; row address signals 4104; vertical input word lines 4105; a horizontal word output line 4106 which is coupled to word lines of VMM arrays; an inverter 4107; switches 4108 and 4112; and an isolation transistor 4109, and receives a control gate input 4110 CGIN0 and outputs a control gate line 4111 CG0. The word line output 4106 WL0 and control gate output 4111 CG0 are selected or de-selected at the same times by decoding logic that controls a NAND gate 4101.SELECTED DRAWING: Figure 41

A method for a vector computing device, for example a vector-matrix multiplier, comprising: supplying a first set of a first input quantity, for example in the form of a bit vector, to the vector computing device; charging a capacitor device with a first output current, which characterizes a product, for example a scalar product, of a multiplication of the first set of the first input quantity with a second input quantity by means of the vector computing device; partially discharging the capacitor device by a predefinable amount; repeating at least one of the aspects of supplying and charging, optionally also of discharging, using at least a second set of the first input quantity.

A non-volatile memory device is configured for in-memory computation of discrete Fourier transformations and their inverses. The real and imaginary components of the twiddle factors are stored as conductance values of memory cells in non-volatile memory arrays having a cross-point structure. The real and imaginary components of inputs are encoded as word line voltages applied to the arrays. Positive and negative valued components of the twiddle factors are stored separately and positive and negative of the inputs are separately applied to the arrays. Real and imaginary parts of the outputs for the discrete Fourier transformation are determined from combinations of the output currents from the arrays.

The invention relates to a method and a device for data processing and to a use. In a method for data processing, an analog electrical input signal (4) is time-continuously multiplied by a matrix (A, B), thereby allowing a time-continuous projection of the input signal into a function space.

Provided is a highly reliable semiconductor device capable of multiplication. This semiconductor device comprises first and second cells and a drive circuit. Each of the first cell and the second cell includes first to third transistors and a resistance change element. The drive circuit includes a first input terminal, a second input terminal, and an output terminal. The resistance change element includes a conductive layer and an MTJ element. The conductive layer includes a first region connected to one of the source and the drain of the first transistor, a second region connected to one of the source and the drain of the second transistor, and a region in contact with a free layer of the MTJ element located between the first region and the second region. A fixed layer of the MTJ element includes a third region connected to one of the source and the drain of the third transistor. The drive circuit has a function of outputting to the output terminal, as a signal, information corresponding to a difference between a current flowing between the first cell and the first input terminal and a current flowing between the second cell and the second input terminal.

We provide electronic devices for use in artificial neuronal networks. [Solution] The electronic device 100, which is an artificial neural network, has an artificial neural array (ANA) 111, a row decoder 112, a column decoder 113, an input circuit 114, an output circuit 115, an analog signal processing circuit 116, and a memory 130. The ANA 111 has multiple circuits 10, 11, multiple wires WW, WB, DL, RB, and one wire RD. The circuits 10 are arranged in an n-row m-column array, and the circuits 11 are arranged in an n-row 1-column array. The wires WW are electrically connected to the row decoder, and the wires WB are electrically connected to the column decoder. The row decoder and column decoder are peripheral circuits for writing weights or thresholds to the circuit 10. The input circuit writes data DIN to the ANA 111, and the output circuit processes the analog signal input via wires RB and RD to generate data DOUT.

The application discloses a mixed-precision dequantization system and method for in-memory computing, and belongs to the field of integrated circuits and artificial intelligence hardware. The system comprises a digital domain pre-alignment module, an analog in-memory computing core and a general dequantization DQ-SIMD unit. The pre-alignment module completes floating-point activation processing and generates an activation value compensation term. The analog in-memory computing core completes multiplication and accumulation and eliminates physical offset errors based on a 1T1R single-terminal array. The dequantization unit realizes fixed-point to floating-point conversion and asymmetric quantization inverse transformation through a three-stage pipeline. The application proposes a single-terminal storage scheme of non-negative shift mapping in view of the core contradiction between mixed-precision computing requirements and the non-negativity of device conductance when deploying a large language model inference on a 1T1R structure RRAM array. The single-terminal storage scheme is matched with a double-error elimination mechanism of software and hardware cooperation to realize single-terminal storage of signed weights by superimposing a fixed offset in the analog domain and to eliminate physical errors introduced by the offset in real time through a pipeline circuit in the digital domain.

Numerous examples of artificial neural networks comprising vector matrix multiplication arrays utilizing analog inputs are disclosed. In one example, a system comprises a vector matrix multiplication array comprising an array including a plurality of non-volatile memory cells arranged in rows and columns, a capacitor having a first terminal and a second terminal coupled to a common potential, a row decoder for enabling application of an input signal to the first terminal of the capacitor in response to an address, and a buffer coupled to the first terminal of the capacitor for generating an output voltage for each row of the vector matrix multiplication array.

An analog multiplier circuit for performing multiply and scaling operations comprises a differential amplifier, at least two storage circuits, a summing circuit; and an exponentiating circuit. In response to receiving a first control signal, receiving as input an analog signal output by the differential amplifier and storing a value derived from the analog signal. In response to receiving a second control signal, outputting a storage analog signal derived from the stored value. The summing circuit receives storage analog signals from the storage circuits, and outputs an analog signal substantially proportional to a sum of the input storage analog signals.

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present invention. The circuit includes a capacitor charging / discharging module and an error amplification module electrically connected to the capacitor charging / discharging module. The capacitor charging / discharging module is configured to receive first, second and third signals external to the capacitor charging / discharging module, and to output a reference signal and a feedback signal. The error amplification module is configured to receive the reference and feedback signals and output a target signal to the capacitor charging / discharging module based on the received reference and feedback signals. The first, second and third signals are all analog signals, and in a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current / voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current / voltage converter circuit; an output terminal of the current / voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.

A transistor having a large S value or a semiconductor device performing calculation utilizing a transistor operation in a subthreshold region is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a gate electrode including a region overlapping with the oxide semiconductor layer with an insulating layer therebetween, and a first conductive layer including a region overlapping with the oxide semiconductor layer with a ferroelectric layer therebetween. In particular, the ferroelectric layer includes a crystal having a crystal structure exhibiting ferroelectricity.

To provide semiconductor and electronic devices that can perform calculations with low power consumption. [Solution] The arithmetic circuit is a semiconductor device having an array unit ALP and a circuit AFP, wherein the array unit ALP has circuits MP[1,j] to MP[m,j]. The circuit AFP also has a circuit ACTF[j], which has a capacitor CRE, a circuit AC, terminal T1, and terminal T2. Each of the circuits MP[1,j] to MP[m,j] is electrically connected to wiring XLS[1] to wiring XLS[m]. Wiring OL[j] is electrically connected to terminal T1, terminal T1 is electrically connected to the first terminal of capacitor CRE, wiring OLB[j] is electrically connected to terminal T2, terminal T2 is electrically connected to the second terminal of capacitor CRE. The voltage (charge) stored in capacitor CRE is input to circuit AC, and the amount of voltage (charge) stored in capacitor CRE is sensed.

Provided is a semiconductor device capable of calculating an echo state network. The semiconductor device has first to fifth circuits and first to third cells. The first circuit has a function of transmitting a first value to the first cell and a function of transmitting a second value to the second cell. The second circuit has a function of transmitting a third value to the third cell. The third circuit has a function of transmitting a fourth value to the first cell. The first cell has a function of adding the product of the first value and the fourth value, as a current, to a first current flowing through an input terminal of the fourth circuit. The fourth circuit has a function of generating a fifth value corresponding to the first current, and a function of transmitting the fifth value to the second cell and the third cell. The second cell has a function of adding the product of the second value and the fifth value, as a current, to the first current flowing through an input terminal of the fifth circuit. The third cell has a function of adding the product of the third value and the fifth value, as a current, to a second current flowing through the input terminal of the fifth circuit.