15 results about "Linear circuit" patented technology

A simulation system and method for implementing a model based on an iterative neural network, the system comprising: a simulation vector-matrix multiplication circuit that encodes a weight matrix of the model based on the iterative neural network; and an analog non-linear circuit that encodes a non-linear function arranged in a feedback loop configured to return an output signal from the non-linear circuit as input to the vector-matrix multiplication circuit, wherein the system is configured to output a solution vector of values of the model based on the iterative neural network upon convergence of the system.

To provide a nonlinear compensation device, a nonlinear compensation method, and a program for appropriately updating a parameter even when a reference signal cannot be used every time.SOLUTION: A nonlinear compensation device 200 includes a plurality of nonlinear circuits 201 - 1 to 201 - N that output signals obtained by adding nonlinear characteristics to reception signals transmitted by a transmitter and received by a receiver, a linear circuit 202 that outputs a sum of values obtained by multiplying outputs of the plurality of nonlinear circuits by weighting coefficients as a compensation signal, and a first learning unit 204 that sets at least one of parameters of the nonlinear characteristics of the plurality of nonlinear circuits and the weighting coefficients of the linear circuit on the basis of an error between the compensation signal and a reference signal. And a second learning unit 203 that changes each weight coefficient of the linear circuit 202.SELECTED DRAWING: Figure 3

The application provides a self-powered circuit of a switching power supply and the switching power supply. The self-powered circuit comprises a first linear voltage stabilizing circuit connected between a common connection end of a main power tube and an auxiliary power tube and a power supply capacitor; a second linear voltage stabilizing circuit connected in parallel with the second linear voltage stabilizing circuit; and an adjusting circuit connected with the second linear voltage stabilizing circuit, which generates an adjusting voltage to adjust a first charging current flowing through the second linear voltage stabilizing circuit when the second linear voltage stabilizing circuit is turned on. When the switching power supply is started, the first linear voltage stabilizing circuit is turned on, and the power supply capacitor is charged. When a PWM signal generated by a control chip of the switching power supply is valid, the second linear voltage stabilizing circuit is turned on. The application can save power supply loss and optimize system EMI.

A device includes an adaptive power limitation circuit configured to automatically determine active phases of a DCDC converter based upon power level of the DCDC converter. The adaptive power limitation circuit includes a translinear circuit configured to convert the power level of the DCDC converter to a current level and a clamping circuit, operatively connected to the translinear circuit, configured to clamp a maximum output current of the adaptive power limitation circuit to a predetermined value.

To provide a square root circuit capable of generating a highly accurate output value by suppressing and reducing the influence of a base current error.SOLUTION: In the square root circuit, a translinear circuit is configured by the first transistor 1 to the fourth transistor 4 using NPN bipolar transistors, and the fifth transistor 5 to the seventh transistor 7 using NMOS transistors are provided so that a base current error of the first transistor 1 to the fourth transistor 4 does not directly appear in the output current IOUT, and even if there is a base current error, the output current IOUT accurately proportional to the square root of the input current IIN is obtained.SELECTED DRAWING: Figure 1

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a band-gap reference circuit with subrange piecewise linear compensation and a control method. According to the invention, the core circuit realizes temperature segmentation processing by superposing the current with positive and negative temperature coefficients, combining with the digital-to-analog converter and finely adjusting the proportion of the current with the positive and negative temperature coefficients in different temperature intervals through the comparator. On the basis, a sub-range linear circuit is introduced into each temperature sub-interval, the influence of the second-order temperature coefficient on the output reference voltage is effectively restrained, and therefore the temperature stability is improved. And in order to ensure that the residual influence of the first-order temperature coefficient can be further eliminated after compensation of the sub-temperature sections, the DAC is adopted to realize detailed adjustment of the first-order temperature coefficient, and the robustness of the circuit to process deviation is improved.

In a general aspect, a superconducting quantum processing circuit includes a tunable qubit device. The tunable qubit device includes a circuit loop configured to receive, during operation of the tunable qubit device, a magnetic flux that controls a qubit frequency of the tunable qubit device. In some aspects, the circuit loop consists of: a single non-linear circuit element and one or more linear circuit elements. The single non-linear circuit element is a Josephson junction connected between a first circuit node and a second circuit node. The one or more linear circuit elements includes a linear inductor connected in parallel with the Josephson junction between the first circuit node and the second circuit node.

The utility model relates to the technical field of switching power supplies, and discloses a high-efficiency adjustable linear circuit, which comprises a BACK circuit, a control circuit, an MCU and a low dropout regulator LDO, the BACK circuit comprises a DC / DC chip, the VCCOUT end of the DC / DC chip is electrically connected with the low dropout regulator LDO, the low dropout regulator LDO comprises a triode Q5, a triode M3, a capacitor C81, a resistor R65 and a resistor R59, and the triode Q5, the triode M3, the capacitor C81, the resistor R65 and the resistor R59 are electrically connected with the control circuit. The VCCOUT end of the DC / DC chip is conducted with the C ends of the triode Q5 and the triode M3, the E end of the triode Q5 is connected to the OUT-end through a resistor R65, the E end of the triode M3 is connected to the OUT + end, and the OUT + end is connected with the control circuit. The circuit is low in power consumption and high in efficiency, voltage and current output by the low dropout linear stabilizer LDO are in a linear relation, stability and reliability of the circuit are improved, voltage drop can be reduced, efficiency can be improved, and heating can be reduced due to the fact that following type dropout voltage control is adopted.

The application discloses a high-precision bipolar linear high-voltage regulating circuit and belongs to the technical field of linear regulating circuits. The high-precision bipolar linear high-voltage regulating circuit comprises an operational amplifier U1, triodes Q1-Q4, a negative high-voltage end -HV, a positive high-voltage end +HV, an input control voltage end VSET and an output end VOUT. The positive input end of the operational amplifier U1 is connected with the input control voltage end VSET in series with a resistor R1, the negative input end is grounded in series with a resistor R2, the output end and the negative input end are connected with a capacitor C1 in parallel, the output end is connected with the emitter of the triode Q3, the base of the triode Q3 is grounded, the collector of the triode Q3 is connected with the base of the triode Q4, the emitter of the triode Q4 is directly connected with the negative high-voltage end -HV, the collector of the triode Q4 is connected with one end of a resistor R5 and the emitter of the triode Q2, and the other end of the resistor R5 is connected with one end of a resistor R6. The high-precision bipolar linear high-voltage regulating circuit realizes a bipolar, adjustable, high-precision and high-voltage output linear circuit at low cost.

A terahertz (THz) frequency multiplier device is disclosed. The device includes a first metallic waveguide that receives, in its first interior space, an input electromagnetic field oscillating at an input frequency. A dielectric waveguide extends partly within the first interior space and is terminated with an output port located outside the first interior space. A nonlinear circuit element is coupled to the dielectric waveguide in the first interior space. The element is excited by the input field to generate an electrical current containing harmonics of the input field and inducing an output electromagnetic field within the dielectric waveguide at an output THz frequency corresponding to one of the harmonics. A second metallic waveguide receives a portion of the dielectric waveguide extending outside the first interior space, the second waveguide being configured to impede propagation of the input field while allowing propagation of the output field toward the output port.

The application discloses a model order reduction method, system, terminal and computer readable storage medium of a multi-port linear circuit. The method comprises the following steps: obtaining a to-be-reduced circuit model, reducing the number of ports of the to-be-reduced circuit model according to a port reduction strategy, and obtaining a target circuit model; based on the target circuit model, a residual module and a tensor mapping structure, a target mapping equation is constructed, the tensor mapping structure is used to represent the correlation between the to-be-reduced circuit model and the target circuit model, and the residual module is used to predict the corresponding output according to the input; training data sets are generated according to the to-be-reduced circuit model, the residual module and the tensor mapping structure in the target mapping equation are trained, and a trained target mapping equation is obtained; and a reduced order result is generated according to the target circuit model and the trained target mapping equation. The application can use the trained target mapping equation on the basis of the target circuit model, so that the accuracy of the multi-port model after order reduction can be improved.

The invention relates to a non-inductive chaotic neuron circuit based on a second-order flow control memristor, and belongs to the technical field of neuromorphic calculation and nonlinear circuits. The circuit adopts a very simple parallel structure and is only composed of a current source, a capacitor and a second-order flow control local active memristor. According to the memristor, through nonlinear coupling of two internal state variables, local active characteristics are provided, and meanwhile, the memristor and a capacitor naturally form a three-order dynamic system together. According to the design, an external complex topology required by a traditional neuron circuit is replaced by the complexity of the device, and high-level neurodynamics behaviors such as chaos and tufting can be realized without an inductance element. Simulation results prove that the circuit can generate stable chaotic attractors under specific parameters. According to the invention, the implementation complexity of neuromorphic hardware is obviously reduced, and the method has the characteristics of simple structure and rich functions, and has a better application prospect in the field of high-integration brain-like chips.

Method and apparatus for a magnetic sensor device having a magnetic field sensing element to generate an output signal and a signal processing module coupled to the magnetic field sensing element, the signal processing module including linearization module having an analog translinear circuit.

A method and a system for large-scale linear circuit simulation, a circuit simulator and a storage medium are provided. The method includes: constructing ordinary differential equations for a linear circuit and converting the ordinary differential equations into a large-scale sparse system of linear equations; performing column reordering on a coefficient matrix of the large-scale sparse system of linear equations, obtaining a pre-reordered matrix; utilizing partitioning partition algorithm to perform row-column reordering, obtaining a doubly bordered-block diagonal matrix; employing a plurality of compute nodes, solving for local Schur complements of each of the distributed nodes, and summing up the local Schur complements to obtain a global Schur complement; solving for states of each of the distributed nodes at a current time step; and converting solution results from all time steps of each of the distributed nodes into a simulation result. The method significantly improves simulation efficiency while ensuring smooth simulation execution.