Low stray linear circuit structure applied to fraction frequency division phase-locked loop

Abstract

The invention discloses a low stray linear circuit structure applied to a fraction frequency division phase-locked loop, which includes a first phase frequency detector, a first charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, a second phase frequency detector, and a second charge pump. An output end of the second phase frequency detector is connected to an input end of the second charge pump. The second phase frequency detector generates a UP3 signal and a DN2 signal having phase differences according to obtained two paths of reference signals to control the second charge pump to generate a second bias current. An input end of the loop filter is connected to an output end of the first charge pump and an output end of the second charge pump. A first bias current and the second bias current are combined to form an input current of the loop filter. An output end of the loop filter is connected to an input end of the voltage controlled oscillator so as to input voltage signals to the voltage controlled oscillator according to the input current. The noise aliasing effect caused by the nonlinearity of PFD/CP can be eliminated, the in-band noise is reduced, and reference stray is not deteriorated.

Description

technical field [0001] The invention relates to the technical field of radio frequency integrated circuits, in particular to a low stray linearization circuit structure applied to a fractional frequency division phase-locked loop. Background technique [0002] In the wireless communication transmitter / receiver, the phase-locked loop is an important module, which provides the clock for data transmission and reception. Among them, the charge pump phase-locked loop is the first choice for the phase-locked loop architecture because of its wide capture range. In the charge pump phase-locked loop, the lock time is an important indicator. The loop lock time is determined by the loop bandwidth. A wide loop bandwidth corresponds to a small lock time. However, the loop bandwidth generally only takes the reference signal frequency 1 / 20 to 1 / 10 of that, so a large reference signal frequency is necessary for designing fast locking. For the application of multiple channels, small resolut...

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Problems solved by technology

However, the fixed phase difference will cause the charge pump to periodically charge and discharge the loop filter, so that the voltage control waveform of the VCO has a large ripple, which deteriorates the reference spurious

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