14results about How to "Reduce circuit area" patented technology

The invention relates to the field of in-memory calculation, and provides an in-memory calculation method and device of a floating-point number exponent and a storage medium, the method is applied to an in-memory calculation structure of the floating-point number exponent, the structure comprises a static random access memory (SRAM) row, a first delay chain and a maximum value searching and difference value generating module, the first delay chain is formed by connecting N in-memory computing units (CIMs) in series; according to the in-memory calculation method of the floating-point number index, an input floating-point number index and a weight floating-point number index are divided into a high part and a low part, maximum value searching and difference value generation are carried out on the high part and the low part respectively, and double-edge index summation calculation is carried out on a rising edge and a falling edge of an output pulse. The amount of data needing to be stored and the number of calculation units are reduced, the circuit area of calculation in the floating-point number index memory can be reduced, and the calculation time and the calculation power consumption can be reduced.

The present application discloses a circuit for detecting data correlation, including: a serial-to-parallel conversion module, receiving a serial data signal and a reference data signal, and converting the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; a voltage detection module, receiving the parallel data signal, and converting the parallel data signal into an analog voltage detection signal; a correlation output module, suitable for comparing the voltage detection signal with a first threshold voltage and a second threshold voltage to determine the correlation between the serial data signal and the reference data signal. By determining the correlation of data in an analog comparison manner, a resistor and a comparator are used to replace the accumulator and the numerical comparator in the existing digital correlator, which greatly simplifies the calculation part circuit of the correlation detection, is conducive to simplifying the circuit structure, reducing the complexity of the circuit, and reducing the cost of correlation detection.

The embodiment of the present application discloses a kind of multiplexer and communication equipment, the multiplexer includes a transmitting port, at least one receiving port, at least one antenna port, filter set and switch.The fixed end of switch is connected with the first TDD filter in filter set, the first free end of switch is connected with the output end of the second TDD filter in filter set, and the second free end of switch is connected with one of receiving port;Transmitting port is connected with the input end of FDD transmitting filter in filter set and the input end of second TDD filter, and the output end of FDD receiving filter in filter set is connected with one of receiving port;The output end of FDD transmitting filter, the input end of FDD receiving filter and the first TDD filter are respectively connected with one of antenna port.Using the embodiment of the present application can improve port multiplexing rate and reduce circuit area under the premise of ensuring the reliable work of FDD and TDD.

The present invention discloses an on-chip temperature sensor based on an enhanced positive temperature coefficient voltage generation structure, comprising: a circuit for outputting a zero temperature coefficient reference voltage V REF and positive temperature coefficient voltage V PTAT The first part of the circuit is used to enhance the zero temperature coefficient reference voltage V REF The second part of the circuit is used to enhance the driving capability of the positive temperature coefficient voltage V PTAT The third part of the circuit is used to enhance the output voltage V of the third part of the circuit PTAT_E The invention comprises a fourth circuit for outputting a zero temperature coefficient bias current; a fifth circuit for outputting a zero temperature coefficient bias current; and a sixth circuit for on-chip temperature detection. The invention optimizes the slope of a traditional positive temperature coefficient voltage and expands the amplitude range to generate an optimized enhanced positive temperature coefficient voltage under the condition of constant temperature, and performs on-chip temperature detection of the chip by controlling an analog-to-digital converter.

The invention discloses a voltage regulator which is characterized by comprising a front-end circuit, a current mirror circuit assembly and an output circuit. The front-end circuit and the current mirror circuit assembly are connected at a first node, and the current mirror circuit assembly and the output circuit are connected at a second node. The front-end circuit comprises a first diode and a first capacitor. The anode of the first diode is connected with a first voltage source, and the cathode of the first diode and the first capacitor are connected to a first node. The first voltage source supplies power to the first node through the first diode, the first capacitor is used for storing electric energy, and the first node forms a first voltage. The first voltage drives the current mirror circuit assembly to generate a first current, and the first current is mapped to the second node to form a second voltage. The second voltage drives the output circuit to generate a working voltage required for chip operation.

The invention relates to an artificial intelligence chip and a test access method for the artificial intelligence chip. On the basis of the application, the on-chip function module of the artificial intelligence chip can be provided with a synchronous conversion circuit of which the control logic is simplified compared with the JTAG logic, and the conversion controller of the synchronous conversion circuit can be based on a control state maintained by an external host; a test signal written by an external host through a JTAG interface is controlled to be synchronized to a signal of a signal synchronization register of the synchronous conversion circuit according to a bus clock of the AMBA bus, and data transmission of the test signal in the signal synchronization register to a function register through the AMBA bus in the artificial intelligence chip can also be controlled. Therefore, the on-chip function module of the artificial intelligence chip does not need to have JTAG logic, thereby facilitating reduction of the circuit area of the on-chip function module, and further facilitating reduction of the circuit area of the artificial intelligence chip.

The invention discloses a voltage regulator which is characterized by comprising a front-end circuit, a current mirror circuit assembly and an output circuit. The front-end circuit and the current mirror circuit assembly are connected at a first node, and the current mirror circuit assembly and the output circuit are connected at a second node. The front-end circuit comprises a first diode and a first capacitor. The anode of the first diode is connected with a first voltage source, and the cathode of the first diode and the first capacitor are connected to a first node. The first voltage source supplies power to the first node through the first diode, the first capacitor is used for storing electric energy, and the first node forms a first voltage. The first voltage drives the current mirror circuit assembly to generate a first current, and the first current is mapped to the second node to form a second voltage. The second voltage drives the output circuit to generate a working voltage required for chip operation.

The embodiments of the present application relate to the field of memory, and provide a data input-output circuit and a memory, including: a parallel-to-serial circuit, configured to receive N data and output the N data serially within a first time period; a read enable signal generating circuit, configured to generate a read enable signal, and the read enable signal is at a valid level within the first time period; a resistance control circuit, electrically connected to the read enable signal generating circuit, configured to receive a termination resistance control code, an output drive resistance control code, and a read enable signal, and based on the read enable signal, select to output a termination resistance control code or output an output drive resistance control code; an output drive circuit, electrically connected to the parallel-to-serial circuit and the resistance control circuit, configured to receive N data and a signal output by the resistance control circuit, and configure an output drive resistance value and output N data based on the signal output by the resistance control circuit, or configure a termination resistance value; wherein N is a positive integer greater than 1.

A memory device is described. The memory device includes a memory cell area having a plurality of memory cells, and a peripheral circuit area including peripheral circuits configured to control the memory cells, the peripheral circuits connected to the memory cells by at least a portion of bit lines, word lines, and select lines may be provided. The peripheral circuits may include a reference voltage generator configured to output at least one reference voltage in response to control data of a control logic. The reference voltage generator may include a first resistor chain including first resistors connected in series between a first power node and a second power node, a second resistor chain including second resistors connected in series between the first power node and the second power node, and a plurality of decoders connected to the first resistor chain and the second resistor chain.

The present application discloses a method, device, electronic device and medium for prediction unit size decision. In the present application, multiple first candidate size prediction units can be obtained based on the motion estimation result of the current coding unit and the prediction unit decision model; based on the prediction unit decision result determined by the whole pixel motion estimation process, the second candidate size prediction unit entering the pixel-by-pixel motion estimation stage is determined among the multiple first candidate size prediction units; according to the motion information in the pixel-by-pixel motion estimation stage, the target prediction unit is determined from the second candidate size prediction unit. By applying the technical solution of the present application, all possible PU partitioning modes of each CU in the inter-frame CTU can be judged in advance in the IME stage, and the partitioning results can be passed to FME and MD, which can significantly reduce the number of candidate partitions entering the two, reduce the required storage cost and the circuit area of ​​​​FME.

The invention discloses an on-chip temperature sensor based on an enhanced positive temperature coefficient voltage generation structure. The on-chip temperature sensor comprises a first part circuit, a second part circuit and a third part circuit, wherein the first part circuit is used for outputting zero temperature coefficient reference voltage VREF and positive temperature coefficient voltage VPTAT; the second part circuit is used for enhancing the driving capability of the zero temperature coefficient reference voltage VREF; the third part circuit is used for enhancing the positive temperature coefficient voltage VPTAT; the fourth part circuit is used for enhancing the driving capability of the output voltage VPTATE of the third part circuit; the fifth part circuit is used for outputting zero temperature coefficient bias current; and the sixth part circuit is used for on-chip temperature detection of the chip. Under the condition that the temperature is not changed, the traditional positive temperature coefficient voltage slope is optimized, the amplitude range is expanded, the optimized and enhanced positive temperature coefficient voltage is generated, and on-chip temperature detection of a chip is carried out by controlling the analog-to-digital converter.

This disclosure relates to the field of USB 2.0 protocol implementation, specifically to a state management circuit architecture for a USB device, comprising: a state detection unit, configured to receive and determine a state signal based on a differential signal pair, and determine the target state of the USB based on the state signal; the differential signal pair includes a differential signal D+ and a differential signal D-; the state signal is any one of SE0, J, and K; the target state is any one of a suspended state, a wake-up state, a reset state, a general working state, and a wake-up request state; a high-speed handshake unit, configured to control the USB to perform high-speed handshake detection after the reset state, and to close the high-speed handshake unit after the high-speed handshake detection, so that the USB re-enters the general working state; and a state transition control unit, configured to manage the current state of the USB and transition the current state of the USB to the target state.

The invention discloses a ternary addressable memory array and a preparation method and a test method thereof, and relates to the technical field of transistor manufacturing. Comprising a plurality of ternary addressable memories which are arranged and interconnected in an array mode; each ternary addressable memory is composed of two reconfigurable double-gate field effect transistors which are connected with each other; a plurality of matching lines and grounding lines; the matching lines of the ternary addressable memories in the same row are connected with the same line, and the grounding lines are connected with the same line; a plurality of search lines; the search lines of the ternary addressable memories in the same column are connected with the same line; a plurality of first write lines and second write lines; the first write-in lines of the ternary addressable memories in the same column are connected with the same line, and the second write-in lines are connected with the same line. The memory array disclosed by the invention has the advantages of compact structure, strong reconfigurability, good compatibility and the like, obviously reduces the circuit area and power consumption, and is suitable for a high-energy-efficiency storage and calculation integrated system and a next-generation adaptive logic integrated circuit.

The invention provides an area-saving driving circuit, an area-saving driving method and a touch display driving chip. The driving circuit comprises a common electrode driving circuit, the common electrode driving circuit outputs a common voltage used for driving a common electrode in a display driving period, and the common electrode driving circuit outputs a compensation voltage used for driving a compensation capacitor in a touch sensing period. And the compensation capacitor is used for compensating parasitic capacitance on the sensing path. The common electrode driving circuit is adopted to drive the compensation capacitor in the touch sensing time period, an additional driving circuit used for driving the compensation capacitor is omitted, and the complexity and the circuit area of a driving circuit on a touch display driving chip are reduced.