5results about How to "Reduce circuit area" patented technology

The embodiment of the present application discloses a kind of multiplexer and communication equipment, the multiplexer includes a transmitting port, at least one receiving port, at least one antenna port, filter set and switch.The fixed end of switch is connected with the first TDD filter in filter set, the first free end of switch is connected with the output end of the second TDD filter in filter set, and the second free end of switch is connected with one of receiving port;Transmitting port is connected with the input end of FDD transmitting filter in filter set and the input end of second TDD filter, and the output end of FDD receiving filter in filter set is connected with one of receiving port;The output end of FDD transmitting filter, the input end of FDD receiving filter and the first TDD filter are respectively connected with one of antenna port.Using the embodiment of the present application can improve port multiplexing rate and reduce circuit area under the premise of ensuring the reliable work of FDD and TDD.

The invention relates to an artificial intelligence chip and a test access method for the artificial intelligence chip. On the basis of the application, the on-chip function module of the artificial intelligence chip can be provided with a synchronous conversion circuit of which the control logic is simplified compared with the JTAG logic, and the conversion controller of the synchronous conversion circuit can be based on a control state maintained by an external host; a test signal written by an external host through a JTAG interface is controlled to be synchronized to a signal of a signal synchronization register of the synchronous conversion circuit according to a bus clock of the AMBA bus, and data transmission of the test signal in the signal synchronization register to a function register through the AMBA bus in the artificial intelligence chip can also be controlled. Therefore, the on-chip function module of the artificial intelligence chip does not need to have JTAG logic, thereby facilitating reduction of the circuit area of the on-chip function module, and further facilitating reduction of the circuit area of the artificial intelligence chip.

A memory device is described. The memory device includes a memory cell area having a plurality of memory cells, and a peripheral circuit area including peripheral circuits configured to control the memory cells, the peripheral circuits connected to the memory cells by at least a portion of bit lines, word lines, and select lines may be provided. The peripheral circuits may include a reference voltage generator configured to output at least one reference voltage in response to control data of a control logic. The reference voltage generator may include a first resistor chain including first resistors connected in series between a first power node and a second power node, a second resistor chain including second resistors connected in series between the first power node and the second power node, and a plurality of decoders connected to the first resistor chain and the second resistor chain.

This disclosure relates to the field of USB 2.0 protocol implementation, specifically to a state management circuit architecture for a USB device, comprising: a state detection unit, configured to receive and determine a state signal based on a differential signal pair, and determine the target state of the USB based on the state signal; the differential signal pair includes a differential signal D+ and a differential signal D-; the state signal is any one of SE0, J, and K; the target state is any one of a suspended state, a wake-up state, a reset state, a general working state, and a wake-up request state; a high-speed handshake unit, configured to control the USB to perform high-speed handshake detection after the reset state, and to close the high-speed handshake unit after the high-speed handshake detection, so that the USB re-enters the general working state; and a state transition control unit, configured to manage the current state of the USB and transition the current state of the USB to the target state.

The invention discloses a ternary addressable memory array and a preparation method and a test method thereof, and relates to the technical field of transistor manufacturing. Comprising a plurality of ternary addressable memories which are arranged and interconnected in an array mode; each ternary addressable memory is composed of two reconfigurable double-gate field effect transistors which are connected with each other; a plurality of matching lines and grounding lines; the matching lines of the ternary addressable memories in the same row are connected with the same line, and the grounding lines are connected with the same line; a plurality of search lines; the search lines of the ternary addressable memories in the same column are connected with the same line; a plurality of first write lines and second write lines; the first write-in lines of the ternary addressable memories in the same column are connected with the same line, and the second write-in lines are connected with the same line. The memory array disclosed by the invention has the advantages of compact structure, strong reconfigurability, good compatibility and the like, obviously reduces the circuit area and power consumption, and is suitable for a high-energy-efficiency storage and calculation integrated system and a next-generation adaptive logic integrated circuit.