531 results about "Electronic chip" patented technology

The invention provides a flexible electronic device multi-physics field coupling performance simulation analysis method, and relates to the technical field of flexible electronics. Firstly, a geometric model of the flexible electronic device is constructed; the geometric model comprises a three-layer assembly structure of an electronic chip, an adhesive layer and a flexible PCB layer, and an interconnection structure; setting electromagnetic-thermal-mechanical field coupling parameters of the geometric model; then, grid division is conducted on the geometric model through a finite element method, and the grid division precision of the area where the interconnection structure is located is higher than that of other areas; building a multi-physics field coupling model according to the geometric model and set coupling parameters; applying load and boundary conditions to the model, wherein the load and boundary conditions comprise a current source, a heat generation load, a convection heat dissipation boundary condition and a mechanical constraint condition; and simulating the working state of the flexible electronic device under the action of multi-physics field coupling in the multi-physics field coupling model to obtain a simulation result. According to the method, the performance and the failure mechanism of the flexible electronic device under the multi-physics field coupling effect can be effectively predicted.

Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface.

The invention provides a laser galvanometer intelligent control system and method based on big data, and belongs to the technical field of intelligent control systems. S2, data preprocessing; s3, feature extraction; s4, model training; s5, performing real-time prediction; s6, generating a control instruction; s7, executing a control instruction; and S8, performing feedback and optimization. High-precision closed-loop control over movement of the laser galvanometer can be achieved, the deviation between the actual movement state and the target movement state is effectively reduced, the laser machining precision is improved, and application scenes such as electronic chip fine machining with extremely high precision requirements are met.

A cryogenic structure can include a cryogenic chamber that houses a plurality of circuits that operate and cryogenic temperatures, and a room temperature portion that houses a plurality of circuits that operate at non-cryogenic temperatures. The circuits can include computer chips, such as electrical or photonic chips, that are housed on movable structures that insertable into the cryogenic structure.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.

The invention relates to the technical field of ultrapure water particle monitoring, and discloses a light scattering and image recognition dual-method ultrapure water particle monitoring system and method. The system comprises a light scattering detection module, an image recognition detection module, a double-channel parallel sampling module, a multi-modal data fusion module and a dynamic feedback control module. The light scattering detection module detects large particles, the image recognition detection module detects small particles, and double-channel parallel sampling provides a stable water sample environment for the light scattering detection module and the image recognition detection module respectively. The multi-modal data fusion module fuses data to generate a full-particle-size particle distribution map, and the dynamic feedback control module adjusts detection parameters according to the full-particle-size particle distribution map. According to the invention, full-particle-size precise monitoring is realized, the monitoring precision, stability and reliability are improved, detection parameters can be adaptively optimized, the method is widely applied to the industries of electronic chip manufacturing, biological medicine and the like, and the water quality of ultrapure water is effectively guaranteed.

The present application provides a co-packaged optics structure and a manufacturing method therefor. The co-packaged optics structure comprises: an electronic chip packaging unit, wherein electronic chips are packaged in the electronic chip packaging unit; and an optical chip unit, wherein the optical chip unit comprises an optical chip and an optical window located on the front surface of the optical chip, the front surfaces of the electronic chips in the electronic chip packaging unit are opposite to and electrically connected to the front surface of the optical chip in the optical chip unit, and there is no overlapping area between the projection of the electronic chip packaging unit on the optical chip unit and the optical window. The co-packaged optics structure provided by the present application can achieve high-efficiency signal transmission and improve the product yield of the co-packaged optics structure.

The invention relates to the technical field of image processing. The invention provides a visual image monitoring method and an electronic chip, and the method comprises the steps: collecting an original image flow through a complementary metal oxide semiconductor sensor of a bionic retina structure, and generating a dynamic perception event flow; carrying out target detection and trajectory prediction processing, and generating a vector data set comprising a space-time correlation mark; performing heterogeneous graphic rendering processing on the original image flow through a programmable rendering pipeline to generate a superimposed image fused with augmented reality annotations; carrying out self-adaptive transparency mixing processing on the superposed image, the middle feature layer and the environment state layer to generate a feedback control signal and a visual synthetic image; and synchronous output processing is carried out on the visual synthetic image and the feedback control signal through the photon coding interface to obtain a synchronous output signal, so that the problem that dynamic transparency mixing and photon-level low-delay output cannot be supported in related technologies is solved, and the requirements of high-precision real-time monitoring and closed-loop control in an industrial scene are met.

The invention relates to the technical field of automatic identification and data acquisition, discloses a control method and system for positioning a scanning gun based on an RFID electronic chip, and aims to solve the problems of remnant detection failure and misjudgment caused by shielding and deformation of existing video monitoring. A unique identification RFID chip is arranged on the surface of an object, a multi-protocol scanning gun terminal is combined to capture label signals in real time, a space coordinate mapping module is used for achieving three-dimensional positioning, a track generation engine restores a moving path, and a retention judgment unit recognizes abnormal retention according to a time threshold value and a behavior mode and triggers an alarm linkage mechanism. According to the method, an active identity binding and trajectory tracking system is constructed, so that the dependence on a visual environment is eliminated, the remnant identification precision, the anti-interference capability and the response speed in a security scene are remarkably improved, and all-weather stable operation and large-scale convenient deployment are supported.

The invention discloses a construction cost evaluation system and method based on engineering list intelligent matching. The system comprises a block chain material account book module, a material supply and demand intelligent scheduling module and an abnormity self-healing processing module. The block chain material account book module is used for constructing a material full-life-cycle evidence storage network, the evidence storage network comprises purchasing, transportation, warehousing, receiving and final verification, data of each step of operation is uploaded to a block chain in real time, an NFT chip containing a unique two-dimensional code and RFID is implanted into each material package, and unique material identification and data non-tampering evidence storage are achieved; according to the system, the blockchain material account book module is used for carrying out chaining and evidence storage on data of the whole process of material purchasing, transportation, warehousing, receiving and verification, and each material is identified by a unique electronic chip. The whole life cycle information of the material can be completely and accurately recorded, and due to the non-tampering characteristic of the block chain, the authenticity and reliability of the data are guaranteed.

The application discloses an edge computing platform and system based on FPGA real-time target recognition detection, and relates to the field of microelectronic chips.The edge computing platform comprises an interconnected FPGA and DDR, and an ISP module, a pre-processing module, a VDMA module, an inference accelerator, a CPU and a character superposition module are arranged on the FPGA.The inference accelerator is used for deploying a preset convolutional neural network model, reading any frame of second image and weight parameter data about convolution kernels in the convolutional neural network model from the DDR, accelerating the execution of the algorithm of the convolutional neural network model by using a sphygmic array cluster module, and generating an inference result vector output to the DDR;the sphygmic array cluster module is integrated with a Winograd fast convolution algorithm and a multi-channel sphygmic array.Compared with the prior art, the application realizes the accelerated operation of the convolutional neural network model, and thus improves the inference efficiency.

A tire fitted with a transponder comprises: a crown comprising a crown reinforcement having an axial end at each of its edges, connected at each of its axial ends by a sidewall to a bead having an interior end; a carcass reinforcement layer formed of parallel reinforcers, which is anchored in each bead around a bead wire to form a main part and a turn-up; the transponder comprising a core defining a first axis, a first cover filament helically twisted around the core and an electrical insulation device; and the first cover filament comprising at least two conductive filamentary elements galvanically connected to an electronic chip comprising a radiofrequency transmission-reception component. The thickness of elastomeric compound separating the outer cover filament, located radially outermost with respect to the first axis, and the reinforcements is greater than 0.5 millimeters.

The invention discloses a simulated heat source circuit and a simulated heat source device, and relates to the field of heat testing, a plurality of heat production modules can be arranged at different positions of a circuit board, and the heat production conditions of an electronic chip to be tested at different positions in the working process are simulated through the plurality of heat production modules arranged on the circuit board. The power supplies are connected with the heat production modules in a one-to-one correspondence manner, and the voltage output condition of each power supply can be flexibly adjusted according to the actual application condition of the electronic chip in the test process, so that the heat production power of each heat production module is adjusted, and the power consumption of different areas in the simulated heat source circuit can be independently controlled; by independently controlling the heat production amount of each heat production module, the heat production conditions of different types of actual electronic chips such as uniform heat flux chips or non-uniform heat flux chips in the working process can be simulated more accurately, the flexibility is high, and the application range is wide.

A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

A power device electronics system includes a thermal management configuration in which a power electronics chip is attached to a copper substrate and a single crystal diamond substrate attached to the copper substrate. The copper substrate is sandwiched between a first side of the diamond substrate and the power electronics chip.

An electronic device can include a display assembly including a display and a transparent cover defining an external surface, a battery, the display disposed between the battery and the transparent cover, a printed circuit board (PCB), and an electronic chip disposed on the PCB between the display assembly and the PCB. In some examples, the electronic chip can include an ambient light sensor. In such examples, the battery can be spaced apart from the electronic chip to define an air gap between the battery and the ambient light sensor.

An optoelectronic component is specified with - a connection carrier (1) comprising contact points (3) in a first housing material (2), - an electronic chip (4) which is electrically connected to some of the contact points (3), - a second housing material (5) which completely covers the electronic chip (2) and some of the contact points (3), and - at least one optoelectronic chip (6) which is arranged in a cavity (7) of the second housing material (5) and is electrically conductively connected to the electronic chip (4) and some of the contact points (3).

The present invention relates to the field of semiconductor packaging technology, and specifically to a hybrid packaging structure, method, and testing method and system of an optoelectronic chip. The packaging structure includes: a first substrate; a strengthening connection layer is arranged on the upper surface of the first substrate; the strengthening connection layer includes: a silicon adapter plate, a first and a second strengthening layer are arranged on the silicon adapter plate, and an electronic chip is arranged on the upper surface of the second strengthening layer; a third strengthening layer, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer, the surface area exposed by the second strengthening layer, and the side of the electronic chip; a photonic chip is arranged on the upper surface of the third strengthening layer at a position corresponding to the first strengthening layer. The hybrid packaging solution based on the strengthening connection layer proposed in the present invention can be applied to wafer-level batch processing, which is conducive to achieving compatibility with advanced packaging processes of electronic chips and large-scale mass production.

The invention relates to a jet type liquid cooling heat dissipation device for an electronic chip and a working method of the jet type liquid cooling heat dissipation device. The device comprises a chip carrier provided with an electronic chip, a base, a jet flow guide plate, a backflow collection plate, a cover plate and a connector, the base is installed on the chip carrier in a sealed mode, and the jet flow guide plate, the backflow collecting plate and the cover plate are sequentially stacked and mutually connected in a sealed mode and are integrally fixed to the base. A first through hole and a second through hole are formed in the position, above the electronic chip, of the jet flow guide plate, a cooling liquid through hole and a cooling liquid guide hole are formed in the backflow collection plate, and a first cooling liquid connector and a second cooling liquid connector are formed in the cover plate. Compared with the prior art, through the collaborative design of the jet flow guide plate and the backflow collection plate, cooling liquid directly impacts the surface of an electronic chip in a high-speed jet flow mode, and therefore the local heat exchange efficiency is remarkably improved; and meanwhile, a backflow path is optimized, flowing resistance is reduced, high heat exchange performance and low pressure drop are both considered, and the heat dissipation device is suitable for efficient heat dissipation of high-heat-flux electronic chips.

The invention provides an automobile electronic chip parallel burning control method and system for multi-protocol dynamic switching, electronic equipment and a storage medium, and relates to the technical field of automobile electronic chip burning. A protocol power consumption association library is constructed, and a current sudden change interval in the protocol switching process is recognized; performing phase inversion processing to generate reverse compensation current, and performing active offset processing on transient fluctuation of a power supply layer of the automobile electronic chip by using the current to generate a power supply optimization enable signal; performing load period configuration processing on the multi-protocol burning time slot to generate a protocol distribution strategy; obtaining a multi-path protocol switching request, and performing priority sequence recombination processing based on the request to generate a recombination burning queue; and performing dynamic switching control processing by combining the recombined burning queue, the protocol distribution strategy and the power optimization enable signal to generate a multi-protocol parallel burning control signal. Cooperative control of multi-protocol dynamic switching and parallel burning can be realized, and burning efficiency and stability are improved.

The present invention discloses a heterogeneously integrated optoelectronic chip based on an optical through-substrate via (TSV), comprising multiple stacked optoelectronic chips based on the same or different types of substrates, each layer of optoelectronic chips having several optoelectronic devices, and at least one pair of optoelectronic chip layers are attached back-to-back and have an optical TSV with interlayer coupling structures at both ends, so as to establish optical interconnection between at least one pair of optoelectronic devices in different layers. The interlayer coupling structures include coupling gratings with high alignment tolerance, and a high-reflectivity metal film at a certain distance above the grating to achieve efficient unidirectional coupling. The invention solves the technical difficulties of III-V / silicon heterogeneous integration and 3D multi-chip stacking. It achieves interlayer connections through optical TSVs, enabling front electrodes of optoelectronic chips to be used for interconnection with electronic chips, avoiding the fabrication difficulty of electrical TSVs.

The anti-counterfeit detector allows to recognize authentic products (handbags) and to distinguish them from counterfeits. It is composed of 3 element chips allowing the recognition of branded products. - An electronic chip dedicated to the gates called Smart Electronic Chips for Gate (3) [Fig1], (1) [Fig2] - An electronic chip dedicated to the gates called Smart Electronic Chips for reader by waves for barcode scanner (2), (3) [Fig1], (2), (3) [Fig3] - An electronic chip dedicated to the gates called Smart Electronic Chips for barcode reader for barcode scanner (2) [Fig1] [Fig3] [Fig4] The control of counterfeiting is carried out thanks to the recognition / authentication of at least three of the criteria below: a. Recognition of an identical shape b. Recognition of an identical color c. Recognition of a specific sign

The invention discloses temperature-sensitive fluorescent coating ink based on quantum dots as well as a preparation method and application of the temperature-sensitive fluorescent coating ink. The ink is prepared from quantum dots, a polymer substrate material and a solvent, a temperature-sensitive fluorescent coating is formed on the surfaces of electronic components including an electronic chip, a micro-fluidic chip, an energy storage battery, a sensor and a micro-electro-mechanical system through a dispensing method, a spin-coating method, a blade coating method or a spraying method, and a uniform fluorescent film is prepared on the surface of the chip; exciting the fluorescent film by using laser; and according to a pre-calibrated temperature-spectrum relation curve, reconstructing a micro-scale two-dimensional or three-dimensional temperature distribution diagram of the chip in a working state. According to the invention, non-contact and high-resolution real-time temperature imaging of a chip working state microcell is realized, and a key technology is provided for temperature anomaly detection, thermal management optimization and failure analysis of a miniature electronic component.

Disclosed in the present invention are an interface thermal conductivity coefficient distribution optimization design method and system for improving the thermal contact performance of an assembly interface, the method comprising: acquiring microscopic morphological features of a contact heat dissipation surface of a component of an electronic chip packaging system; constructing a thermal contact performance numerical analysis model; using the thermal contact performance numerical analysis model to perform multiple iterations on the thermal conductivity coefficient distribution of a design area to obtain a thermal conductivity coefficient distribution and thermal contact resistance; on the basis of the thermal conductivity coefficient distribution and the thermal contact resistance, determining whether each iteration meets an iteration convergence criterion; and if the iteration convergence criterion is met, outputting the thermal conductivity coefficient distribution and the thermal contact resistance. In the present invention, the temperature transfer path of an assembly interface is controlled by designing the thermal conductivity coefficient distribution of the surface of the assembly interface, and the innovative design thinking of a "heterogeneous" thermal conductivity coefficient distribution is used to truly achieve a uniform temperature gradient distribution.

The present specification relates to an ultrasonic probe (100) comprising: an electronic chip (110) having a front face (110A) and comprising a substrate (111) and at least one micro-machined ultrasonic transducer (210) in and on the substrate and on the front face; an electrically insulating protective layer (130) covering the at least one transducer; and a metallic shielding layer (140) on the protective layer, the shielding layer forming an electromagnetic shield of the at least one transducer.

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

The present invention belongs to the technical field of enhanced heat transfer for electronic chip cooling, and discloses a microchannel-nanoporous thin film composite core silicon-based ultra-thin heat pipe and a manufacturing method thereof, which includes a pipe body. One end of the pipe body is an evaporation end, and the other end is set as a condensation end. The pipe body includes a first heat-conducting silicon wafer and a second heat-conducting silicon wafer bonded to each other, and a nanoporous thin film is arranged between the first heat-conducting silicon wafer and the second heat-conducting silicon wafer. A microchannel array is arranged on the first heat-conducting silicon wafer, a steam channel is arranged on the second heat-conducting silicon wafer, and the nanoporous thin film is arranged between the microchannel array and the steam channel. A working medium for cooling is circulated and arranged in the steam channel and the microchannel array. The structure of the present invention is compact and has high precision, enabling the working medium to circulate without external power, improving the heat dissipation capacity of capillary evaporation, capable of quickly cooling the chip, and the heat dissipation amount can be automatically adjusted according to the heat load of the chip, having the advantage of improving the temperature uniformity.