685 results about "Electronic chip" patented technology

The invention provides a flexible electronic device multi-physics field coupling performance simulation analysis method, and relates to the technical field of flexible electronics. Firstly, a geometric model of the flexible electronic device is constructed; the geometric model comprises a three-layer assembly structure of an electronic chip, an adhesive layer and a flexible PCB layer, and an interconnection structure; setting electromagnetic-thermal-mechanical field coupling parameters of the geometric model; then, grid division is conducted on the geometric model through a finite element method, and the grid division precision of the area where the interconnection structure is located is higher than that of other areas; building a multi-physics field coupling model according to the geometric model and set coupling parameters; applying load and boundary conditions to the model, wherein the load and boundary conditions comprise a current source, a heat generation load, a convection heat dissipation boundary condition and a mechanical constraint condition; and simulating the working state of the flexible electronic device under the action of multi-physics field coupling in the multi-physics field coupling model to obtain a simulation result. According to the method, the performance and the failure mechanism of the flexible electronic device under the multi-physics field coupling effect can be effectively predicted.

Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface.

The invention provides a laser galvanometer intelligent control system and method based on big data, and belongs to the technical field of intelligent control systems. S2, data preprocessing; s3, feature extraction; s4, model training; s5, performing real-time prediction; s6, generating a control instruction; s7, executing a control instruction; and S8, performing feedback and optimization. High-precision closed-loop control over movement of the laser galvanometer can be achieved, the deviation between the actual movement state and the target movement state is effectively reduced, the laser machining precision is improved, and application scenes such as electronic chip fine machining with extremely high precision requirements are met.

The invention is a handheld device that utilizes light for skin treatment. It consists of a handle with a power source, a user interface, and at least two capacitors. Connected to the top surface of the base unit is a head with at least two flash lamps and at least two reflectors. The device includes a control unit that regulates the voltage on the discharge capacitors to control the light energy from each flash lamp. Additionally, the device comes with an exchangeable cartridge, with each type of cartridge featuring a unique window layout and electronic chip containing information on lamp activation.

A cryogenic structure can include a cryogenic chamber that houses a plurality of circuits that operate and cryogenic temperatures, and a room temperature portion that houses a plurality of circuits that operate at non-cryogenic temperatures. The circuits can include computer chips, such as electrical or photonic chips, that are housed on movable structures that insertable into the cryogenic structure.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

The invention discloses an interface heat conductivity coefficient distribution optimization design method and system for improving the contact thermal performance of an assembly interface, and the method comprises the steps: obtaining the contact heat dissipation surface microstructure features of a part of an electronic chip packaging system, and constructing a contact thermal performance numerical analysis model; performing multiple iterations on the heat conductivity coefficient distribution of the design area by adopting a contact thermal performance numerical analysis model to obtain the heat conductivity coefficient distribution and contact thermal resistance; judging whether each iteration meets an iteration convergence criterion or not according to the heat conductivity coefficient distribution and the contact thermal resistance; and if the iterative convergence criterion is met, outputting heat conductivity coefficient distribution and contact thermal resistance. The temperature transfer path of the assembly interface is controlled by designing the surface heat conductivity coefficient distribution of the assembly interface, and temperature gradient distribution homogenization is truly achieved by applying the innovative design thought of'heterogeneous' heat conductivity coefficient distribution.

A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.

A microfluidic electronic chip, an organoid model preparation method, and a protein analysis method. The microfluidic electronic chip comprises a lab-on-chip and an electrode array, wherein the lab-on-chip comprises chambers for accommodating substances to be cultured; and the electrode array is connected to the chambers, and the electrode array is used for performing stimulation and electrophysiological monitoring on said substances in the chambers. The organoid model preparation method and the protein analysis method are both executed on the basis of the microfluidic electronic chip.

The invention relates to the technical field of ultrapure water particle monitoring, and discloses a light scattering and image recognition dual-method ultrapure water particle monitoring system and method. The system comprises a light scattering detection module, an image recognition detection module, a double-channel parallel sampling module, a multi-modal data fusion module and a dynamic feedback control module. The light scattering detection module detects large particles, the image recognition detection module detects small particles, and double-channel parallel sampling provides a stable water sample environment for the light scattering detection module and the image recognition detection module respectively. The multi-modal data fusion module fuses data to generate a full-particle-size particle distribution map, and the dynamic feedback control module adjusts detection parameters according to the full-particle-size particle distribution map. According to the invention, full-particle-size precise monitoring is realized, the monitoring precision, stability and reliability are improved, detection parameters can be adaptively optimized, the method is widely applied to the industries of electronic chip manufacturing, biological medicine and the like, and the water quality of ultrapure water is effectively guaranteed.

The present application provides a co-packaged optics structure and a manufacturing method therefor. The co-packaged optics structure comprises: an electronic chip packaging unit, wherein electronic chips are packaged in the electronic chip packaging unit; and an optical chip unit, wherein the optical chip unit comprises an optical chip and an optical window located on the front surface of the optical chip, the front surfaces of the electronic chips in the electronic chip packaging unit are opposite to and electrically connected to the front surface of the optical chip in the optical chip unit, and there is no overlapping area between the projection of the electronic chip packaging unit on the optical chip unit and the optical window. The co-packaged optics structure provided by the present application can achieve high-efficiency signal transmission and improve the product yield of the co-packaged optics structure.

The invention relates to a high-voltage testing device and method for a high-power power electronic chip. The device comprises a probe assembly, a probe adjusting unit, a wafer positioning platform and a positioning platform movement unit. The wafer positioning platform is used for fixing a chip, and the positioning platform movement unit is used for bearing the chip in the wafer positioning platform to move in a plane range; the probe assembly is used for carrying out connection test on a chip, and the probe adjusting unit is used for controlling the relative position of the probe assembly and the wafer positioning platform; through the design of different specifications of the probe assembly and the wafer positioning platform, high-voltage testing can be carried out on chips of different voltage grades, the distance between a probe and an oil pool can be flexibly adjusted in the testing process through the probe adjusting unit and the positioning platform moving unit, and the testing efficiency of the high-voltage power electronic chip is improved. The problems that the depth of an oil pool cannot be flexibly adjusted, the chip is ignited at high voltage and automatic testing is difficult due to limitation of the design size and specification of a probe in the chip testing process are solved.

The invention relates to the technical field of semiconductor packaging, in particular to a hybrid packaging structure and method of a photoelectric chip and a testing method and system of the photoelectric chip. The packaging structure comprises a first substrate; a reinforced connecting layer is arranged on the upper surface of the first substrate; the reinforced connection layer comprises a silicon adapter plate, a first reinforced layer and a second reinforced layer are arranged on the silicon adapter plate, and an electronic chip is arranged on the upper surface of the second reinforced layer; the third reinforcing layer at least can cover the exposed surface area of the first reinforcing layer, the exposed surface area of the second reinforcing layer and the side surface of the electronic chip; and a photon chip is arranged on the upper surface of the third reinforcing layer corresponding to the first reinforcing layer. The hybrid packaging scheme realized based on the reinforced connection layer can be applied to wafer-level batch processing, so that the compatibility with an advanced packaging process of an electronic chip and large-scale mass production can be realized.

The invention relates to a photoelectric integrated double-frequency laser for coherent wind measurement, which comprises a first light source module, a second light source module, a first coupler module, a second coupler module, a third coupler module, a first beam splitter module, a second beam splitter module, a third beam splitter module and a first balanced photoelectric detector module, a second balance photoelectric detector module, a modulator module, an optical phase-locked loop module and a transceiver. Based on the silicon-based optoelectronic chip technology and the photoelectric hybrid packaging technology on the structural level, the coupler, the beam splitter and the photoelectric detector are integrated on the silicon optical chip, and the silicon optical chip, the DFB chip, the coupling optical path, the electrical module and the like are packaged together by utilizing the photoelectric hybrid packaging technology, so that high-density integration is realized; a heterodyne digital optical phase-locked loop technology is applied to a system level, so that a specific frequency difference exists between output signal light and reference light, and pulse light with a high extinction ratio is generated in a modulator cascading mode. Compared with a conventional single-light-source system scheme, the heterodyne Doppler wind measurement laser radar system can greatly improve the integration level, reduce the power consumption and the cost, and is beneficial to mass production, and compared with a homodyne detection mode, heterodyne detection is higher in measurement speed, simpler in scheme and better in stability. The system has extremely high expansibility, and can be applied to systems of optical fiber sensing, laser remote sensing and cold atomic clocks through operations of replacing a transmitting-receiving device, modifying a control program and the like.

The invention relates to the technical field of image processing. The invention provides a visual image monitoring method and an electronic chip, and the method comprises the steps: collecting an original image flow through a complementary metal oxide semiconductor sensor of a bionic retina structure, and generating a dynamic perception event flow; carrying out target detection and trajectory prediction processing, and generating a vector data set comprising a space-time correlation mark; performing heterogeneous graphic rendering processing on the original image flow through a programmable rendering pipeline to generate a superimposed image fused with augmented reality annotations; carrying out self-adaptive transparency mixing processing on the superposed image, the middle feature layer and the environment state layer to generate a feedback control signal and a visual synthetic image; and synchronous output processing is carried out on the visual synthetic image and the feedback control signal through the photon coding interface to obtain a synchronous output signal, so that the problem that dynamic transparency mixing and photon-level low-delay output cannot be supported in related technologies is solved, and the requirements of high-precision real-time monitoring and closed-loop control in an industrial scene are met.

The invention relates to the technical field of automatic identification and data acquisition, discloses a control method and system for positioning a scanning gun based on an RFID electronic chip, and aims to solve the problems of remnant detection failure and misjudgment caused by shielding and deformation of existing video monitoring. A unique identification RFID chip is arranged on the surface of an object, a multi-protocol scanning gun terminal is combined to capture label signals in real time, a space coordinate mapping module is used for achieving three-dimensional positioning, a track generation engine restores a moving path, and a retention judgment unit recognizes abnormal retention according to a time threshold value and a behavior mode and triggers an alarm linkage mechanism. According to the method, an active identity binding and trajectory tracking system is constructed, so that the dependence on a visual environment is eliminated, the remnant identification precision, the anti-interference capability and the response speed in a security scene are remarkably improved, and all-weather stable operation and large-scale convenient deployment are supported.

The invention discloses a construction cost evaluation system and method based on engineering list intelligent matching. The system comprises a block chain material account book module, a material supply and demand intelligent scheduling module and an abnormity self-healing processing module. The block chain material account book module is used for constructing a material full-life-cycle evidence storage network, the evidence storage network comprises purchasing, transportation, warehousing, receiving and final verification, data of each step of operation is uploaded to a block chain in real time, an NFT chip containing a unique two-dimensional code and RFID is implanted into each material package, and unique material identification and data non-tampering evidence storage are achieved; according to the system, the blockchain material account book module is used for carrying out chaining and evidence storage on data of the whole process of material purchasing, transportation, warehousing, receiving and verification, and each material is identified by a unique electronic chip. The whole life cycle information of the material can be completely and accurately recorded, and due to the non-tampering characteristic of the block chain, the authenticity and reliability of the data are guaranteed.

Described herein is a packaging approach that employs a remapping layer to maintain compatibility to different types of electronic chips while allowing chip designers to standardize the layout of the electrical interface of a photonic interposer. A remapping layer remaps the electrical interface of an electronic chip to the electrical interface of a photonic interposer. Remapping layers may be implemented in various ways, including for example as monolithic electronic interposers and / or as individual remapping chips. In some embodiments, to reduce manufacturing costs, remapping layers may be implemented using passive electronics (without transistors). Because remapping layers are significantly less costly to manufacture than photonic interposers, shifting the need to provide ad hoc electrical interfaces from the photonic interposer to the remapping layer enhances the applicability of photonic interposers in computational, telecom and datacom settings.

The utility model relates to a high-voltage detection device of a power electronic chip, which comprises a detection box, a detection mechanism arranged in the detection box and a supporting seat used for supporting the chip, and is characterized in that the detection mechanism comprises a high-voltage probe assembly, a first limiting and fixing structure and a driving part used for driving the high-voltage probe assembly to move up and down; the high-voltage probe assembly is provided with a test probe, the first limiting and fixing structure comprises a fixing rod, the fixing rod and the high-voltage probe assembly are connected and move synchronously, the top end of the fixing rod is fixed through a spring, the bottom end of the fixing rod is used for pressing a chip to be tested when the fixing rod moves downwards in place, and the lowest point of the fixing rod is lower than the lowest point of the test probe. According to the detection device, the limiting and fixing structure is adopted to press, fix and position more than two positions of the chip, the structure is simple and convenient, the chip can be tightly fixed, the probe can conveniently probe downwards to test the chip, the detection device can be suitable for testing chips of different models, the whole operation is fast and convenient, and the test efficiency is improved.

The application discloses an edge computing platform and system based on FPGA real-time target recognition detection, and relates to the field of microelectronic chips.The edge computing platform comprises an interconnected FPGA and DDR, and an ISP module, a pre-processing module, a VDMA module, an inference accelerator, a CPU and a character superposition module are arranged on the FPGA.The inference accelerator is used for deploying a preset convolutional neural network model, reading any frame of second image and weight parameter data about convolution kernels in the convolutional neural network model from the DDR, accelerating the execution of the algorithm of the convolutional neural network model by using a sphygmic array cluster module, and generating an inference result vector output to the DDR;the sphygmic array cluster module is integrated with a Winograd fast convolution algorithm and a multi-channel sphygmic array.Compared with the prior art, the application realizes the accelerated operation of the convolutional neural network model, and thus improves the inference efficiency.

A tire fitted with a transponder comprises: a crown comprising a crown reinforcement having an axial end at each of its edges, connected at each of its axial ends by a sidewall to a bead having an interior end; a carcass reinforcement layer formed of parallel reinforcers, which is anchored in each bead around a bead wire to form a main part and a turn-up; the transponder comprising a core defining a first axis, a first cover filament helically twisted around the core and an electrical insulation device; and the first cover filament comprising at least two conductive filamentary elements galvanically connected to an electronic chip comprising a radiofrequency transmission-reception component. The thickness of elastomeric compound separating the outer cover filament, located radially outermost with respect to the first axis, and the reinforcements is greater than 0.5 millimeters.

The invention discloses a chip debugging function control method and system, electronic equipment and a storage medium, and belongs to the technical field of electronic chip debugging. The chip debugging function control method comprises the following steps: if an authorization request transmitted by target equipment is received, generating a random number, and encrypting the random number to obtain a random ciphertext; wherein the target equipment is debugging equipment or a server; sending the random ciphertext to the target device, so that the target device adds a decryption result of the random ciphertext to an authorization certificate; receiving the authorization certificate sent by the target equipment, and verifying the authorization certificate; and if the authorization certificate passes the verification, adding an identifier of the chip to the authorization certificate, and starting a debugging function of the chip by using the authorization certificate, so that the debugging device debugs the chip. In conclusion, the safety of chip debugging can be improved.

The invention discloses a simulated heat source circuit and a simulated heat source device, and relates to the field of heat testing, a plurality of heat production modules can be arranged at different positions of a circuit board, and the heat production conditions of an electronic chip to be tested at different positions in the working process are simulated through the plurality of heat production modules arranged on the circuit board. The power supplies are connected with the heat production modules in a one-to-one correspondence manner, and the voltage output condition of each power supply can be flexibly adjusted according to the actual application condition of the electronic chip in the test process, so that the heat production power of each heat production module is adjusted, and the power consumption of different areas in the simulated heat source circuit can be independently controlled; by independently controlling the heat production amount of each heat production module, the heat production conditions of different types of actual electronic chips such as uniform heat flux chips or non-uniform heat flux chips in the working process can be simulated more accurately, the flexibility is high, and the application range is wide.

A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

The invention discloses a high-phosphorus fluorine-containing wastewater advanced treatment system and method.The high-phosphorus fluorine-containing wastewater advanced treatment system comprises a high-phosphorus fluorine-containing wastewater homogenizing pond, a first-stage phosphorus and fluorine removal system, a second-stage advanced treatment system, a water producing pond and a regeneration dosing device, and the first-stage phosphorus and fluorine removal system comprises a reaction system and a first sedimentation pond; the secondary advanced treatment system comprises a pretreatment tank, a second sedimentation tank, a clarification tank, an advanced treatment pretreatment filtering device, a filtering water tank and a high-fluorine advanced treatment resin exchange tower which are connected in sequence, and a high-phosphorus fluorine-containing wastewater homogenizing tank is connected with an inlet of the reaction system; a water outlet of the reaction system is sequentially connected with the first sedimentation tank, the secondary advanced treatment system and the water producing tank, an unqualified water producing port of the clarification tank is connected with the high-phosphorus fluorine-containing wastewater homogenizing tank, and a water outlet of the high-fluorine advanced treatment resin exchange tower is connected with a washing and regeneration water inlet main pipeline. When the method is used for treating the phosphorus-containing and fluorine-containing wastewater generated in electronic chip manufacturing, the phosphorus and fluorine removal rate reaches 99% or above.

The invention provides a temperature acquisition system, a thermosensitive module, a communication system, an electronic chip and electronic equipment, and the temperature acquisition system can acquire a small minimum value of a temperature measurement value representing the temperature of a first thermosensitive device, i.e., the temperature acquisition resolution of the temperature acquisition system is high. And the temperature acquisition precision of the temperature acquisition system is improved. The temperature acquisition system may include a sampling circuit and a processing module. The sampling circuit may include a first sampling circuit and a second sampling circuit. The first sampling circuit can comprise a first resistor unit and a second thermosensitive device and is used for outputting a first voltage. The second sampling circuit can comprise a second resistor unit and a third thermosensitive device and is used for outputting a second voltage. The processing module may be configured to output a temperature measurement representative of a temperature of the first thermal device based on the first voltage and the second voltage.

A power device electronics system includes a thermal management configuration in which a power electronics chip is attached to a copper substrate and a single crystal diamond substrate attached to the copper substrate. The copper substrate is sandwiched between a first side of the diamond substrate and the power electronics chip.

An electronic device can include a display assembly including a display and a transparent cover defining an external surface, a battery, the display disposed between the battery and the transparent cover, a printed circuit board (PCB), and an electronic chip disposed on the PCB between the display assembly and the PCB. In some examples, the electronic chip can include an ambient light sensor. In such examples, the battery can be spaced apart from the electronic chip to define an air gap between the battery and the ambient light sensor.