403 results about "Electronic chip" patented technology

A cryogenic structure can include a cryogenic chamber that houses a plurality of circuits that operate and cryogenic temperatures, and a room temperature portion that houses a plurality of circuits that operate at non-cryogenic temperatures. The circuits can include computer chips, such as electrical or photonic chips, that are housed on movable structures that insertable into the cryogenic structure.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

The invention relates to the technical field of automatic identification and data acquisition, discloses a control method and system for positioning a scanning gun based on an RFID electronic chip, and aims to solve the problems of remnant detection failure and misjudgment caused by shielding and deformation of existing video monitoring. A unique identification RFID chip is arranged on the surface of an object, a multi-protocol scanning gun terminal is combined to capture label signals in real time, a space coordinate mapping module is used for achieving three-dimensional positioning, a track generation engine restores a moving path, and a retention judgment unit recognizes abnormal retention according to a time threshold value and a behavior mode and triggers an alarm linkage mechanism. According to the method, an active identity binding and trajectory tracking system is constructed, so that the dependence on a visual environment is eliminated, the remnant identification precision, the anti-interference capability and the response speed in a security scene are remarkably improved, and all-weather stable operation and large-scale convenient deployment are supported.

The application discloses an edge computing platform and system based on FPGA real-time target recognition detection, and relates to the field of microelectronic chips.The edge computing platform comprises an interconnected FPGA and DDR, and an ISP module, a pre-processing module, a VDMA module, an inference accelerator, a CPU and a character superposition module are arranged on the FPGA.The inference accelerator is used for deploying a preset convolutional neural network model, reading any frame of second image and weight parameter data about convolution kernels in the convolutional neural network model from the DDR, accelerating the execution of the algorithm of the convolutional neural network model by using a sphygmic array cluster module, and generating an inference result vector output to the DDR;the sphygmic array cluster module is integrated with a Winograd fast convolution algorithm and a multi-channel sphygmic array.Compared with the prior art, the application realizes the accelerated operation of the convolutional neural network model, and thus improves the inference efficiency.

The invention discloses a simulated heat source circuit and a simulated heat source device, and relates to the field of heat testing, a plurality of heat production modules can be arranged at different positions of a circuit board, and the heat production conditions of an electronic chip to be tested at different positions in the working process are simulated through the plurality of heat production modules arranged on the circuit board. The power supplies are connected with the heat production modules in a one-to-one correspondence manner, and the voltage output condition of each power supply can be flexibly adjusted according to the actual application condition of the electronic chip in the test process, so that the heat production power of each heat production module is adjusted, and the power consumption of different areas in the simulated heat source circuit can be independently controlled; by independently controlling the heat production amount of each heat production module, the heat production conditions of different types of actual electronic chips such as uniform heat flux chips or non-uniform heat flux chips in the working process can be simulated more accurately, the flexibility is high, and the application range is wide.

A power device electronics system includes a thermal management configuration in which a power electronics chip is attached to a copper substrate and a single crystal diamond substrate attached to the copper substrate. The copper substrate is sandwiched between a first side of the diamond substrate and the power electronics chip.

The invention relates to a jet type liquid cooling heat dissipation device for an electronic chip and a working method of the jet type liquid cooling heat dissipation device. The device comprises a chip carrier provided with an electronic chip, a base, a jet flow guide plate, a backflow collection plate, a cover plate and a connector, the base is installed on the chip carrier in a sealed mode, and the jet flow guide plate, the backflow collecting plate and the cover plate are sequentially stacked and mutually connected in a sealed mode and are integrally fixed to the base. A first through hole and a second through hole are formed in the position, above the electronic chip, of the jet flow guide plate, a cooling liquid through hole and a cooling liquid guide hole are formed in the backflow collection plate, and a first cooling liquid connector and a second cooling liquid connector are formed in the cover plate. Compared with the prior art, through the collaborative design of the jet flow guide plate and the backflow collection plate, cooling liquid directly impacts the surface of an electronic chip in a high-speed jet flow mode, and therefore the local heat exchange efficiency is remarkably improved; and meanwhile, a backflow path is optimized, flowing resistance is reduced, high heat exchange performance and low pressure drop are both considered, and the heat dissipation device is suitable for efficient heat dissipation of high-heat-flux electronic chips.

The invention provides an automobile electronic chip parallel burning control method and system for multi-protocol dynamic switching, electronic equipment and a storage medium, and relates to the technical field of automobile electronic chip burning. A protocol power consumption association library is constructed, and a current sudden change interval in the protocol switching process is recognized; performing phase inversion processing to generate reverse compensation current, and performing active offset processing on transient fluctuation of a power supply layer of the automobile electronic chip by using the current to generate a power supply optimization enable signal; performing load period configuration processing on the multi-protocol burning time slot to generate a protocol distribution strategy; obtaining a multi-path protocol switching request, and performing priority sequence recombination processing based on the request to generate a recombination burning queue; and performing dynamic switching control processing by combining the recombined burning queue, the protocol distribution strategy and the power optimization enable signal to generate a multi-protocol parallel burning control signal. Cooperative control of multi-protocol dynamic switching and parallel burning can be realized, and burning efficiency and stability are improved.

The present invention discloses a heterogeneously integrated optoelectronic chip based on an optical through-substrate via (TSV), comprising multiple stacked optoelectronic chips based on the same or different types of substrates, each layer of optoelectronic chips having several optoelectronic devices, and at least one pair of optoelectronic chip layers are attached back-to-back and have an optical TSV with interlayer coupling structures at both ends, so as to establish optical interconnection between at least one pair of optoelectronic devices in different layers. The interlayer coupling structures include coupling gratings with high alignment tolerance, and a high-reflectivity metal film at a certain distance above the grating to achieve efficient unidirectional coupling. The invention solves the technical difficulties of III-V / silicon heterogeneous integration and 3D multi-chip stacking. It achieves interlayer connections through optical TSVs, enabling front electrodes of optoelectronic chips to be used for interconnection with electronic chips, avoiding the fabrication difficulty of electrical TSVs.

The anti-counterfeit detector allows to recognize authentic products (handbags) and to distinguish them from counterfeits. It is composed of 3 element chips allowing the recognition of branded products. - An electronic chip dedicated to the gates called Smart Electronic Chips for Gate (3) [Fig1], (1) [Fig2] - An electronic chip dedicated to the gates called Smart Electronic Chips for reader by waves for barcode scanner (2), (3) [Fig1], (2), (3) [Fig3] - An electronic chip dedicated to the gates called Smart Electronic Chips for barcode reader for barcode scanner (2) [Fig1] [Fig3] [Fig4] The control of counterfeiting is carried out thanks to the recognition / authentication of at least three of the criteria below: a. Recognition of an identical shape b. Recognition of an identical color c. Recognition of a specific sign

The invention discloses temperature-sensitive fluorescent coating ink based on quantum dots as well as a preparation method and application of the temperature-sensitive fluorescent coating ink. The ink is prepared from quantum dots, a polymer substrate material and a solvent, a temperature-sensitive fluorescent coating is formed on the surfaces of electronic components including an electronic chip, a micro-fluidic chip, an energy storage battery, a sensor and a micro-electro-mechanical system through a dispensing method, a spin-coating method, a blade coating method or a spraying method, and a uniform fluorescent film is prepared on the surface of the chip; exciting the fluorescent film by using laser; and according to a pre-calibrated temperature-spectrum relation curve, reconstructing a micro-scale two-dimensional or three-dimensional temperature distribution diagram of the chip in a working state. According to the invention, non-contact and high-resolution real-time temperature imaging of a chip working state microcell is realized, and a key technology is provided for temperature anomaly detection, thermal management optimization and failure analysis of a miniature electronic component.

Disclosed in the present invention are an interface thermal conductivity coefficient distribution optimization design method and system for improving the thermal contact performance of an assembly interface, the method comprising: acquiring microscopic morphological features of a contact heat dissipation surface of a component of an electronic chip packaging system; constructing a thermal contact performance numerical analysis model; using the thermal contact performance numerical analysis model to perform multiple iterations on the thermal conductivity coefficient distribution of a design area to obtain a thermal conductivity coefficient distribution and thermal contact resistance; on the basis of the thermal conductivity coefficient distribution and the thermal contact resistance, determining whether each iteration meets an iteration convergence criterion; and if the iteration convergence criterion is met, outputting the thermal conductivity coefficient distribution and the thermal contact resistance. In the present invention, the temperature transfer path of an assembly interface is controlled by designing the thermal conductivity coefficient distribution of the surface of the assembly interface, and the innovative design thinking of a "heterogeneous" thermal conductivity coefficient distribution is used to truly achieve a uniform temperature gradient distribution.

The present specification relates to an ultrasonic probe (100) comprising: an electronic chip (110) having a front face (110A) and comprising a substrate (111) and at least one micro-machined ultrasonic transducer (210) in and on the substrate and on the front face; an electrically insulating protective layer (130) covering the at least one transducer; and a metallic shielding layer (140) on the protective layer, the shielding layer forming an electromagnetic shield of the at least one transducer.

Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

An electronic chip including a semiconductor substrate in and on which an integrated circuit is formed at least one connection metallization of the integrated circuit formed on the side of a front face of the semiconductor substrate and a first passivation layer covering the front face of the semiconductor substrate, the first passivation layer including openings in line with the connection metallization of the integrated circuit The chip having a second passivation layer covering the side flanks of the semiconductor substrate, the second passivation layer being made of a parylene, and the first passivation layer and the second passivation layer being in contact with each other on the side of the front face of the semiconductor substrate. Methods of making a device are also provided.

The present invention relates to the technical field of blister boxes and discloses a blister box for transferring electronic chips, comprising a box body, an inner groove one is provided at the center of the box body, a plurality of evenly distributed placement grooves are provided on the lower surface of the inner groove one, a connecting plate is fixedly connected to the top of the box body, an upper and lower penetrating mounting groove is provided at the center of the connecting plate, and the interior of the mounting groove is communicated with the interior of the inner groove one, a box cover is plugged into the upper part of the interior of the mounting groove, and a mounting assembly is jointly provided between the box cover and the interior of the mounting groove; the blister box is installed and disassembled by the connecting plate and the box cover fixedly connected to the top of the box body when in use, and the box cover is easily connected to or separated from the connecting plate by the mounting assembly when installing or disassembling, thereby avoiding the elastic vibration when the traditional blister box is separated from the cover plate, which causes the electronic chip to jump out of the placement groove and collide, and the blister box is easy to use.

A card-shaped data carrier includes an electronic chip module with at least one chip and a contact structure, and including a card body with an arrangement region for receiving the chip module, the chip module being arranged in the arrangement region of the card body, and the card body having at least one first plastics layer and at least one ceramic layer, the first plastics layer being formed from a brittle plastics material to adjust a fracture behavior of the card-shaped data carrier.

1. The name of this design product: electronic chip tray. 2. Purpose of this design product: Tray for placing electronic chips. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: Stereoscopic drawing 1. 5. The rear view is symmetrical with the main view, so the rear view is omitted; the left view is symmetrical with the right view, so the left view is omitted.

The utility model belongs to the field of air cooling radiators, and particularly relates to an air cooling radiator for an evaporative electronic chip, which comprises a heat conducting plate and a cooling fan, a mounting plate is arranged on the heat conducting plate, a mounting groove is formed in the top of the mounting plate, an arc-shaped block is fixedly connected to the inner wall of the mounting groove, and a clamping groove is formed in the bottom of the arc-shaped block; through the design of the structures such as the mounting groove, the arc-shaped block, the notch, the positioning plate and the convex edge, when the cooling fan is mounted, the convex edge is aligned with the notch and then the cooling fan is pressed downwards, so that the positioning plate extrudes the supporting plate to descend, meanwhile, after the positioning plate is rotated, the convex edge is rotated to the bottom of the arc-shaped block from the notch position, and after the cooling fan is loosened, under the action of the spring, the cooling fan is pressed downwards. The supporting plate abuts against the positioning plate so that the cooling fan can be positioned and installed, when the cooling fan needs to be maintained or replaced, the cooling fan can be easily disassembled without a tool, operation steps are greatly simplified, and time and labor cost are saved.

Electronic chip The present description relates to an electronic chip (200) delimited by an edge and comprising: - a semiconductor layer (101) extending along a main plane (XY); - an interconnection structure (202) positioned above the semiconductor layer; - a sealing ring (207) arranged in the interconnection structure between the edge of the electronic chip and an electronic circuit region (105) of the electronic chip, the sealing ring including: - a plurality of cavities (231, 231') connected together so as to form at least one continuous annular cavity around the electronic circuit region; and / or - a plurality of conductive regions connected together so as to form at least one annular conductive wall around the electronic circuit region. Figure for abstract: Fig. 2B

The embodiments of the present application relate to the technical field of semiconductor packaging. Disclosed are an optical-communication module packaging structure and a preparation method. The optical-communication module packaging structure comprises a packaging substrate, wherein a first recess is provided in an upper surface of the packaging substrate, a first chip is embedded in the first recess, an upper surface of the first chip is flush with the upper surface of the packaging substrate, and the upper surface of the first chip is an active surface; and a first packaging structure, wherein a second chip is packaged in the first packaging structure, the first packaging structure is arranged on the upper surface of the packaging substrate and the upper surface of the first chip, the first packaging structure is separately electrically connected to the packaging substrate and the first chip by means of a plurality of first solders isolated from each other, the first chip is an optical chip, and the second chip is an electronic chip. The optical-communication module packaging structure and the preparation method provided in the embodiments of the present application can satisfy a short interconnection length between packaged chips and also reduce packaging costs.

Power Module The invention relates to a power module (1) comprising an electronic chip (33), an encapsulation housing (2) housing said electronic chip (33), and at least a first pin (13) and a second pin (15) connected to said electronic chip (33), each having a first portion (27) projecting from a face (11) of the encapsulation housing (2), said first portions (27) being separated by a first clearance zone (19) from the face, characterized in that the power module (1) comprises a first protrusion (23) integral with the encapsulation housing (2) and disposed on the first clearance zone (19) between the first portion (27) of the first pin (13) and the first portion (27) of the second pin (15), said first protrusion (23) being made of at least one insulating material. (Figure 2)

The present invention relates to a method for processing the end face of an optoelectronic chip, the method comprising: making a plurality of grooves on a surface having a bump on the optoelectronic chip, the grooves being axially symmetrically distributed along any one central axis of the optoelectronic chip, and making one groove every 300 μm-1000 μm on the central axis of the optoelectronic chip, making at least four grooves in a preset clamping area, and making at least four grooves in a non-clamping area; then covering the surface having a bump on the optoelectronic chip with a protective sheet having a raised structure, fixing it by fitting the raised structure and the grooves, and filling it with an adhesive to form a composite structure, then clamping the end face of the optoelectronic chip with a fixture and performing a grinding and polishing process, removing the protective sheet and the adhesive, and obtaining the processed optoelectronic chip. The method of the present invention can protect the bumps of the optoelectronic chip and, by controlling the distribution of the grooves, can reduce the stress at a single point position and prevent damage to the optoelectronic chip.

An electronic chip includes a first main surface, intended to be glued to a substrate, a second main surface, and lateral surfaces. The second main surface includes a central area and a locally patterned peripheral area. The locally patterned peripheral area successively forms, from the central area, a first portion having a first thickness and a second portion having a second thickness. The first thickness is smaller than the thickness of the central area. The second thickness is greater than the first thickness and smaller than the thickness of the central area.

The utility model relates to a bag type electronic tag. A pocket is arranged on the bag type electronic tag. An electronic chip is placed in the pocket; a unique code is arranged below the pocket and on one side of the pocket type electronic tag, the pocket type electronic tag with the electronic chip easy to recycle can be achieved, and the problem that in an existing electronic tag, the electronic chip and washable cloth are sewn together, but when the existing electronic chip needs to be recycled, the electronic chip and the washable cloth are sewn together, so that the electronic chip cannot be recycled easily is solved. The technical effects that the sewing structure of the electronic chip and the washable cloth needs to be dismantled, time and labor are wasted, and sometimes, the electronic chip is damaged when the electronic chip is dismantled are achieved.

The utility model relates to circuit board technical field, and disclose a kind of circuit board of anti-electromagnetic interference, including circuit board and electronic chip, the electronic chip is fixedly installed in the one side of circuit board, and the one side of electronic chip is provided with anti-interference mechanism;The anti-interference mechanism includes the electromagnetic shield of being set to the one side of circuit board, the both sides of the electromagnetic shield are fixedly connected with a plurality of heat conduction needle, and one end of the heat conduction needle is penetrated to the inside of electromagnetic shield;The utility model can be fixed on circuit board by positioning mechanism through setting anti-interference mechanism, so that electromagnetic shield can completely cover electronic chip, realize anti-electromagnetic effect, avoid the interference of outside electromagnetic to electronic chip, when electronic chip is energized, heat energy will gather in the inside of electromagnetic shield, and heat conduction needle will absorb heat energy, and heat energy is conducted to the outside of electromagnetic shield, reach the effect of heat dissipation, avoid electronic chip overheating damage.

Silicon-based optoelectronic chips and lidar are disclosed. A silicon-based optoelectronic chip can include a reference light stabilization link, an optical phase-locked link, a switching switch link, and a frequency shift tuning and beat measurement link. These links enable on-chip integration of various devices, thereby improving the integration and reliability of a seed light source stabilization scheme.

The invention provides an electronic chip efficient assembly production device, and relates to the technical field of machine tool machining, the electronic chip efficient assembly production device comprises an assembly table, the front end of the assembly table is provided with a conveyor belt used for conveying chips and shell covers, the center of the top is rotatably provided with a station seat rotating intermittently, and a plurality of positioning assemblies used for positioning and clamping the chips are arranged on the station seat in an annular array mode; transfer assemblies used for transferring a chip and a shell cover are installed on the two sides of the assembly table, a shell disassembling assembly is installed on the back of the assembly table, and the shell disassembling assembly drives a shifting piece through a specially-designed transmission mechanism so that the shifting piece can automatically do composite rectangular track movement along a joint between the chip and the shell cover, and therefore filling glue can be accurately scraped open and separated, and shell cover disassembling is completed. According to the invention, the whole-course automation of the chip cover dismounting process is realized, the low-efficiency and error-prone manual operation is replaced, the production efficiency is obviously improved, and the damage to the bare chip and peripheral precise components in the dismounting process is effectively avoided.