523 results about "Parasitic capacitor" patented technology

The invention discloses an electricity meter adaptive error compensation method, system and device based on multi-physical coupling and hidden variable modeling and a storage medium, and relates to the technical field of electric energy metering and detection, and the method comprises the steps: constructing a multi-physical coupling basis vector containing a single variable and a cross variable based on a sensing output signal; hidden variable joint modeling is carried out based on the multi-physical coupling basis vector and parasitic capacitance change, magnetic conductivity drift and shunt resistance offset, and a compensation mapping relation of electromagnetic, thermal and stress coupling is formed; generating a compensation coefficient by adopting the compensation mapping relation, and applying the compensation coefficient in an ammeter metering link to complete an error compensation process; according to the method, voltage, current and phase compensation coefficients are generated through multi-physical coupling basis vector and hidden variable modeling, dynamic description and self-adaptive correction of error sources are achieved, dynamic accurate correction of voltage, current and phase is achieved, and it is ensured that the ammeter keeps high-precision metering for a long time under the complex environment and the device drift condition.

The invention discloses a primary and secondary fusion pole-mounted circuit breaker state monitoring system and method, and relates to the technical field of power system automation. The system comprises a native signal acquisition module which is used for multiplexing an inherent electrical loop of a circuit breaker and acquiring a current signal of an opening and closing coil and a capacitive reactance change signal of a parasitic capacitor between a high-voltage electrode and a grounding end; and the edge analysis module is used for processing the signal acquired by the original signal acquisition module, including generating a mechanical health degree through feature extraction and state mapping, calculating an insulation aging index based on capacitive reactance change, and dynamically correcting a monitoring reference in combination with a digital twin model and a filtering algorithm. Non-auxiliary element monitoring is realized by multiplexing the inherent electrical loop of the circuit breaker, so that the service life of the monitoring system and the service life of primary equipment are completely synchronous, and elements do not need to be replaced in the whole life cycle; errors introduced by additional sensors are avoided by using the original electrical signals, and the mechanical fault recognition and insulation state evaluation precision is remarkably improved.

A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source / drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and / or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and / or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.

The utility model provides a directional coupler and a radio frequency chip, and relates to the technical field of electronic communication. The directional coupler comprises an input port, an output port, a coupling port, an isolation port and an impedance adjusting network, the impedance adjusting network comprises an access switch, an impedance adjusting module and an inductance unit. The impedance adjusting module comprises an adjustable resistor unit and an adjustable capacitor unit which are connected in parallel; one end of the impedance adjusting module is connected to the isolation port through the access switch, and the other end of the impedance adjusting module is connected to the inductance unit; wherein the inductance unit is used for compensating parasitic capacitance in the directional coupler. According to the scheme, the impedance matching and phase characteristics of the directional coupler can be adjusted according to different working frequencies and environmental conditions through mutual cooperation of the access switch, the impedance adjusting module and the inductance unit, so that the directional coupler can maintain good directivity under various working conditions.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage VN collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage VP at a non-inverting input terminal of the AD converter, and converts a value of (VP−VN) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.

The invention discloses a common-mode electromagnetic interference modeling and suppression method for a matrix converter, and the method comprehensively considers high-frequency parameters and topological characteristics, builds a conduction CM EMI equivalent circuit model of the matrix converter, completes the impedance network fitting of key elements and the extraction of high-frequency parasitic parameters, and achieves the modeling and suppression of the common-mode electromagnetic interference of the matrix converter. The precision of the CM EMI model of the matrix converter is improved, and the analysis of the CM EMI characteristics of the matrix converter is simplified. According to the common-mode electromagnetic interference suppression method for the matrix converter, CM EMI characteristics of the matrix converter are analyzed, a low-attenuation loop in the converter is constructed by adopting a method of combining a neutral line leading-back type structure and increasing output filter capacitor neutral-point-to-ground parasitic capacitance, the propagation proportion of noise in a linear impedance stabilization network measurement branch is reduced, and the measurement accuracy of the common-mode electromagnetic interference suppression method for the matrix converter is improved. And effective suppression of low-cost CM EMI noise is realized on the premise of not depending on an input EMI filter.

The invention relates to a method and circuit for analyzing and reconstructing current type digital active EMI filtering based on a switching frequency spectrum, and the method comprises the steps: obtaining initial common-mode noise data and initial differential-mode noise data of a Buck circuit at a switching frequency point; constructing a common-mode equivalent circuit and a differential-mode equivalent circuit comprising a noise source, a compensation voltage source, a compensation capacitor, a parasitic capacitor and LISN impedance, and calculating initial compensation voltage common-mode data and initial compensation voltage differential-mode data of each frequency point to obtain initial compensation voltage data; synchronously outputting the initial compensation voltage data through a DAC (Digital-to-Analog Converter), and performing initial noise compensation; and measuring noise voltage on the LISN as noise source voltage, calculating to obtain secondary compensation voltage data, and carrying out superposition iteration on the compensation voltage data. The method is suitable for a scene with common-mode noise as a main part, can realize common-mode and differential-mode composite suppression without detection and size reduction, and continuously optimizes an EMI suppression effect through iterative updating.

The invention relates to a filtering connector, in particular to a high-speed and low-speed signal mixed-loading filtering connector, which comprises a shell, a plate-type capacitor is arranged in the shell, and a plurality of capacitor hole positions are distributed on the plate-type capacitor; an insulating sleeve penetrates through a part of the capacitor hole positions, and a high-speed contact piece penetrates through the insulating sleeve; an elastic piece penetrates through the other part of capacitor holes, a low-speed contact piece penetrates through the elastic piece, and a grounding spring is arranged between the plate-type capacitor and the inner wall of the shell, so that filter conduction of the low-speed contact piece, the plate-type capacitor and the shell is realized; and insulating structures are arranged in the inner cavity of the shell on two sides of the plate-type capacitor. For the condition that signals transmitted by the connector comprise high-speed signals, low-speed signals and power signals and the number of cores is large, the low-speed signals and the power signals are filtered, and the high-speed signals are subjected to stray capacitance reduction processing, so that equipment using the connector can pass an electromagnetic compatibility test, and the high-speed signals are normally transmitted.

The invention discloses a low-power-consumption radiation-resistant quadrature voltage-controlled oscillator based on an SOI (Silicon On Insulator) process, relates to the technical field of quadrature voltage-controlled oscillators, and is used for solving the technical problems that an existing quadrature voltage-controlled oscillator is low in radiation resistance in a harsh radiation environment and does not have the characteristic of low power consumption. The invention discloses a low-power-consumption anti-radiation quadrature voltage-controlled oscillator based on an SOI process. The low-power-consumption anti-radiation quadrature voltage-controlled oscillator comprises a first voltage-controlled oscillator, a second voltage-controlled oscillator, a first tail filter and a second tail filter, the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively form an LC resonant cavity with a parasitic capacitor of an inductor and a varactor through the inductor; the first tail filter is connected with the first voltage-controlled oscillator, and the second tail filter is connected with the second voltage-controlled oscillator; two inductors of the first tail filter and the second tail filter are coupled; lC resonant cavities of the first voltage-controlled oscillator and the second voltage-controlled oscillator output oscillation waveforms, and negative impedance is formed through configured transistor pairs, so that the waveforms are output constantly.

The invention discloses an excitation inductance design method for guaranteeing soft switching of a CLLC resonant converter, and the method comprises the steps: carrying out the qualitative analysis of a dead-zone equivalent circuit of the CLLC resonant converter, and carrying out the Laplace coordinate transformation. And according to the constant frequency analysis principle of the CLLC resonant converter, obtaining the electric quantity values of the capacitor and the inductor at the dead zone moment. And obtaining a resonance current time domain expression in a dead zone period by adopting a mesh current method. And calculating the period of the resonance current according to the parasitic capacitance values of the primary and secondary side switching tubes. And calculating the discharge time of the parasitic capacitor by considering the electric quantity of the capacitor. And calculating the excitation inductance value required when the resonance current just drops to zero when the dead time is ended. Soft switching of the resonant converter can be effectively guaranteed, the amplitude of the resonant current is reduced, the efficiency of the resonant converter is improved, and the universality is high.

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming an injection layer on the substrate; forming a buffer layer and a drift layer on the injection layer, and performing laser annealing on the buffer layer and the drift layer from one side away from the substrate; a plurality of conductive channel units arranged at intervals are formed on the upper surface layer of the drift layer, laser annealing is conducted on the conductive channel units from the side away from the substrate, and each conductive channel unit comprises a well region, an emitter region and a contact region, forming a gate structure above the well region; removing the substrate to expose the injection layer; laser annealing is carried out on the injection layer from the side, away from the buffer layer, of the injection layer, and laser wavelengths used in laser annealing of the buffer layer, the drift layer, the conductive channel unit and the injection layer are selected based on light absorption characteristic parameters of the injection layer, the buffer layer and the drift layer. According to the semiconductor structure and the preparation method thereof, the formation of parasitic capacitance is reduced, and the device performance is improved.

The invention discloses a voltage-controlled oscillator with small-area and wide-band modulation capability, and particularly relates to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises two symmetrical voltage-controlled oscillation units; wherein each voltage-controlled oscillation unit comprises a resonance circuit; the resonance circuit comprises an LC resonance circuit and a negative resistance active circuit; the LC resonant circuit comprises a switched capacitor array; two ports of the LC resonance circuit are respectively connected to the output ends of the cross coupling MOS pair; the switched capacitor array is used for providing at least two gears of variable capacitance; the negative resistance active circuit comprises a cross coupling pair transistor and a bias current source; the mode change-over switch circuit comprises two groups of symmetrical switch MOS (Metal Oxide Semiconductor) tubes and mutual inductance transformer taps; and in each voltage-controlled oscillation unit, a tap of the resonant inductor is connected with a corresponding port of the mode switching switch MOS tube. According to the scheme, the mismatch effect caused by a small process and the stray capacitance caused by layout and wiring can be reduced as much as possible, and the chip area can be reduced while the performance is ensured, so that the tape-out cost is reduced.

The invention provides a preparation method of an inductor and the inductor, and the preparation method comprises the following steps: (1) mixing a magnetic powder raw material with a glue solution, sequentially carrying out granulation and pressing to obtain a magnetic core, and carrying out primary curing on the magnetic core; (2) winding a conductor coil, soaking the conductor coil into an insulating liquid for insulating treatment to form an insulating layer, and then filling the conductor coil into the magnetic core; and (3) magnetic slurry is injected into the magnetic core in the step (2), secondary curing is carried out, and an inductor blank is obtained. The coil can be prevented from being deformed, and the parasitic capacitance of the inductor is greatly reduced through insulation protection treatment.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source / drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source / drain opening, and forming a source / drain feature in the source / drain opening and over the isolation layer, wherein the source / drain feature is spaced apart from the isolation layer by an air gap.

The invention discloses a method for extracting parameters of an equivalent circuit model of a GaN HEMT device. The method at least comprises the following steps of S1, modeling the GaN HEMT device into a small-signal equivalent circuit model; s2, extracting external parasitic parameters based on the model in the step S1; s3, internal intrinsic parameters are extracted; in the step S1, the equivalent circuit model comprises external parasitic parameters and internal intrinsic parameters, and the external parasitic parameters are not affected by applied bias voltage and comprise parasitic capacitances Cpg, Cpd and Cpg between metal electrodes, external parasitic inductances Lg, Ld and Ls and external parasitic resistances Rg, Rd and Rs; internal intrinsic parameters are influenced by a channel structure and a bias condition when the device works, and comprise a channel resistor Rgs, a gate-drain resistor Rgd and a drain-source output conductor Gds; capacitors Cgs, Cgd and Cds are arranged among the ports; the transconductance is gm, and the time delay parameter is tau.

The invention provides an image sensor. The image sensor comprises a substrate; the transmission gate is located on the substrate, and the floating diffusion region is located in the substrate on one side of the transmission gate; the source following grid electrode is located on the substrate, and the source following source region and the source following drain region are located in the substrate on the two sides of the source following grid electrode respectively; the MOM capacitor is located on the side, away from the substrate, of the transmission grid electrode and the source following grid electrode, and the floating diffusion region and the source following source region are electrically connected through the MOM capacitor. According to the invention, the MOM capacitor is connected between the floating diffusion region and the source following source region, so that the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the signal-to-noise ratio of the device can be improved, thereby improving the reading noise reduction capability of the image sensor.

The invention discloses a driving method, a display device, display equipment and a computer readable storage medium, and the method comprises the steps: determining an xth data line and an (x + 1) th data line in a driving chip, obtaining a first voltage of a first sub-pixel of a current updating line of an xth column of sub-pixels corresponding to the xth data line, determining an influence factor of each sub-pixel on the (x + 1)-th data line according to the voltage difference of the display gray scale of each sub-pixel on the (x + 1)-th data line, and determining a first correlation quantity according to the influence factor of the sub-pixel on the (x + 1)-th row before the first sub-pixel, determining a second correlation quantity according to the influence factor of the sub-pixel on the (x + 1) th row after the first sub-pixel, obtaining a compensation value based on the first preset value, the first correlation quantity and the second correlation quantity, obtaining a second voltage according to the compensation value and the first voltage value, and transmitting the second voltage to the first sub-pixel, the voltage interference of the first sub-pixel caused by a parasitic capacitance coupling effect is reduced, and abnormal display on a display screen is eliminated.

An electronic key may include a partial capacitor comprising a capacitive metal plate in communication with a processor. The capacitive metal plate of the partial capacitor is configured to form a capacitor with a corresponding capacitive metal plate of a lock when brought into proximity with the metal plate of the lock. Data may be transferred from the key to the lock using a capacitor formed by combining the two metal plates, wherein a common ground is established between the metal plate of the key and the metal plate of the lock through a parasitic capacitance present between the key and lock circuitry. Audit trail data may be recorded based on usage of the key.

A low-voltage integrated power distribution architecture and a vehicle. The low-voltage integrated power distribution architecture comprises a high-voltage input end (110), a DCDC circuit (200), a low-voltage management circuit (400), a low-voltage power distribution circuit (300), and a low-voltage battery (500); the low-voltage power distribution circuit (300) is provided with a low-voltage power supply end (120) for connection to a low-voltage load; one end of the low-voltage power distribution circuit (300) is connected to the low-voltage battery (500) by means of the low-voltage management circuit (400); and the other end of the low-voltage power distribution circuit (300) is connected to a high-voltage input end (110) by means of the DCDC circuit (200). By integrating the DCDC circuit (200), the low-voltage management circuit (400), the low-voltage power distribution circuit (300), and the low-voltage battery (500) together and reusing a same controller (600), the function of managing the low-voltage management circuit (400), the low-voltage power distribution circuit (300), and the DCDC circuit (200) is integrated in the controller (600). The weight and size of the power distribution architecture are reduced, and the probability of parasitic inductance or parasitic capacitance between the DCDC circuit (200) and the low-voltage battery (500) causing damage to circuits in the vehicle is reduced.

The invention discloses a silicon carbide device simulation model and a simulation method thereof. The simulation model is composed of a device gate parasitic inductor, a device gate internal resistor, a device gate collector parasitic capacitor, a device gate emitter parasitic capacitor, an electron current voltage-controlled current source, a hole current source, a device collector parasitic resistor, a device emitter parasitic inductor, a device collector parasitic inductor, a device collector emitter parasitic capacitor and a device ideal diode. During application, parameter data of the device are tested through the static analysis device and the 18kV high-voltage dynamic characteristic test platform, the measured data are input into fitting software, parameter values of the device are determined according to fitting results, and the fitting voltage range is widened, so that the model can be used for simulating the high-voltage silicon carbide device with the voltage class of 18kV and below. The technical problems that an existing silicon carbide device simulation model cannot simulate a silicon carbide device with the voltage of 6.5 kV or above and cannot meet the simulation requirement of a 18kV high-voltage silicon carbide device are solved.

An MEMS resonator disclosed by the present invention comprises a resonance main body, an anchoring area and an electrode area, the resonance main body comprises a plurality of resonance rings arranged at intervals and a connecting beam connecting the resonance rings and the anchoring area, and the electrode area and the resonance rings are correspondingly arranged. Comprising a first electrode area which is arranged outside the resonant ring and is separated from the outer edge of the resonant ring, and a second electrode area which is arranged in the resonant ring and is separated from the inner edge of the resonant ring; positive electrodes are arranged in parts of the first electrode area and the second electrode area, negative electrodes are arranged in parts of the first electrode area and the second electrode area, the positive electrodes comprise positive driving electrodes and / or positive sensing electrodes, the negative electrodes comprise negative driving electrodes and / or negative sensing electrodes, and the capacitance area formed by the positive electrodes at intervals relative to the base substrate is the same as the capacitance area formed by the negative electrodes at intervals relative to the base substrate. The parasitic capacitance generated by the positive electrode and the negative electrode is the same and can be counteracted, so that the parasitic capacitance is reduced, and the signal-to-noise ratio of signals and the stability of high-frequency output are improved.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source / drain region are reduced, and device characteristics are improved.

The application discloses an in-cell touch display panel, which comprises a color film substrate, an array substrate and a liquid crystal layer sandwiched between the color film substrate and the array substrate; the touch electrode is hollowed out to reduce the parasitic capacitance between the pixel touch electrode and the scanning line, and a BM barrier is arranged above the corresponding CF of the touch electrode hollowing-out part; the BM covers the touch electrode hollowing-out part with a certain distance, so as to avoid the light leakage caused by the influence of the scanning line voltage on the liquid crystal deflection. The size of the overlapping area between the touch electrode and the scanning line is designed to be consistent at the edge and the middle of the touch electrode TP block, so that the parasitic capacitance between the touch electrode and the scanning line is consistent at the edge and the middle of the touch electrode TP block; the wires are arranged in the horizontal and vertical directions in the touch electrode TP block to reduce the impedance. The application solves the problem of uneven display brightness of the in-cell touch display panel.

The utility model provides a laser radar circuit and laser radar equipment, and relates to the technical field of laser radars. The laser radar circuit comprises a controller, a receiving module, a transmitting module and a digital processing module. The control module is electrically connected with the receiving module, the transmitting module and the digital processing module. The receiving module comprises a receiver and a matching capacitor. The capacitance value of a parasitic capacitor of the receiver is equal to the capacitance value of the matching capacitor. In the laser radar circuit provided by the invention, the capacitance value of the parasitic capacitor of the receiver is equal to the capacitance value of the matching capacitor, so that impedance matching can be more effectively realized, signal reflection and transmission loss can be reduced, noise in the circuit can be reduced, the signal-to-noise ratio of signals can be improved, electromagnetic interference can be effectively reduced, and the reliability of the laser radar circuit can be improved. The background noise of the optical receiver is effectively reduced, and the overall performance of the laser radar system is improved.

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

The invention relates to the technical field of power transistor output matching, in particular to an integrated passive matching, pre-matching and output internal matching circuit, and discloses an integrated passive matching circuit which is characterized in that an auxiliary wire group is arranged below a wire group for connecting two conductive blocks; the conductive block is fixedly arranged above the conductive plane through the insulating support, the two ends of the auxiliary wire group are connected with the conductive plane, and the inductance value of the wire group is adjusted through the number and width of wires of the auxiliary wire group and the distance between the auxiliary wire group and the wire group, so that the inductance value of the wire group arranged in the limited space is controllable. According to the pre-matching circuit disclosed by the embodiment of the invention, the inductor and the capacitor which are connected in series are arranged, and the inductor and the capacitor are set and are connected with the drain electrode of the power transistor, so that the harmonic wave with the preset frequency generates resonance on the inductor, the capacitor and the parasitic capacitor of the power transistor, and the output impedance of the transistor is increased; the power loss of the matching circuit is reduced and the efficiency of the power transistor is improved.

A touch display device according to embodiments of the disclosure may comprise a substrate including a display area and a non-display area adjacent to the display area, a pixel electrode disposed on the substrate, a common electrode disposed on the pixel electrode, a first inorganic encapsulation layer disposed on the common electrode, an organic encapsulation layer disposed on the first inorganic encapsulation layer, a second inorganic encapsulation layer disposed on the organic encapsulation layer, and a touch sensor disposed on the second inorganic encapsulation layer. A dielectric constant of the first inorganic encapsulation layer may be smaller than a dielectric constant of the second inorganic encapsulation layer, and a dielectric constant of the organic encapsulation layer may be smaller than the dielectric constant of the first inorganic encapsulation layer. This layered encapsulation structure may reduce parasitic capacitance and enhance touch sensitivity while maintaining improved resistance to moisture and oxygen permeation.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.