274 results about "Parasitic capacitor" patented technology

The invention discloses a primary and secondary fusion pole-mounted circuit breaker state monitoring system and method, and relates to the technical field of power system automation. The system comprises a native signal acquisition module which is used for multiplexing an inherent electrical loop of a circuit breaker and acquiring a current signal of an opening and closing coil and a capacitive reactance change signal of a parasitic capacitor between a high-voltage electrode and a grounding end; and the edge analysis module is used for processing the signal acquired by the original signal acquisition module, including generating a mechanical health degree through feature extraction and state mapping, calculating an insulation aging index based on capacitive reactance change, and dynamically correcting a monitoring reference in combination with a digital twin model and a filtering algorithm. Non-auxiliary element monitoring is realized by multiplexing the inherent electrical loop of the circuit breaker, so that the service life of the monitoring system and the service life of primary equipment are completely synchronous, and elements do not need to be replaced in the whole life cycle; errors introduced by additional sensors are avoided by using the original electrical signals, and the mechanical fault recognition and insulation state evaluation precision is remarkably improved.

The utility model provides a directional coupler and a radio frequency chip, and relates to the technical field of electronic communication. The directional coupler comprises an input port, an output port, a coupling port, an isolation port and an impedance adjusting network, the impedance adjusting network comprises an access switch, an impedance adjusting module and an inductance unit. The impedance adjusting module comprises an adjustable resistor unit and an adjustable capacitor unit which are connected in parallel; one end of the impedance adjusting module is connected to the isolation port through the access switch, and the other end of the impedance adjusting module is connected to the inductance unit; wherein the inductance unit is used for compensating parasitic capacitance in the directional coupler. According to the scheme, the impedance matching and phase characteristics of the directional coupler can be adjusted according to different working frequencies and environmental conditions through mutual cooperation of the access switch, the impedance adjusting module and the inductance unit, so that the directional coupler can maintain good directivity under various working conditions.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source / drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source / drain opening, and forming a source / drain feature in the source / drain opening and over the isolation layer, wherein the source / drain feature is spaced apart from the isolation layer by an air gap.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

A touch display device according to embodiments of the disclosure may comprise a substrate including a display area and a non-display area adjacent to the display area, a pixel electrode disposed on the substrate, a common electrode disposed on the pixel electrode, a first inorganic encapsulation layer disposed on the common electrode, an organic encapsulation layer disposed on the first inorganic encapsulation layer, a second inorganic encapsulation layer disposed on the organic encapsulation layer, and a touch sensor disposed on the second inorganic encapsulation layer. A dielectric constant of the first inorganic encapsulation layer may be smaller than a dielectric constant of the second inorganic encapsulation layer, and a dielectric constant of the organic encapsulation layer may be smaller than the dielectric constant of the first inorganic encapsulation layer. This layered encapsulation structure may reduce parasitic capacitance and enhance touch sensitivity while maintaining improved resistance to moisture and oxygen permeation.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

The application discloses a broadband multi-stage Gysel power divider based on an IPD process, comprising a microstrip structure layer, and first and second dielectric substrates and a ground metal layer; the microstrip structure layer adopts a multi-layer nested structure, each layer of the nested structure is formed by cascading multi-stage Gysel power division units, and is arranged on the upper surface and the interior of the first dielectric substrate, so that an integrated layout based on the IPD process is formed, and a planar spiral structure, an air bridge, a parallel plate capacitor, a thin film resistor and a layered ground unit structure are integrated; the planar spiral structure is equivalent to a specific characteristic impedance transmission line, the air bridge structure solves cross interference and suppresses a parasitic capacitor, the parallel plate capacitor structure calibrates equivalent reactance parameters, the thin film resistor effectively improves port isolation and heat dissipation, and the layered ground unit structure strengthens heat dissipation and ground reliability. The application can realize stable power distribution in a wide frequency band, and is suitable for the integration requirements of high-frequency, high-power and small-sized radio frequency front ends.

The invention relates to the technical field of integrated circuits, and discloses an ESD circuit for power supply clamping, and the ESD circuit comprises a quick starting circuit, a detection circuit and a bleeder circuit which are connected in sequence. The quick starting circuit comprises a sensing branch and a logic control generation branch; the sensing branch is configured to generate a trigger voltage through a parasitic capacitor in an MOS tube in the branch when electrostatic charges reach a power supply port; the logic control generation branch is connected with the output end of the sensing branch and is configured to generate a trigger signal based on the trigger voltage; wherein the trigger signal is used for controlling the detection circuit to be started and generating a starting signal, so as to control the discharge circuit to discharge electrostatic charges through the starting signal. According to the circuit, the bleeder circuit can be opened in time, so that the possibility that electrostatic charges break down an internal protected circuit is reduced. The invention also discloses a chip.

A pixel circuit and a display device are disclosed. A display device may include a plurality of subpixels that each include: a light emitting element; a driving transistor configured to operate the light-emitting element by receiving a data voltage; a switching transistor configured to apply the data voltage to a gate electrode of the driving transistor; the light-emitting element including a cathode and an anode, the anode being connected to a source electrode of the driving transistor, the cathode being electrically connected to a low-potential voltage supply line, in which the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, and in which an intermediate electrode line that traverses a storage capacitor of the subpixels composes a first parasitic capacitor with the gate electrode of the driving transistor and composes a second parasitic capacitor with the source electrode of the driving transistor.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The application provides a display substrate and a display device. The display substrate comprises a substrate, a sub-pixel, a data line and a selection switch. The substrate comprises a display area and a peripheral area. The sub-pixel and the data line are located in the display area, and the selection switch is located in the peripheral area. The selection switch comprises a first selection switch and a second selection switch located on both sides of the first selection switch. The data lead comprises a plurality of first data leads and a plurality of second data leads. The first selection switch and the second selection switch are electrically connected with the first data lead and the second data lead respectively. The width of at least part of the line segment in the first data lead is greater than the width of at least part of the line segment in the second data lead. The width of the first data lead and the second data lead is set, which can effectively reduce the parasitic capacitance difference between different areas, thereby effectively improving the dark stripe defect of the display substrate.

The invention provides a preparation method of a metal interconnection structure and the metal interconnection structure, and the method comprises the steps: forming a first dielectric layer and a plurality of through holes in the first dielectric layer on a substrate on which a semiconductor device layer and a first metal wiring layer are formed, and then employing a flowable organic material as a second dielectric layer on the first dielectric layer, and a plurality of metal grooves are formed in the second dielectric layer, and after the remaining second dielectric layer is cured, the through holes and the metal grooves are filled with second metal to form a metal interconnection structure. The preparation process of the through hole and the metal wire is divided into independent parts according to the sequence, so that the depth-to-width ratio of through hole etching is reduced during preparation of the through hole, and the etching process window is increased; in addition, a curable organic matter is adopted as a dielectric layer of the metal wire, the thickness of photoresist is reduced during preparation of the metal wire, a photoetching process window is increased, and meanwhile, due to the low dielectric constant of the organic matter, the parasitic capacitance between the metal interconnection wires is effectively reduced.

The invention discloses a differential derivative structure circuit based on three-coupling transformation and an amplifier, and relates to the technical field of amplification circuit design. The differential derivative structure circuit comprises a three-coupling inductance network and N output parts. Through a three-coupling transformation mode, power supply of a main amplifier tube and an auxiliary amplifier tube in a differential derivative structure formed by connecting MOS tubes in parallel is integrated into an inductance matching network, so that homologous coupling of the main amplifier tube and the auxiliary amplifier tube on a radio frequency signal path is realized, physical isolation and independent bias control are also realized on a direct current path, and the power supply efficiency is improved. Therefore, a resistor does not need to be used, excessive use of a capacitor is avoided, loss caused by self impedance of the capacitor and ground parasitic capacitance loss are reduced, gain is greatly improved, extra area occupation caused by the capacitor and the resistor is effectively inhibited, and thermal noise introduced by the resistor is eliminated by utilizing the characteristic of low impedance of inductive coupling. Therefore, post-stage noise is effectively suppressed, and the noise coefficient is reduced.

Structure, comprehensive: a plurality of gate structures (110), each comprising a gate material (112); Source and / or drain metallization features (165); a beveled top layer (140) directly on an upper surface of the gate material (112); Sidewall spacers (115) on sidewalls of the gate structures (110); Liners formed from a first material (155) and a second material (180), wherein the first material (155) directly contacts an entire bottom surface of the source and / or drain metallization features (165), wherein the first material (155) is formed from Ti, TiN, TaN, Ru or Co; Contacts in electrical contact with the source and / or drain metallization features (165), which are separated from the gate structures (110) at least by the side wall spacers (115), wherein the first material (155) directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source and / or drain metallization features (165); and Air gap (175) between the first material (155) and the second material (180), wherein the air gap (175) is located next to the side wall spacers (115) and below the beveled top layer (140) and is formed by a selected aspect ratio of the depressions as a result of constriction phenomena, so that a parasitic capacity is reduced.

The invention relates to the technical field of PCB layout wiring, and discloses a method and a device for improving surge capacity between an RJ45 connector and a transformer, and the method comprises the following steps: in a PCB area of the transformer, arranging a non-metal slot at a boundary between a primary side and a secondary side of the transformer; an RJ45 connector is arranged in a PCB area far away from an external interface base of a transformer, a preset linear distance between the RJ45 connector and the interface base is set, the length of a differential wire from the RJ45 connector to the transformer is controlled within the preset length of the differential wire, the differential wire is subjected to roughing processing with preset wire width and keeps continuous, and the RJ45 connector is arranged in the PCB area of the external interface base of the transformer. The accumulation of surge energy in a transmission path is reduced. According to the invention, the inherent isolation axis of the primary-secondary winding of the transformer is accurately aligned through the slotting, the central area with the most concentrated winding coupling is covered, and the conduction path of surge energy through parasitic capacitance between the windings is blocked.

A multilayer filter of an embodiment includes: a first ground layer and a second ground layer; a plurality of conductive pattern layers disposed between the first ground layer and the second ground layer; and a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers, in which adjacent ones of the plurality of conductive pattern layers include a capacitance pattern layer forming a first capacitance, and at least a portion of the plurality of conductive pattern layers may include an inductance pattern layer forming an inductor, the capacitance pattern layer faces each of the first ground layer and the second ground layer to form a parasitic capacitance, and filters a signal having a desired frequency band by using the first capacitor, the inductor, and the parasitic capacitance.

Pixel driver circuit applied to a display field, wherein the display field comprises multiple pixel elements, and wherein the pixel driver circuit comprises the following: a driver module (11) comprising a driver transistor (Tm) whose input terminal (111) is coupled to a driver voltage terminal (VDD) and whose output terminal (112) is coupled to a subpixel element (M); a data write module (12) whose output terminal is coupled between the input terminal (111) of the driver transistor (Tm) and the driver voltage terminal (VDD) and which serves to write a data voltage to the driver transistor (Tm) during a compensation write phase; and a voltage stabilization module (13) coupled to a first control terminal (113) of the driver transistor (Tm) and serves to maintain a stable voltage of the first control terminal (113) of the driver transistor (Tm) during a reset phase; characterized in that the driver transistor (Tm) further comprises a second control terminal (114), wherein the first control terminal (113) in conjunction with an active layer of the driver transistor (Tm) forms a first parasitic capacitance (Cgd), while the second control terminal (114) is coupled to a DC signal terminal, such that the second control terminal (114) and the active layer (4) form a second parasitic capacitance (Cgd2).

The application discloses a capacitor unit and a capacitor array, wherein the capacitor unit comprises: a first electrode plate comprising a plurality of first capacitor layers; a second electrode plate comprising a plurality of second capacitor layers; each of the first capacitor layers and the second capacitor layers comprises a plurality of first interdigital lines arranged in parallel with each other and a plurality of second interdigital lines arranged in parallel with each other; the first interdigital lines of each of the first capacitor layers and the second interdigital lines of the corresponding second capacitor layers in the same layer are interlaced with each other and spaced apart from each other; a first metal layer is arranged on one side of the plurality of first capacitor layers and the plurality of second capacitor layers; the first capacitor layers and the second capacitor layers are respectively provided with a predetermined gap from the first metal layer and are connected to the first metal layer through a via; and a shielding structure surrounds the first electrode plate and the second electrode plate to protect the first capacitor layers and the second capacitor layers in the same layer. In the above manner, the installation area of the capacitor unit is reduced, the consistency of the parasitic capacitance is optimized, the high-integration design is met, the product reliability and yield are improved, and the production cost is reduced.

A manufacturing method for a semiconductor structure includes: providing a Si-supporting substrate having a SiO2 protection layer on a surface of the Si-supporting substrate; thinning the SiO2 protection layer to form a SiO2 intermediate layer; disposing a Si growth substrate on a side, away from the Si-supporting substrate, of the SiO2 intermediate layer; and disposing a device layer on a side, away from the Si-supporting substrate, of the Si growth substrate. The technical solutions of the present disclosure may reduce a possibility of generating parasitic capacitance and leakage current, and greatly improve the reliability of a device.

The application provides a CMOS device and a preparation method thereof, the CMOS device comprising a GaN HEMT device and a diamond PMOS device arranged in a vertical direction, and an isolation layer arranged between the GaN HEMT device and the diamond PMOS device; the GaN HEMT device comprising a GaN layer, an AlGaN layer, a first source, a first gate and a first drain, the diamond PMOS device comprising a hydrogen-terminated diamond layer, a second source, a second drain and a second gate; the first gate and the second gate are arranged in correspondence in the vertical direction and are electrically connected through a first metal filling hole extending in the vertical direction; the first drain and the second drain are arranged in correspondence in the vertical direction and are electrically connected through a second metal filling hole extending in the vertical direction. The COMS device provided by the application has high carrier mobility, low power consumption and high heat dissipation performance, and can reduce parasitic resistance, parasitic capacitance and parasitic inductance, and improve integration density.

The application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein a plurality of active regions are arranged in the substrate; removing part of the substrate to form a groove in the substrate, and at least the active regions are exposed in the groove; forming a bit line contact structure on a region corresponding to the active region in the groove; forming a dielectric layer on the groove, and a gap with a top opening is formed between the dielectric layer and the sidewall of the bit line contact structure; and forming a bit line on the bit line contact structure, and the bit line seals the opening of the gap. The manufacturing method of the semiconductor structure provided by the application can reduce the parasitic capacitance between the bit line contact structure and the storage node contact structure, thereby improving the working reliability of the semiconductor structure.

This invention proposes a three-active half-bridge DC-DC converter and its control method based on device reuse, belonging to the field of power electronics technology. To address the problems of complex architecture and low transmission efficiency in existing dual-active-bridge DC-DC converters, it includes: an FSBB circuit and a TAHB circuit. The FSBB circuit includes an extended half-bridge. HB 0. Energy storage inductor L m and reused half bridge HB 1. The TAHB circuit includes a multiplexed half-bridge. HB 1. Transmission half-bridge HB 2 and transmission half-bridge HB 3. The control method includes: switching the three active half-bridge DC-DC converter to single-input dual-output mode or dual-input single-output mode according to the number of input and output ports in the bidirectional port; setting the control strategy of TAHB circuit and FSBB circuit; and triggering eight working modes in sequence according to the closed / open state of different switching transistors. In each working mode, soft switching of the switching transistor is achieved by discharging the parasitic capacitance of the body diode of the switching transistor through the inductor current, thereby completing the high-efficiency transmission of energy storage.

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate containing a substrate, a floating diffusion region and a source follower, a gate structure of the source follower is located on the upper surface of the substrate, and the floating diffusion region is located on both sides of the gate structure in a first direction; forming an interlayer dielectric layer covering the substrate and the gate structure; forming grooves located on both sides of the gate structure in the interlayer dielectric layer, the bottom of the groove and the top of the gate structure are arranged in a second direction; forming a mask layer covering the sidewall of the groove; etching to form a first contact hole, a second contact hole and a connecting hole connecting the two holes based on the mask layer, the bottom of the first contact hole and the second contact hole respectively exposes the floating diffusion region and the gate structure; forming a low dielectric constant layer covering the sidewall of the first contact hole, the second contact hole and the connecting hole; and forming a connecting structure filling the first contact hole, the second contact hole and the connecting hole and covering the low dielectric constant layer. The semiconductor structure and the preparation method thereof reduce the contact resistance of the device and reduce the parasitic capacitance.

The invention discloses an integrated transformer which comprises a primary winding and a secondary winding, the primary winding comprises four groups of sub-windings which are connected in series, an upper and lower layer staggered balance winding winding structure is adopted, the first group of sub-windings is a starting winding of the primary winding, a first metal winding layer close to the secondary winding is taken as a starting line, and a second metal winding layer close to the secondary winding is taken as a starting line. Sequentially winding m1 turns in parallel from outside to inside; the second group of sub-windings penetrate to the second metal winding layer from the ending position of the m1th turn to sequentially wind m2 turns in parallel from outside to inside; the third group of sub-windings serves as a starting line of the second metal winding layer at the ending position of m2 turns, penetrates to the first metal winding layer and is sequentially wound for n1 turns in parallel from inside to outside; and the fourth group of sub-windings penetrate to the second metal winding layer at the ending position of the n1 turns and are continuously wound for n2 turns in parallel from inside to outside in sequence. Compared with the prior art, the integrated transformer can effectively reduce equivalent parasitic capacitance between the primary winding and the secondary winding by adopting the specific staggered PCB windings on the primary side and the secondary side.

The application provides a touch component and a touch display device. The touch component comprises a touch layer, and the touch layer comprises a plurality of touch units. Each touch unit comprises: a first electrode arranged along a first direction, the first electrode comprising a first trunk electrode extending along the first direction and at least one first branch electrode extending from the first trunk electrode; and a second electrode arranged along a second direction, the second electrode being electrically insulated from the first electrode, the second electrode comprising a second trunk electrode extending along the second direction and at least one second branch electrode extending from the second trunk electrode, and at least part of the first branch electrode and at least part of the second branch electrode are arranged in a cross manner. At least one of the first electrode and the second electrode is provided with a hollow part. By providing the hollow part in at least one of the first electrode and the second electrode, the parasitic capacitance formed between at least one of the first electrode and the second electrode and a cathode of an organic light-emitting diode array layer is reduced.

The application discloses an acceleration sensor and a manufacturing method thereof. The acceleration sensor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor on a substrate. The first capacitor comprises a second detection mass and a first detection electrode. The second capacitor comprises a first detection mass and a first detection electrode. The third capacitor comprises a second detection mass and a second detection electrode. The fourth capacitor comprises a first detection mass and a second detection electrode. The first detection electrode and the second detection electrode are located between the first detection mass and the second detection mass and are independent of each other and located in the same plane. The application forms a full-bridge capacitor detection structure by the first detection mass, the second detection mass, the first detection electrode and the second detection electrode located between the first detection mass and the second detection mass, which can effectively reduce parasitic capacitance, optimize noise, improve stability and sensitivity.

The utility model relates to a kind of high bandwidth current transformer.It includes: mutual inductor body, including mutual inductor shell and the winding assembly being set in the mutual inductor shell, wherein, the winding assembly at least includes winding unit, the winding unit at least includes several turns winding, based on one or more turns winding forms a corresponding winding inductance;The assembly state of winding unit in winding assembly is configured in the mutual inductor shell, to generate parasitic balance capacitor for balancing each turns winding corresponding winding inductance respectively;Distributed component, assembled on winding assembly, including several distribution elements, wherein, one distribution element is connected with the winding of corresponding turns in winding unit, to realize impedance matching between winding inductance and parasitic capacitor.The utility model can effectively improve the frequency bandwidth and measurement accuracy of current transformer, reduce assembly difficulty.

This application provides a lightning transient electric field observation device, relating to the field of meteorological observation. The device comprises a hemispherical induction electrode and a grounding reference plate, which are spaced apart and insulated from each other by a mounting column. Compared to a flat electrode with an equal projected area, the electric field concentration effect of the convex surface of the hemispherical conductor generates a higher equivalent charge collection efficiency. The signal preprocessing module is located on the mounting column near the hemispherical induction electrode and is directly electrically connected to it, structurally minimizing the signal path and avoiding excessive parasitic capacitance. Thus, without increasing the physical size, it improves the response capability to weak electric field changes and enhances the high-frequency response effect.