391 results about "Parasitic capacitor" patented technology

The invention discloses an electricity meter adaptive error compensation method, system and device based on multi-physical coupling and hidden variable modeling and a storage medium, and relates to the technical field of electric energy metering and detection, and the method comprises the steps: constructing a multi-physical coupling basis vector containing a single variable and a cross variable based on a sensing output signal; hidden variable joint modeling is carried out based on the multi-physical coupling basis vector and parasitic capacitance change, magnetic conductivity drift and shunt resistance offset, and a compensation mapping relation of electromagnetic, thermal and stress coupling is formed; generating a compensation coefficient by adopting the compensation mapping relation, and applying the compensation coefficient in an ammeter metering link to complete an error compensation process; according to the method, voltage, current and phase compensation coefficients are generated through multi-physical coupling basis vector and hidden variable modeling, dynamic description and self-adaptive correction of error sources are achieved, dynamic accurate correction of voltage, current and phase is achieved, and it is ensured that the ammeter keeps high-precision metering for a long time under the complex environment and the device drift condition.

The invention discloses a primary and secondary fusion pole-mounted circuit breaker state monitoring system and method, and relates to the technical field of power system automation. The system comprises a native signal acquisition module which is used for multiplexing an inherent electrical loop of a circuit breaker and acquiring a current signal of an opening and closing coil and a capacitive reactance change signal of a parasitic capacitor between a high-voltage electrode and a grounding end; and the edge analysis module is used for processing the signal acquired by the original signal acquisition module, including generating a mechanical health degree through feature extraction and state mapping, calculating an insulation aging index based on capacitive reactance change, and dynamically correcting a monitoring reference in combination with a digital twin model and a filtering algorithm. Non-auxiliary element monitoring is realized by multiplexing the inherent electrical loop of the circuit breaker, so that the service life of the monitoring system and the service life of primary equipment are completely synchronous, and elements do not need to be replaced in the whole life cycle; errors introduced by additional sensors are avoided by using the original electrical signals, and the mechanical fault recognition and insulation state evaluation precision is remarkably improved.

The utility model provides a directional coupler and a radio frequency chip, and relates to the technical field of electronic communication. The directional coupler comprises an input port, an output port, a coupling port, an isolation port and an impedance adjusting network, the impedance adjusting network comprises an access switch, an impedance adjusting module and an inductance unit. The impedance adjusting module comprises an adjustable resistor unit and an adjustable capacitor unit which are connected in parallel; one end of the impedance adjusting module is connected to the isolation port through the access switch, and the other end of the impedance adjusting module is connected to the inductance unit; wherein the inductance unit is used for compensating parasitic capacitance in the directional coupler. According to the scheme, the impedance matching and phase characteristics of the directional coupler can be adjusted according to different working frequencies and environmental conditions through mutual cooperation of the access switch, the impedance adjusting module and the inductance unit, so that the directional coupler can maintain good directivity under various working conditions.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

The invention discloses a low-power-consumption radiation-resistant quadrature voltage-controlled oscillator based on an SOI (Silicon On Insulator) process, relates to the technical field of quadrature voltage-controlled oscillators, and is used for solving the technical problems that an existing quadrature voltage-controlled oscillator is low in radiation resistance in a harsh radiation environment and does not have the characteristic of low power consumption. The invention discloses a low-power-consumption anti-radiation quadrature voltage-controlled oscillator based on an SOI process. The low-power-consumption anti-radiation quadrature voltage-controlled oscillator comprises a first voltage-controlled oscillator, a second voltage-controlled oscillator, a first tail filter and a second tail filter, the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively form an LC resonant cavity with a parasitic capacitor of an inductor and a varactor through the inductor; the first tail filter is connected with the first voltage-controlled oscillator, and the second tail filter is connected with the second voltage-controlled oscillator; two inductors of the first tail filter and the second tail filter are coupled; lC resonant cavities of the first voltage-controlled oscillator and the second voltage-controlled oscillator output oscillation waveforms, and negative impedance is formed through configured transistor pairs, so that the waveforms are output constantly.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source / drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source / drain opening, and forming a source / drain feature in the source / drain opening and over the isolation layer, wherein the source / drain feature is spaced apart from the isolation layer by an air gap.

The invention provides an image sensor. The image sensor comprises a substrate; the transmission gate is located on the substrate, and the floating diffusion region is located in the substrate on one side of the transmission gate; the source following grid electrode is located on the substrate, and the source following source region and the source following drain region are located in the substrate on the two sides of the source following grid electrode respectively; the MOM capacitor is located on the side, away from the substrate, of the transmission grid electrode and the source following grid electrode, and the floating diffusion region and the source following source region are electrically connected through the MOM capacitor. According to the invention, the MOM capacitor is connected between the floating diffusion region and the source following source region, so that the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the signal-to-noise ratio of the device can be improved, thereby improving the reading noise reduction capability of the image sensor.

The invention discloses a driving method, a display device, display equipment and a computer readable storage medium, and the method comprises the steps: determining an xth data line and an (x + 1) th data line in a driving chip, obtaining a first voltage of a first sub-pixel of a current updating line of an xth column of sub-pixels corresponding to the xth data line, determining an influence factor of each sub-pixel on the (x + 1)-th data line according to the voltage difference of the display gray scale of each sub-pixel on the (x + 1)-th data line, and determining a first correlation quantity according to the influence factor of the sub-pixel on the (x + 1)-th row before the first sub-pixel, determining a second correlation quantity according to the influence factor of the sub-pixel on the (x + 1) th row after the first sub-pixel, obtaining a compensation value based on the first preset value, the first correlation quantity and the second correlation quantity, obtaining a second voltage according to the compensation value and the first voltage value, and transmitting the second voltage to the first sub-pixel, the voltage interference of the first sub-pixel caused by a parasitic capacitance coupling effect is reduced, and abnormal display on a display screen is eliminated.

A low-voltage integrated power distribution architecture and a vehicle. The low-voltage integrated power distribution architecture comprises a high-voltage input end (110), a DCDC circuit (200), a low-voltage management circuit (400), a low-voltage power distribution circuit (300), and a low-voltage battery (500); the low-voltage power distribution circuit (300) is provided with a low-voltage power supply end (120) for connection to a low-voltage load; one end of the low-voltage power distribution circuit (300) is connected to the low-voltage battery (500) by means of the low-voltage management circuit (400); and the other end of the low-voltage power distribution circuit (300) is connected to a high-voltage input end (110) by means of the DCDC circuit (200). By integrating the DCDC circuit (200), the low-voltage management circuit (400), the low-voltage power distribution circuit (300), and the low-voltage battery (500) together and reusing a same controller (600), the function of managing the low-voltage management circuit (400), the low-voltage power distribution circuit (300), and the DCDC circuit (200) is integrated in the controller (600). The weight and size of the power distribution architecture are reduced, and the probability of parasitic inductance or parasitic capacitance between the DCDC circuit (200) and the low-voltage battery (500) causing damage to circuits in the vehicle is reduced.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

The application discloses an in-cell touch display panel, which comprises a color film substrate, an array substrate and a liquid crystal layer sandwiched between the color film substrate and the array substrate; the touch electrode is hollowed out to reduce the parasitic capacitance between the pixel touch electrode and the scanning line, and a BM barrier is arranged above the corresponding CF of the touch electrode hollowing-out part; the BM covers the touch electrode hollowing-out part with a certain distance, so as to avoid the light leakage caused by the influence of the scanning line voltage on the liquid crystal deflection. The size of the overlapping area between the touch electrode and the scanning line is designed to be consistent at the edge and the middle of the touch electrode TP block, so that the parasitic capacitance between the touch electrode and the scanning line is consistent at the edge and the middle of the touch electrode TP block; the wires are arranged in the horizontal and vertical directions in the touch electrode TP block to reduce the impedance. The application solves the problem of uneven display brightness of the in-cell touch display panel.

The utility model provides a laser radar circuit and laser radar equipment, and relates to the technical field of laser radars. The laser radar circuit comprises a controller, a receiving module, a transmitting module and a digital processing module. The control module is electrically connected with the receiving module, the transmitting module and the digital processing module. The receiving module comprises a receiver and a matching capacitor. The capacitance value of a parasitic capacitor of the receiver is equal to the capacitance value of the matching capacitor. In the laser radar circuit provided by the invention, the capacitance value of the parasitic capacitor of the receiver is equal to the capacitance value of the matching capacitor, so that impedance matching can be more effectively realized, signal reflection and transmission loss can be reduced, noise in the circuit can be reduced, the signal-to-noise ratio of signals can be improved, electromagnetic interference can be effectively reduced, and the reliability of the laser radar circuit can be improved. The background noise of the optical receiver is effectively reduced, and the overall performance of the laser radar system is improved.

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

A touch display device according to embodiments of the disclosure may comprise a substrate including a display area and a non-display area adjacent to the display area, a pixel electrode disposed on the substrate, a common electrode disposed on the pixel electrode, a first inorganic encapsulation layer disposed on the common electrode, an organic encapsulation layer disposed on the first inorganic encapsulation layer, a second inorganic encapsulation layer disposed on the organic encapsulation layer, and a touch sensor disposed on the second inorganic encapsulation layer. A dielectric constant of the first inorganic encapsulation layer may be smaller than a dielectric constant of the second inorganic encapsulation layer, and a dielectric constant of the organic encapsulation layer may be smaller than the dielectric constant of the first inorganic encapsulation layer. This layered encapsulation structure may reduce parasitic capacitance and enhance touch sensitivity while maintaining improved resistance to moisture and oxygen permeation.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

The application discloses a broadband multi-stage Gysel power divider based on an IPD process, comprising a microstrip structure layer, and first and second dielectric substrates and a ground metal layer; the microstrip structure layer adopts a multi-layer nested structure, each layer of the nested structure is formed by cascading multi-stage Gysel power division units, and is arranged on the upper surface and the interior of the first dielectric substrate, so that an integrated layout based on the IPD process is formed, and a planar spiral structure, an air bridge, a parallel plate capacitor, a thin film resistor and a layered ground unit structure are integrated; the planar spiral structure is equivalent to a specific characteristic impedance transmission line, the air bridge structure solves cross interference and suppresses a parasitic capacitor, the parallel plate capacitor structure calibrates equivalent reactance parameters, the thin film resistor effectively improves port isolation and heat dissipation, and the layered ground unit structure strengthens heat dissipation and ground reliability. The application can realize stable power distribution in a wide frequency band, and is suitable for the integration requirements of high-frequency, high-power and small-sized radio frequency front ends.

The invention relates to the technical field of integrated circuits, and discloses an ESD circuit for power supply clamping, and the ESD circuit comprises a quick starting circuit, a detection circuit and a bleeder circuit which are connected in sequence. The quick starting circuit comprises a sensing branch and a logic control generation branch; the sensing branch is configured to generate a trigger voltage through a parasitic capacitor in an MOS tube in the branch when electrostatic charges reach a power supply port; the logic control generation branch is connected with the output end of the sensing branch and is configured to generate a trigger signal based on the trigger voltage; wherein the trigger signal is used for controlling the detection circuit to be started and generating a starting signal, so as to control the discharge circuit to discharge electrostatic charges through the starting signal. According to the circuit, the bleeder circuit can be opened in time, so that the possibility that electrostatic charges break down an internal protected circuit is reduced. The invention also discloses a chip.

A pixel circuit and a display device are disclosed. A display device may include a plurality of subpixels that each include: a light emitting element; a driving transistor configured to operate the light-emitting element by receiving a data voltage; a switching transistor configured to apply the data voltage to a gate electrode of the driving transistor; the light-emitting element including a cathode and an anode, the anode being connected to a source electrode of the driving transistor, the cathode being electrically connected to a low-potential voltage supply line, in which the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, and in which an intermediate electrode line that traverses a storage capacitor of the subpixels composes a first parasitic capacitor with the gate electrode of the driving transistor and composes a second parasitic capacitor with the source electrode of the driving transistor.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The application provides a double Buck-Boost conversion device, which comprises a circuit board and three-phase conversion units arranged on the circuit board, the direct current side of each phase conversion unit is connected with a direct current source, and the alternating current side of each phase conversion unit is connected with a three-phase alternating current source; the circuit board is divided into three types of regions according to dv / dt, and the signal lines of bus capacitors, switch units, alternating current inductors and filter capacitors and other devices are divided into dynamic signals and static signals according to the type of emitted signals, and then the signal lines are routed on the static region, the dynamic region and the dynamic-static combined region of the circuit board, so that the layout of the conversion circuit is optimized, the interlayer parasitic capacitance is reduced, and the electromagnetic radiation is optimized.

The application provides a display substrate and a display device. The display substrate comprises a substrate, a sub-pixel, a data line and a selection switch. The substrate comprises a display area and a peripheral area. The sub-pixel and the data line are located in the display area, and the selection switch is located in the peripheral area. The selection switch comprises a first selection switch and a second selection switch located on both sides of the first selection switch. The data lead comprises a plurality of first data leads and a plurality of second data leads. The first selection switch and the second selection switch are electrically connected with the first data lead and the second data lead respectively. The width of at least part of the line segment in the first data lead is greater than the width of at least part of the line segment in the second data lead. The width of the first data lead and the second data lead is set, which can effectively reduce the parasitic capacitance difference between different areas, thereby effectively improving the dark stripe defect of the display substrate.

The invention provides a preparation method of a metal interconnection structure and the metal interconnection structure, and the method comprises the steps: forming a first dielectric layer and a plurality of through holes in the first dielectric layer on a substrate on which a semiconductor device layer and a first metal wiring layer are formed, and then employing a flowable organic material as a second dielectric layer on the first dielectric layer, and a plurality of metal grooves are formed in the second dielectric layer, and after the remaining second dielectric layer is cured, the through holes and the metal grooves are filled with second metal to form a metal interconnection structure. The preparation process of the through hole and the metal wire is divided into independent parts according to the sequence, so that the depth-to-width ratio of through hole etching is reduced during preparation of the through hole, and the etching process window is increased; in addition, a curable organic matter is adopted as a dielectric layer of the metal wire, the thickness of photoresist is reduced during preparation of the metal wire, a photoetching process window is increased, and meanwhile, due to the low dielectric constant of the organic matter, the parasitic capacitance between the metal interconnection wires is effectively reduced.

The present application provides an inductor component capable of reducing the parasitic capacitance between a coil and an external electrode. The inductor component includes a core, a coil, a first external electrode, and a second external electrode. The core has a first end surface and a second end surface at both end sides in a length direction. The first external electrode and the second external electrode are respectively provided at the first end surface side and the second end surface side with respect to the center of the length direction of the core and are exposed from the outer surface of the core. At least a part of the portion of the first external electrode exposed from the outer surface of the core and at least a part of the portion of the second external electrode exposed from the outer surface of the core do not overlap each other when viewed from the first end surface side in the length direction. The center of gravity of the area of the portion of the first external electrode exposed from the outer surface of the core and the center of gravity of the area of the portion of the second external electrode exposed from the outer surface of the core are located on opposite sides with respect to the center of the width direction of the core.

Techniques are provided herein to form semiconductor devices with gate structures that do not extend below a top surface of dielectric subregions. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the fin of semiconductor material includes a subfin adjacent to a dielectric fill. A sacrificial material layer is deposited before the formation of the gate structure to prevent the gate structure from forming along the sides of the subfin. This sacrificial layer may then be removed from the backside of the structure along with the semiconductor material of the subfin. The subfin area may be replaced with one or more dielectric materials formed on the backside. As a result, the device performance is improved by lowering the parasitic capacitance caused by having the gate structure on either side of the dielectric structure replacing the subfin region.

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source / drain contact over a source / drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source / drain contact, a gate contact via over and electrically coupled to the gate structure, and a source / drain contact via over and electrically coupled to the source / drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source / drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source / drain contact via and the liner.

The invention discloses a differential derivative structure circuit based on three-coupling transformation and an amplifier, and relates to the technical field of amplification circuit design. The differential derivative structure circuit comprises a three-coupling inductance network and N output parts. Through a three-coupling transformation mode, power supply of a main amplifier tube and an auxiliary amplifier tube in a differential derivative structure formed by connecting MOS tubes in parallel is integrated into an inductance matching network, so that homologous coupling of the main amplifier tube and the auxiliary amplifier tube on a radio frequency signal path is realized, physical isolation and independent bias control are also realized on a direct current path, and the power supply efficiency is improved. Therefore, a resistor does not need to be used, excessive use of a capacitor is avoided, loss caused by self impedance of the capacitor and ground parasitic capacitance loss are reduced, gain is greatly improved, extra area occupation caused by the capacitor and the resistor is effectively inhibited, and thermal noise introduced by the resistor is eliminated by utilizing the characteristic of low impedance of inductive coupling. Therefore, post-stage noise is effectively suppressed, and the noise coefficient is reduced.

Structure, comprehensive: a plurality of gate structures (110), each comprising a gate material (112); Source and / or drain metallization features (165); a beveled top layer (140) directly on an upper surface of the gate material (112); Sidewall spacers (115) on sidewalls of the gate structures (110); Liners formed from a first material (155) and a second material (180), wherein the first material (155) directly contacts an entire bottom surface of the source and / or drain metallization features (165), wherein the first material (155) is formed from Ti, TiN, TaN, Ru or Co; Contacts in electrical contact with the source and / or drain metallization features (165), which are separated from the gate structures (110) at least by the side wall spacers (115), wherein the first material (155) directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source and / or drain metallization features (165); and Air gap (175) between the first material (155) and the second material (180), wherein the air gap (175) is located next to the side wall spacers (115) and below the beveled top layer (140) and is formed by a selected aspect ratio of the depressions as a result of constriction phenomena, so that a parasitic capacity is reduced.

The invention relates to the technical field of PCB layout wiring, and discloses a method and a device for improving surge capacity between an RJ45 connector and a transformer, and the method comprises the following steps: in a PCB area of the transformer, arranging a non-metal slot at a boundary between a primary side and a secondary side of the transformer; an RJ45 connector is arranged in a PCB area far away from an external interface base of a transformer, a preset linear distance between the RJ45 connector and the interface base is set, the length of a differential wire from the RJ45 connector to the transformer is controlled within the preset length of the differential wire, the differential wire is subjected to roughing processing with preset wire width and keeps continuous, and the RJ45 connector is arranged in the PCB area of the external interface base of the transformer. The accumulation of surge energy in a transmission path is reduced. According to the invention, the inherent isolation axis of the primary-secondary winding of the transformer is accurately aligned through the slotting, the central area with the most concentrated winding coupling is covered, and the conduction path of surge energy through parasitic capacitance between the windings is blocked.

A multilayer filter of an embodiment includes: a first ground layer and a second ground layer; a plurality of conductive pattern layers disposed between the first ground layer and the second ground layer; and a dielectric layer disposed between the first and second ground layers and the plurality of conductive pattern layers, in which adjacent ones of the plurality of conductive pattern layers include a capacitance pattern layer forming a first capacitance, and at least a portion of the plurality of conductive pattern layers may include an inductance pattern layer forming an inductor, the capacitance pattern layer faces each of the first ground layer and the second ground layer to form a parasitic capacitance, and filters a signal having a desired frequency band by using the first capacitor, the inductor, and the parasitic capacitance.

A multi-feed antenna with a shared radiator comprises a ground capacitor, a first antenna module, a second antenna module, a first feed-in module, a second feed-in module and at least one sensing module. The first antenna module is grounded through the ground capacitor. The second antenna module is coupled with the first antenna module. The first feed-in module and the second feed-in module are connected with the second antenna module, and the first feed-in module and the second feed-in module are used to receive or send radio frequency signals through the first antenna module and the second antenna module. The at least one sensing module is connected with the first antenna module or the second antenna module, and the at least one sensing module is used to sense a capacitance value of a parasitic capacitance of the first antenna module or the second antenna module.