841 results about "Parasitic capacitor" patented technology

Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.

Apparatus for cancelling electromagnetic interference (EMI) during power conversion. In one embodiment, the apparatus comprises a power converter for converting a DC input to a DC output, wherein the power converter comprises a transformer having a primary winding and a secondary winding, the secondary winding coupled to a diode such that a plurality of secondary winding voltages cause a balanced current flow through a plurality of parasitic capacitances.

Disclosed is an organic light emitting display which has a scan driver to supply scan signals to a plurality of scan lines, a data driver to supply data signal to output lines, with a demultiplexer on each output line to supply the data signal to a plurality of data lines is disclosed. The display also has a pixel portion comprising pixels connected to the scan lines, the data lines, and pixel power source lines. There is also a power source line placed between the pixel portion and the data driver to supply first power to the pixel power source lines, and a parasitic capacitor formed on each data line to charge voltage corresponding to the data signal. With this configuration, the number of output lines provided in a data driver is decreased, and an image is displayed with uniform brightness.

Fabrication methods for capacitive micromachined ultrasonic transducers (CMUTS) with independent and precise gap and post thickness control are provided. The fabrication methods are based on local oxidation or local oxidation of silicon (LOCOS) to grow oxide posts. The process steps enable low surface roughness to be maintained to allow for direct wafer bonding of the membrane. In addition, methods for fabricating a step in a substrate are provided with reduced or minimal over-etch time by utilizing the nonlinearity of oxide growth. The fabrication methods of the present invention produce CMUTs with unmatched uniformity, low parasitic capacitance, and high breakdown voltage.

A method is provided for driving a liquid crystal display having a multi-channel single-amplifier structure, where the number of times of coupling according to video signals transmitted to adjacent source lines while the source lines are floated is 3 and it is equal for the respective source lines for 6 frames, noise aspects of the respective source lines are similarly repeated for every 6 frames, kick-back noise compensation is uniformly applied to the source lines S_r, S_g and S_b with noise of the 6 frames averaged, and charge sharing time of parasitic capacitors between the source lines and charge sharing time of capacitors of liquid crystal cells become similar to each other.

A pixel includes a first subpixel and a second subpixel. The first subpixel includes a first switching element connected to a first gate line and a data line, a first liquid crystal capacitor connected to the first switching element, and a first storage capacitor connected to the first switching element. The second subpixel includes a second switching element connected to a second gate line and the data line, a second liquid crystal capacitor connected to the second switching element, and a second storage capacitor connected to the second switching element. At least one of a ratio of capacitances between a first parasitic capacitor formed in the first switching element and a second parasitic capacitor formed in the second switching element and a ratio of capacitances between the first storage capacitor and a second storage capacitor is determined based on a ratio of the first liquid crystal capacitor and the second liquid crystal capacitor.

A capacitance type microphone with a stress release membrane prepared at a low temperature and a preparation method thereof. The capacitance type microphone includes a substrate having at least a resonant cavity; a septum, arranged on the top of the resonant cavity and connected with the substrate for implementing a mechanical vibration when being excitated by an acoustic pressure wave; a back board, arranged on the top of the septum and having a plurality of perforations; an air gap is provided the back board and the septum; a capacitor is composed of the septum, the air gap and the back board. The method includes steps: forming the resonant cavity on the substrate; forming the septum on the top of the resonant cavity, wherein the septum is connected with the substrate; setting the back board on the top of the septum, wherein the back board has a plurality of perforations; forming the air gap between the back board and the septum. The invention is a MEMS capacitance type microphone processed by a completely low-temperature technique. It is capable of being used as a post IC circuit processing technique being compatible thereof. The structure of the vibration diaphragm of the capacitance type microphone is a stress-releasing structure, and is capable of reducing a parasitic capacitance. Comparing with the traditional initial stress release membrane, the invention improves the sensitivity of the microphone more effectively.

In a display, capacitors are charged with first precharge voltages at the time of applying selection signals to previous scan lines. A data driver divides a plurality of data lines into a plurality of groups each of which consists of at least one data line and applies corresponding data voltages to the data lines of respective groups sequentially. The display further includes a precharge means, and such precharge means applies second precharge voltages to data lines of at least one group before selection signals for selecting scan line are applied to the scan line connected to the pixel circuits and stops application of the second precharge voltages before corresponding data voltages are applied to the respective groups. In this way, it is possible to solve the problem of poor images due to charge redistribution of the capacitors caused by previous data voltages stored in parasitic capacitors.

The invention belongs to the field of LED (light-emitting diode) drive control, and provides a blanking control circuit for LED (light-emitting diode) display screens and an LED drive chip. According to the invention, by adopting the blanking control circuit (comprising a time-sequence control module and a blanking module) for the LED (light-emitting diode) display screens, in the line scanning process of an LED display screen, the blanking module charges parasitic capacitors in each line of the LED display screen in a time gap generated by scanning every two lines of LEDs so to achieve the purpose of effectively eliminating a smearing phenomenon; meanwhile, a drive circuit module realizes the accurate constant current control on each line of LEDs on the LED display screen, so that the image display quality of the LED display screen is improved, thereby solving the problem that in the prior art, the display quality of the LED display screen is low because the accurate constant current control on LEDs can not be realized.

In a conventional liquid crystal display panel using a metallic film as a light shielding mask of a color filter, there arose a problem in that a parasitic capacitor with the other wiring is generated to often cause a delay in signal. Further, there arose a problem in that, if an organic film containing a black pigment is used as the light shielding film of the color filter, the manufacturing step thereof increases. In the present invention, lamination films of colored layers consisting of two layers (lamination film of a red-colored layer and a blue-colored layer, or lamination film of a red-colored layer and a green-colored layer) are formed on an opposing substrate as light shielding portions so as to overlap with TFTs on a device substrate without forming a light-shielding mask (black matrix).

The invention provides an electric field fingerprint recognition device, a state control method thereof and a prosthesis identification method. The electric field fingerprint recognition device comprises a signal acquisition module and a signal processing module. When a measurement state signal processing unit is electrically connected with a signal acquisition unit, a to-be-measured state signal processing unit is at least electrically connected with at least one signal collection unit at the periphery of the measurement state signal processing unit. The charging and discharging processes of a sensing capacitor which is electrically connected to the measurement state signal processing unit and the to-be-measured state signal processing unit, and the charging and discharging quantity of electricity of a parasitic capacitor between the measurement state signal processing unit and the to-be-measured state signal processing unit is inhibited. The device and the methods have the advantages of simple structure and saving of device cost, a problem of mutual interference between signal collection units is avoided, the fingerprint recognition device can be suitable for various application requirements, a prosthesis finger fingerprint can be judged, and the safety and the reliability of the fingerprint identification device are improved.

The invention relates to a cavity-type film bulk acoustic resonator (FBAR), consisting of a silicon on insulator (SOI) substrate with a cavity and a piezoelectric thin film transducer arranged on the substrate. The FBAR is characterized in that the surface of the substratum silicon slice in the SOI substrate with the cavity is provided with a groove, substratum silicon slice and top-layer silicon are bonded to form a closed cavity structure; the upper of the top-layer silicon is provided with a transducer which is composed of a piezoelectric thin film and thin electrodes plated on the upper surface and the lower surface of the piezoelectric thin film; and a resonator can be tuned, and the thickness of the top-layer silicon can be regulated through controlling the etching time of the top-layer silicon on the upper of the cavity, thus the resonant frequency of the resonator can be regulated. As the preset cavity structure is used, in the invention, no sacrificial layer is needed, thus the chemical mechanical polishing process and the sacrificial layer release process in aboard patents and products, which are used for treating the sacrificial layer are not required; and meanwhile, in the invention, the advantages of small source parasitic capacitance, small drain parasitic capacitance, low voltage, low power consumption and the like of an SOI material are integrated, therefore, the FBAR can be compatible with an integrated circuit (IC), is easy to integrate, has simple process and is applicable to mass production.

The invention discloses a drive circuit for a P type power MOS switch tube. A push-pull drive circuit and a floating voltage division circuit are connected between a source electrode and a grid electrode of the P type power MOS switch tube. The push-pull drive circuit rapidly controls the charging and discharging of a parasitic capacitor inside the P type power MOS tube by transient current generated when triodes Q1 and Q2 are in alternates; and the floating voltage division circuit provides a stable voltage value of a negative pulse grid source for the P type power MOS tube, thereby improving the dynamic property of the P type power MOS tube and reducing the switch loss of the P type power MOS tube as well as having the advantages of stability, reliability, flexible control and low energy consumption, and the like.

The invention discloses a high-performance output driving circuit, which comprises an output logic unit, a level conversion unit, a buffer unit and an output stage, wherein the output logic unit is used for converting DOUT output by a chip core into two paths of controlled output signals under the control of an enable signal E; THE level conversion unit is used for converting the two paths of controlled output signals with low power supply voltage level of the chip core into two paths of controlled high-voltage output signals with high power supply voltage level of an IO interface circuit, andoutputting the two paths of controlled high-voltage output signals to the buffer unit; the buffer unit is used for increasing driving capacity stage by stage, so as to drive a large-size MOS transistor of the output state; and the output stage is used for transmitting an output signal OUT to a welding pad so as to provide a driving current required for driving a peripheral circuit, and driving anoutput load. By adopting the high-performance output driving circuit, the influence of voltage variations of a parasitic resistor on the operation of an entire output circuit can be effectively reduced when a parasitic capacitor is being charged and discharged by means of a high power supply voltage VCCIO and ground VSSIO of the IO interface circuit, and the reliability of operation of the outputcircuit can be improved.

A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line. A capacitance value of a parasitic capacitor formed between the first pixel electrode and the second pixel electrode is smaller than a capacitance value of a parasitic capacitor formed between the first pixel electrode and the third pixel electrode.