774 results about "Parasitic capacitor" patented technology

The invention discloses an electricity meter adaptive error compensation method, system and device based on multi-physical coupling and hidden variable modeling and a storage medium, and relates to the technical field of electric energy metering and detection, and the method comprises the steps: constructing a multi-physical coupling basis vector containing a single variable and a cross variable based on a sensing output signal; hidden variable joint modeling is carried out based on the multi-physical coupling basis vector and parasitic capacitance change, magnetic conductivity drift and shunt resistance offset, and a compensation mapping relation of electromagnetic, thermal and stress coupling is formed; generating a compensation coefficient by adopting the compensation mapping relation, and applying the compensation coefficient in an ammeter metering link to complete an error compensation process; according to the method, voltage, current and phase compensation coefficients are generated through multi-physical coupling basis vector and hidden variable modeling, dynamic description and self-adaptive correction of error sources are achieved, dynamic accurate correction of voltage, current and phase is achieved, and it is ensured that the ammeter keeps high-precision metering for a long time under the complex environment and the device drift condition.

The high-density POP packaging structure comprises a temporary bonding carrier, a plurality of layers of RDL redistribution lines are arranged on the temporary bonding carrier, openings are formed in the plurality of layers of RDL redistribution lines through photoresist exposure, copper columns are arranged at the photoresist openings, first chips are mounted on the plurality of layers of RDL redistribution lines, and second chips are mounted on the plurality of layers of RDL redistribution lines. A connecting circuit is arranged on the first chip, a first plastic package material wraps the outer walls of the first chip, the connecting circuit and the copper column, a high-density RDL is arranged at the outer ends of the copper column and the connecting circuit, a second chip is mounted on the high-density RDL in an inverted manner through micro bumps, a second plastic package material wraps the outer wall of the second chip, and the second plastic package material wraps the outer wall of the second chip. Balls are arranged on the back face of the multiple layers of RDL redistribution lines. According to the invention, the substrate is replaced by the wafer-level high-density RDL, so that the interconnection density is improved, and the packaging of multiple chips is realized; the vertical routing technology is adopted, the packaging size is reduced, parasitic capacitance and parasitic resistance generated by signal transmission are reduced, and the signal transmission efficiency is improved.

The invention discloses a primary and secondary fusion pole-mounted circuit breaker state monitoring system and method, and relates to the technical field of power system automation. The system comprises a native signal acquisition module which is used for multiplexing an inherent electrical loop of a circuit breaker and acquiring a current signal of an opening and closing coil and a capacitive reactance change signal of a parasitic capacitor between a high-voltage electrode and a grounding end; and the edge analysis module is used for processing the signal acquired by the original signal acquisition module, including generating a mechanical health degree through feature extraction and state mapping, calculating an insulation aging index based on capacitive reactance change, and dynamically correcting a monitoring reference in combination with a digital twin model and a filtering algorithm. Non-auxiliary element monitoring is realized by multiplexing the inherent electrical loop of the circuit breaker, so that the service life of the monitoring system and the service life of primary equipment are completely synchronous, and elements do not need to be replaced in the whole life cycle; errors introduced by additional sensors are avoided by using the original electrical signals, and the mechanical fault recognition and insulation state evaluation precision is remarkably improved.

A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source / drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and / or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and / or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.

The utility model provides a directional coupler and a radio frequency chip, and relates to the technical field of electronic communication. The directional coupler comprises an input port, an output port, a coupling port, an isolation port and an impedance adjusting network, the impedance adjusting network comprises an access switch, an impedance adjusting module and an inductance unit. The impedance adjusting module comprises an adjustable resistor unit and an adjustable capacitor unit which are connected in parallel; one end of the impedance adjusting module is connected to the isolation port through the access switch, and the other end of the impedance adjusting module is connected to the inductance unit; wherein the inductance unit is used for compensating parasitic capacitance in the directional coupler. According to the scheme, the impedance matching and phase characteristics of the directional coupler can be adjusted according to different working frequencies and environmental conditions through mutual cooperation of the access switch, the impedance adjusting module and the inductance unit, so that the directional coupler can maintain good directivity under various working conditions.

Techniques for rejecting apparent (but false) touches caused by objects such as water droplets located in areas with parasitic capacitive paths to ground are disclosed. To minimize these false touches, one or more guard conductors can be located in proximity to the housing and driven with a stimulation signal to shield objects from being capacitively coupled to ground through the housing. In some examples images of touch can be obtained from a non-bootstrapped or bootstrapped scan and also an extended bootstrapped scan wherein the guard conductor is driven with a stimulation signal that has the same characteristics as the stimulation signal being applied to the sensed touch nodes. In some examples, the results of the extended bootstrapped scan can be subtracted from the non-bootstrapped or bootstrapped scan to identify and reject apparent touches resulting from capacitive coupling to ground.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a mask layer on the substrate, and enabling the mask layer to expose an area, where a high-resistance structure needs to be formed, in the substrate; injecting ions into the region by adopting an ion injection process; and removing the mask layer and carrying out an annealing process, forming an insulating buried layer in the region, and forming a crystal layer on the insulating buried layer so as to form a high-resistance structure comprising the insulating buried layer and the crystal layer. The semiconductor device comprises a substrate and a high-resistance structure, and the high-resistance structure comprises an insulating buried layer located in the substrate and a crystallization layer located on the insulating buried layer. According to the invention, the high-resistance structure is formed in the substrate, the resistance uniformity of the high-resistance structure is improved, the thickness of an interlayer dielectric layer formed subsequently is reduced, and the parasitic capacitance and the power consumption of the semiconductor device are reduced.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage VN collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage VP at a non-inverting input terminal of the AD converter, and converts a value of (VP−VN) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.

A flyback converter comprising: a transformer having a primary side winding and a secondary side winding; a primary side switch located at the primary side of the transformer; two secondary side switches located at the secondary side of the transformer; in which the two secondary side switches are connected in parallel and have different characteristics; and a control unit configured to generate a rectification signal and a Zero Voltage Switching (ZVS) pulse and to drive the two secondary side switches; in which a secondary side switch is driven by the rectification signal and the other secondary side switch is driven by the ZVS pulse. At the end of a switching cycle, before turning on the primary side switch: the control unit is configured to generate the ZVS pulse in the secondary side winding such that the parasitic capacitor of the primary side switch is discharged, and to consequently turn on the primary side switch in ZVS conditions or near ZVS conditions.

The invention discloses a common-mode electromagnetic interference modeling and suppression method for a matrix converter, and the method comprehensively considers high-frequency parameters and topological characteristics, builds a conduction CM EMI equivalent circuit model of the matrix converter, completes the impedance network fitting of key elements and the extraction of high-frequency parasitic parameters, and achieves the modeling and suppression of the common-mode electromagnetic interference of the matrix converter. The precision of the CM EMI model of the matrix converter is improved, and the analysis of the CM EMI characteristics of the matrix converter is simplified. According to the common-mode electromagnetic interference suppression method for the matrix converter, CM EMI characteristics of the matrix converter are analyzed, a low-attenuation loop in the converter is constructed by adopting a method of combining a neutral line leading-back type structure and increasing output filter capacitor neutral-point-to-ground parasitic capacitance, the propagation proportion of noise in a linear impedance stabilization network measurement branch is reduced, and the measurement accuracy of the common-mode electromagnetic interference suppression method for the matrix converter is improved. And effective suppression of low-cost CM EMI noise is realized on the premise of not depending on an input EMI filter.

The invention relates to the technical field of integrated circuits, and discloses a switching circuit comprising a charging and discharging module which comprises an energy storage unit and a load unit, the first end of the energy storage unit is connected with an input signal, and the second end of the energy storage unit is connected with the first end of the load unit; the discharge module is connected in parallel with the energy storage unit, and the discharge module can absorb electric energy flowing to the energy storage element from a parasitic capacitor in the switching circuit in a conducting state; the reverse current detection module is connected with the second end of the energy storage unit and is used for detecting reverse current flowing to the energy storage unit from the load unit and outputting a first signal according to the state of the reverse current; and the logic module is connected with the output ends of the charging and discharging module and the reverse current detection module and the input end of the discharge module, and is used for performing logic operation on the at least one control signal and the first signal and controlling the on-off of the discharge module based on the result of the logic operation. According to the switching circuit, the ringing phenomenon of the switching circuit can be avoided.

The invention relates to a method and circuit for analyzing and reconstructing current type digital active EMI filtering based on a switching frequency spectrum, and the method comprises the steps: obtaining initial common-mode noise data and initial differential-mode noise data of a Buck circuit at a switching frequency point; constructing a common-mode equivalent circuit and a differential-mode equivalent circuit comprising a noise source, a compensation voltage source, a compensation capacitor, a parasitic capacitor and LISN impedance, and calculating initial compensation voltage common-mode data and initial compensation voltage differential-mode data of each frequency point to obtain initial compensation voltage data; synchronously outputting the initial compensation voltage data through a DAC (Digital-to-Analog Converter), and performing initial noise compensation; and measuring noise voltage on the LISN as noise source voltage, calculating to obtain secondary compensation voltage data, and carrying out superposition iteration on the compensation voltage data. The method is suitable for a scene with common-mode noise as a main part, can realize common-mode and differential-mode composite suppression without detection and size reduction, and continuously optimizes an EMI suppression effect through iterative updating.

The invention relates to a filtering connector, in particular to a high-speed and low-speed signal mixed-loading filtering connector, which comprises a shell, a plate-type capacitor is arranged in the shell, and a plurality of capacitor hole positions are distributed on the plate-type capacitor; an insulating sleeve penetrates through a part of the capacitor hole positions, and a high-speed contact piece penetrates through the insulating sleeve; an elastic piece penetrates through the other part of capacitor holes, a low-speed contact piece penetrates through the elastic piece, and a grounding spring is arranged between the plate-type capacitor and the inner wall of the shell, so that filter conduction of the low-speed contact piece, the plate-type capacitor and the shell is realized; and insulating structures are arranged in the inner cavity of the shell on two sides of the plate-type capacitor. For the condition that signals transmitted by the connector comprise high-speed signals, low-speed signals and power signals and the number of cores is large, the low-speed signals and the power signals are filtered, and the high-speed signals are subjected to stray capacitance reduction processing, so that equipment using the connector can pass an electromagnetic compatibility test, and the high-speed signals are normally transmitted.

A display apparatus includes: a display panel in which a display region including first to third regions is defined, and which includes a first data line and a second data line connected to first and second pixels of the first and second regions; a driving transistor, a sampling transistor, and a data supply transistor included in each of the first and second pixels; a vertical link line in the first region, and forming a parasitic capacitance with a first node of the first pixel; a horizontal link line in the third region, and connecting the vertical link line and the second data line; and a data compensation portion which calculates a voltage coupling amount caused in the first pixel according to a change of data voltage applied to the vertical link line and provided to the second pixels during the sampling section after the data writing section of the first pixel, calculates a compensation value for the voltage coupling amount, and applies the compensation value to a first input image data of the first pixel to generate a compensated image data.

The invention discloses a low-power-consumption radiation-resistant quadrature voltage-controlled oscillator based on an SOI (Silicon On Insulator) process, relates to the technical field of quadrature voltage-controlled oscillators, and is used for solving the technical problems that an existing quadrature voltage-controlled oscillator is low in radiation resistance in a harsh radiation environment and does not have the characteristic of low power consumption. The invention discloses a low-power-consumption anti-radiation quadrature voltage-controlled oscillator based on an SOI process. The low-power-consumption anti-radiation quadrature voltage-controlled oscillator comprises a first voltage-controlled oscillator, a second voltage-controlled oscillator, a first tail filter and a second tail filter, the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively form an LC resonant cavity with a parasitic capacitor of an inductor and a varactor through the inductor; the first tail filter is connected with the first voltage-controlled oscillator, and the second tail filter is connected with the second voltage-controlled oscillator; two inductors of the first tail filter and the second tail filter are coupled; lC resonant cavities of the first voltage-controlled oscillator and the second voltage-controlled oscillator output oscillation waveforms, and negative impedance is formed through configured transistor pairs, so that the waveforms are output constantly.

The invention discloses a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a wire stacking structure, the wire stacking structure comprises a plurality of wire layers which are arranged at intervals in the vertical direction, each wire layer comprises a first wire part and a second wire part, and the wire layers extend in the first direction; the storage structure is located on one side of the wire stacking structure in the second direction, and the storage structure is electrically connected with the first wire part; the contact plug is located on the other side of the wire stacking structure in the second direction, and the contact plug is electrically connected with the first wire part; and the shielding structure is at least clamped between the adjacent second wire parts in the vertical direction. The semiconductor structure can reduce parasitic capacitance in the semiconductor structure.

The invention provides a voltage loading device and motor bearing electrocorrosion test equipment, and the voltage loading device comprises a voltage loading circuit, a bearing, a rotating shaft, and a carbon brush. The bearing is mounted on the rotating shaft; the carbon brush is connected with the rotating shaft; the voltage loading circuit comprises an AC / DC power supply, a first capacitor, a second capacitor and a third capacitor, the first capacitor, the second capacitor and the third capacitor form a capacitor branch, the capacitor branch is electrically connected with the AC / DC power supply and the outer ring of the bearing, the first capacitor is used for simulating parasitic capacitance between the motor winding and the stator core, and the second capacitor is used for simulating parasitic capacitance between the motor winding and the stator core. The second capacitor is used for simulating parasitic capacitance between the motor winding and the rotor core, and the third capacitor is used for simulating capacitance between the stator core and the rotor core. The actual working circuit of motor bearing electrocorrosion can be simulated, so that the voltage and the discharge current of the bearing can be accurately simulated, and the accuracy of the motor bearing electrocorrosion test can be conveniently improved.

The invention discloses an excitation inductance design method for guaranteeing soft switching of a CLLC resonant converter, and the method comprises the steps: carrying out the qualitative analysis of a dead-zone equivalent circuit of the CLLC resonant converter, and carrying out the Laplace coordinate transformation. And according to the constant frequency analysis principle of the CLLC resonant converter, obtaining the electric quantity values of the capacitor and the inductor at the dead zone moment. And obtaining a resonance current time domain expression in a dead zone period by adopting a mesh current method. And calculating the period of the resonance current according to the parasitic capacitance values of the primary and secondary side switching tubes. And calculating the discharge time of the parasitic capacitor by considering the electric quantity of the capacitor. And calculating the excitation inductance value required when the resonance current just drops to zero when the dead time is ended. Soft switching of the resonant converter can be effectively guaranteed, the amplitude of the resonant current is reduced, the efficiency of the resonant converter is improved, and the universality is high.

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming an injection layer on the substrate; forming a buffer layer and a drift layer on the injection layer, and performing laser annealing on the buffer layer and the drift layer from one side away from the substrate; a plurality of conductive channel units arranged at intervals are formed on the upper surface layer of the drift layer, laser annealing is conducted on the conductive channel units from the side away from the substrate, and each conductive channel unit comprises a well region, an emitter region and a contact region, forming a gate structure above the well region; removing the substrate to expose the injection layer; laser annealing is carried out on the injection layer from the side, away from the buffer layer, of the injection layer, and laser wavelengths used in laser annealing of the buffer layer, the drift layer, the conductive channel unit and the injection layer are selected based on light absorption characteristic parameters of the injection layer, the buffer layer and the drift layer. According to the semiconductor structure and the preparation method thereof, the formation of parasitic capacitance is reduced, and the device performance is improved.

A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The inverted gate cut region may increase a propensity of a frontside gate contact to meld with the gate structure. The increased landing area further enables the frontside contact to be placed in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.

An optical receiver includes a light receiving element, a capacitor, a transimpedance amplifier, and a base. The light receiving element includes a semiconductor layer, a first conductive film electrically connected to a cathode electrode, a second conductive film electrically connected to the first conductive film through a conductor, and an anode pattern electrically connected to an anode electrode. The transimpedance amplifier has a first pad electrically connected to the first conductive film through a first wire and a second pad electrically connected to the anode pattern through a second wire. The base has a main surface. An electrostatic capacitance between the second conductive film and the main surface of the base is larger than a parasitic capacitance between the first conductive film and the second conductive film, and the inductance of the conductor is smaller than the inductance of the first wire.

The invention discloses a voltage-controlled oscillator with small-area and wide-band modulation capability, and particularly relates to the technical field of radio frequency integrated circuits. The voltage-controlled oscillator comprises two symmetrical voltage-controlled oscillation units; wherein each voltage-controlled oscillation unit comprises a resonance circuit; the resonance circuit comprises an LC resonance circuit and a negative resistance active circuit; the LC resonant circuit comprises a switched capacitor array; two ports of the LC resonance circuit are respectively connected to the output ends of the cross coupling MOS pair; the switched capacitor array is used for providing at least two gears of variable capacitance; the negative resistance active circuit comprises a cross coupling pair transistor and a bias current source; the mode change-over switch circuit comprises two groups of symmetrical switch MOS (Metal Oxide Semiconductor) tubes and mutual inductance transformer taps; and in each voltage-controlled oscillation unit, a tap of the resonant inductor is connected with a corresponding port of the mode switching switch MOS tube. According to the scheme, the mismatch effect caused by a small process and the stray capacitance caused by layout and wiring can be reduced as much as possible, and the chip area can be reduced while the performance is ensured, so that the tape-out cost is reduced.

The invention provides a preparation method of an inductor and the inductor, and the preparation method comprises the following steps: (1) mixing a magnetic powder raw material with a glue solution, sequentially carrying out granulation and pressing to obtain a magnetic core, and carrying out primary curing on the magnetic core; (2) winding a conductor coil, soaking the conductor coil into an insulating liquid for insulating treatment to form an insulating layer, and then filling the conductor coil into the magnetic core; and (3) magnetic slurry is injected into the magnetic core in the step (2), secondary curing is carried out, and an inductor blank is obtained. The coil can be prevented from being deformed, and the parasitic capacitance of the inductor is greatly reduced through insulation protection treatment.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source / drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source / drain opening, and forming a source / drain feature in the source / drain opening and over the isolation layer, wherein the source / drain feature is spaced apart from the isolation layer by an air gap.

The invention belongs to the field of high-speed analog integrated circuit design, and provides a high-speed differential signal driving circuit and an implementation method thereof, and the high-speed differential signal driving circuit comprises an input part, an LVPECL part, a CML part and an output part. The input part comprises an adjustable current source, a first NMOS (N-channel Metal Oxide Semiconductor) tube and a second NMOS tube; the LVPECL part comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, a seventh NMOS transistor, the CML part comprises a ninth NMOS (N-channel Metal Oxide Semiconductor) tube, a tenth NMOS tube, a third PMOS (P-channel Metal Oxide Semiconductor) tube, a fourth PMOS tube, a third resistor and a fourth resistor; and the output part comprises a P output end and an N output end. By designing the simplified LVPECL part and the CML part, the circuit scale and the parasitic capacitance are reduced, and the power consumption and the chip area are reduced; the input part is shared by the LVPECL part and the CML part, so that a common pre-driver is omitted.

The invention discloses a method for extracting parameters of an equivalent circuit model of a GaN HEMT device. The method at least comprises the following steps of S1, modeling the GaN HEMT device into a small-signal equivalent circuit model; s2, extracting external parasitic parameters based on the model in the step S1; s3, internal intrinsic parameters are extracted; in the step S1, the equivalent circuit model comprises external parasitic parameters and internal intrinsic parameters, and the external parasitic parameters are not affected by applied bias voltage and comprise parasitic capacitances Cpg, Cpd and Cpg between metal electrodes, external parasitic inductances Lg, Ld and Ls and external parasitic resistances Rg, Rd and Rs; internal intrinsic parameters are influenced by a channel structure and a bias condition when the device works, and comprise a channel resistor Rgs, a gate-drain resistor Rgd and a drain-source output conductor Gds; capacitors Cgs, Cgd and Cds are arranged among the ports; the transconductance is gm, and the time delay parameter is tau.

The invention provides an image sensor. The image sensor comprises a substrate; the transmission gate is located on the substrate, and the floating diffusion region is located in the substrate on one side of the transmission gate; the source following grid electrode is located on the substrate, and the source following source region and the source following drain region are located in the substrate on the two sides of the source following grid electrode respectively; the MOM capacitor is located on the side, away from the substrate, of the transmission grid electrode and the source following grid electrode, and the floating diffusion region and the source following source region are electrically connected through the MOM capacitor. According to the invention, the MOM capacitor is connected between the floating diffusion region and the source following source region, so that the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the signal-to-noise ratio of the device can be improved, thereby improving the reading noise reduction capability of the image sensor.

The invention discloses a driving method, a display device, display equipment and a computer readable storage medium, and the method comprises the steps: determining an xth data line and an (x + 1) th data line in a driving chip, obtaining a first voltage of a first sub-pixel of a current updating line of an xth column of sub-pixels corresponding to the xth data line, determining an influence factor of each sub-pixel on the (x + 1)-th data line according to the voltage difference of the display gray scale of each sub-pixel on the (x + 1)-th data line, and determining a first correlation quantity according to the influence factor of the sub-pixel on the (x + 1)-th row before the first sub-pixel, determining a second correlation quantity according to the influence factor of the sub-pixel on the (x + 1) th row after the first sub-pixel, obtaining a compensation value based on the first preset value, the first correlation quantity and the second correlation quantity, obtaining a second voltage according to the compensation value and the first voltage value, and transmitting the second voltage to the first sub-pixel, the voltage interference of the first sub-pixel caused by a parasitic capacitance coupling effect is reduced, and abnormal display on a display screen is eliminated.

An electronic key may include a partial capacitor comprising a capacitive metal plate in communication with a processor. The capacitive metal plate of the partial capacitor is configured to form a capacitor with a corresponding capacitive metal plate of a lock when brought into proximity with the metal plate of the lock. Data may be transferred from the key to the lock using a capacitor formed by combining the two metal plates, wherein a common ground is established between the metal plate of the key and the metal plate of the lock through a parasitic capacitance present between the key and lock circuitry. Audit trail data may be recorded based on usage of the key.