871 results about "Parasitic capacitor" patented technology

An organic light emitting display includes a display panel including a plurality of pixels, each of the plurality of pixels including an organic light emitting diode (OLED) and a driving thin film transistor (TFT) to control an emission amount of the OLED, the plurality of pixels connected to respective sensing lines; and at least one sensing unit connected to a corresponding one of the pixels through the respective sensing line, the at least one sensing unit configured to sense an amount of carriers accumulated in a parasitic capacitor of the OLED of the corresponding one of the pixels when a driving current flows in the OLED, the at least one sensing unit thereby sensing a degradation of the OLED.

Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.

A system for communicating across conventional HVAC wiring is provided. The system includes a communication device having a communication module capable of inducing low power, high frequency current signals into a single control wire coupling, for example, a thermostat with a compressor. The communication module includes a power supply module that draws power sufficient to operate the communication module from the existing HVAC wiring, so as to eliminate any need for batteries or external power sources. A second communication module may be coupled to the single control wire. The second communication module operates as a transceiver sending communication signals to, and receiving communication signals from, the communication module. In one embodiment, the communication module is disposed within a building, for example coupled to an electronic thermostat, while the second communication module is disposed outside the building near the compressor. The communication signals are RF modulated signals between 5 and 50 MHz so as to take advantage of and pass across parasitic capacitances found inherent in transformers or other coils disposed within HVAC loads.

A liquid crystal display panel capable of reducing a capacitance of a parasitic capacitor between a data line and a pixel electrode. The liquid crystal display panel comprises: a thin film transistor at a crossing of a gate line and a data line, liquid crystal cells including a pixel electrode connected to the thin film transistor; first shield patterns in the liquid crystal cells, each shield pattern being parallel to the data line without overlapping the data line, wherein the shield patterns are insulated from and overlap with an outer portion of the pixel electrode; and a common line arrayed to connect the shield patterns for each the liquid crystal cell.

Apparatus for cancelling electromagnetic interference (EMI) during power conversion. In one embodiment, the apparatus comprises a power converter for converting a DC input to a DC output, wherein the power converter comprises a transformer having a primary winding and a secondary winding, the secondary winding coupled to a diode such that a plurality of secondary winding voltages cause a balanced current flow through a plurality of parasitic capacitances.

Disclosed is an organic light emitting display which has a scan driver to supply scan signals to a plurality of scan lines, a data driver to supply data signal to output lines, with a demultiplexer on each output line to supply the data signal to a plurality of data lines is disclosed. The display also has a pixel portion comprising pixels connected to the scan lines, the data lines, and pixel power source lines. There is also a power source line placed between the pixel portion and the data driver to supply first power to the pixel power source lines, and a parasitic capacitor formed on each data line to charge voltage corresponding to the data signal. With this configuration, the number of output lines provided in a data driver is decreased, and an image is displayed with uniform brightness.

A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase. The second terminal of the first flying capacitor is coupled to a discharge control circuit which increases the voltage of the second terminal of the first flying capacitor during the first discharging phase until the output voltage is equal to a regulated value.

In a display, capacitors are charged with first precharge voltages at the time of applying selection signals to previous scan lines. A data driver divides a plurality of data lines into a plurality of groups each of which consists of at least one data line and applies corresponding data voltages to the data lines of respective groups sequentially. The display further includes a precharge means, and such precharge means applies second precharge voltages to data lines of at least one group before selection signals for selecting scan line are applied to the scan line connected to the pixel circuits and stops application of the second precharge voltages before corresponding data voltages are applied to the respective groups. In this way, it is possible to solve the problem of poor images due to charge redistribution of the capacitors caused by previous data voltages stored in parasitic capacitors.

Fabrication methods for capacitive micromachined ultrasonic transducers (CMUTS) with independent and precise gap and post thickness control are provided. The fabrication methods are based on local oxidation or local oxidation of silicon (LOCOS) to grow oxide posts. The process steps enable low surface roughness to be maintained to allow for direct wafer bonding of the membrane. In addition, methods for fabricating a step in a substrate are provided with reduced or minimal over-etch time by utilizing the nonlinearity of oxide growth. The fabrication methods of the present invention produce CMUTs with unmatched uniformity, low parasitic capacitance, and high breakdown voltage.

A method is provided for driving a liquid crystal display having a multi-channel single-amplifier structure, where the number of times of coupling according to video signals transmitted to adjacent source lines while the source lines are floated is 3 and it is equal for the respective source lines for 6 frames, noise aspects of the respective source lines are similarly repeated for every 6 frames, kick-back noise compensation is uniformly applied to the source lines S_r, S_g and S_b with noise of the 6 frames averaged, and charge sharing time of parasitic capacitors between the source lines and charge sharing time of capacitors of liquid crystal cells become similar to each other.

With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can be diced without damaging a relatively fragile low-k layer.

A pixel includes a first subpixel and a second subpixel. The first subpixel includes a first switching element connected to a first gate line and a data line, a first liquid crystal capacitor connected to the first switching element, and a first storage capacitor connected to the first switching element. The second subpixel includes a second switching element connected to a second gate line and the data line, a second liquid crystal capacitor connected to the second switching element, and a second storage capacitor connected to the second switching element. At least one of a ratio of capacitances between a first parasitic capacitor formed in the first switching element and a second parasitic capacitor formed in the second switching element and a ratio of capacitances between the first storage capacitor and a second storage capacitor is determined based on a ratio of the first liquid crystal capacitor and the second liquid crystal capacitor.

A capacitance type microphone with a stress release membrane prepared at a low temperature and a preparation method thereof. The capacitance type microphone includes a substrate having at least a resonant cavity; a septum, arranged on the top of the resonant cavity and connected with the substrate for implementing a mechanical vibration when being excitated by an acoustic pressure wave; a back board, arranged on the top of the septum and having a plurality of perforations; an air gap is provided the back board and the septum; a capacitor is composed of the septum, the air gap and the back board. The method includes steps: forming the resonant cavity on the substrate; forming the septum on the top of the resonant cavity, wherein the septum is connected with the substrate; setting the back board on the top of the septum, wherein the back board has a plurality of perforations; forming the air gap between the back board and the septum. The invention is a MEMS capacitance type microphone processed by a completely low-temperature technique. It is capable of being used as a post IC circuit processing technique being compatible thereof. The structure of the vibration diaphragm of the capacitance type microphone is a stress-releasing structure, and is capable of reducing a parasitic capacitance. Comparing with the traditional initial stress release membrane, the invention improves the sensitivity of the microphone more effectively.

In a display, capacitors are charged with first precharge voltages at the time of applying selection signals to previous scan lines. A data driver divides a plurality of data lines into a plurality of groups each of which consists of at least one data line and applies corresponding data voltages to the data lines of respective groups sequentially. The display further includes a precharge means, and such precharge means applies second precharge voltages to data lines of at least one group before selection signals for selecting scan line are applied to the scan line connected to the pixel circuits and stops application of the second precharge voltages before corresponding data voltages are applied to the respective groups. In this way, it is possible to solve the problem of poor images due to charge redistribution of the capacitors caused by previous data voltages stored in parasitic capacitors.

In an electro-optical apparatus, such as a liquid-crystal apparatus, a TFT array substrate is provided with pixel electrodes and TFTs connected thereto. In addition, a peripheral area (including a frame area and a sealing area) is provided with peripheral circuits that drive the pixel electrodes, such as data-line driving circuits and a sampling circuit, and wires that send image signals. On an opposite substrate, an opposite electrode is formed so as to avoid areas opposite the wires. Therefore, with a relatively simple structure, parasitic capacitors generated between the wires on one substrate and the opposite electrode on the other substrate are reduced, and high-quality image display having a reduced ghost is achieved.

The invention belongs to the field of LED (light-emitting diode) drive control, and provides a blanking control circuit for LED (light-emitting diode) display screens and an LED drive chip. According to the invention, by adopting the blanking control circuit (comprising a time-sequence control module and a blanking module) for the LED (light-emitting diode) display screens, in the line scanning process of an LED display screen, the blanking module charges parasitic capacitors in each line of the LED display screen in a time gap generated by scanning every two lines of LEDs so to achieve the purpose of effectively eliminating a smearing phenomenon; meanwhile, a drive circuit module realizes the accurate constant current control on each line of LEDs on the LED display screen, so that the image display quality of the LED display screen is improved, thereby solving the problem that in the prior art, the display quality of the LED display screen is low because the accurate constant current control on LEDs can not be realized.

An organic light emitting display including a demultiplexer on each data line that splits and supplies each data signal to a plurality of data lines, thereby decreasing the number of output lines required and reducing production cost. Further, voltages corresponding to the data signals are sequentially charged in data capacitors, while the charged voltages are supplied to the pixels simultaneously allowing the organic light emitting display to display an image with uniform brightness. Scan periods for supplying the scan signals do not overlap with data periods for supplying the data signals thus yielding a stable image. Also, the capacitance of the data capacitor is set to compensate the voltage drop in the first power source line, thereby displaying an image with uniform brightness.

In a conventional liquid crystal display panel using a metallic film as a light shielding mask of a color filter, there arose a problem in that a parasitic capacitor with the other wiring is generated to often cause a delay in signal. Further, there arose a problem in that, if an organic film containing a black pigment is used as the light shielding film of the color filter, the manufacturing step thereof increases. In the present invention, lamination films of colored layers consisting of two layers (lamination film of a red-colored layer and a blue-colored layer, or lamination film of a red-colored layer and a green-colored layer) are formed on an opposing substrate as light shielding portions so as to overlap with TFTs on a device substrate without forming a light-shielding mask (black matrix).

Disclosed is an organic light emitting display which has a scan driver to supply scan signals to a plurality of scan lines, a data driver to supply data signal to output lines, with a demultiplexer on each output line to supply the data signal to a plurality of data lines is disclosed. The display also has a pixel portion comprising pixels connected to the scan lines, the data lines, and pixel power source lines. There is also a power source line placed between the pixel portion and the data driver to supply first power to the pixel power source lines, and a parasitic capacitor formed on each data line to charge voltage corresponding to the data signal. With this configuration, the number of output lines provided in a data driver is decreased, and an image is displayed with uniform brightness.

A TFT-LCD array substrate and a method for manufacturing the same. The TFT-LCD array substrate includes a substrate, on which at least one gate line and at least one data line are formed and cross with each other to define sub-pixel regions, one of the sub-pixel regions includes a thin film transistor (TFT) and a pixel electrode, and the TFT is electrically connected to the pixel electrode. The TFT-LCD array substrate further includes a compensating parasitic capacitor structure comprising a first electrode electrically connected to the gate line and a second electrode electrically connected to the pixel electrode.

A liquid crystal display panel capable of improving a picture quality and reducing power dissipation includes a plurality of liquid crystal cells each having a thin film transistor formed at a crossing of gate lines and date lines, and a pixel electrode connected to the thin film transistor; a first parasitic capacitor formed between a data line and an adjacent preceding or succeeding pixel first electrode; a second parasitic capacitor formed between the data line and an preceding or succeeding pixel second electrode; and a groove formed at a portion of the pixel electrode adjacent the data line and opposing a portion coupled to the thin film transistor.

The invention provides a 3D NAND storage device and a manufacturing method thereof. After a stacked layer is formed, a sacrificial layer in the stacked layer is replaced with a gate layer by a gate line slit, secondly, a dielectric material is filled in the gate line slit, and an array co-source doped region is extracted from a back side of a substrate. The dielectric material is filled in the gate line slit, common source contact is formed on the back side of the substrate, a parasitic capacitor between the gate line slit and a word line is eliminated, breakdown between the word line and the common source contact is avoided, and device performance is improved.

The invention provides an electric field fingerprint recognition device, a state control method thereof and a prosthesis identification method. The electric field fingerprint recognition device comprises a signal acquisition module and a signal processing module. When a measurement state signal processing unit is electrically connected with a signal acquisition unit, a to-be-measured state signal processing unit is at least electrically connected with at least one signal collection unit at the periphery of the measurement state signal processing unit. The charging and discharging processes of a sensing capacitor which is electrically connected to the measurement state signal processing unit and the to-be-measured state signal processing unit, and the charging and discharging quantity of electricity of a parasitic capacitor between the measurement state signal processing unit and the to-be-measured state signal processing unit is inhibited. The device and the methods have the advantages of simple structure and saving of device cost, a problem of mutual interference between signal collection units is avoided, the fingerprint recognition device can be suitable for various application requirements, a prosthesis finger fingerprint can be judged, and the safety and the reliability of the fingerprint identification device are improved.

The invention relates to a cavity-type film bulk acoustic resonator (FBAR), consisting of a silicon on insulator (SOI) substrate with a cavity and a piezoelectric thin film transducer arranged on the substrate. The FBAR is characterized in that the surface of the substratum silicon slice in the SOI substrate with the cavity is provided with a groove, substratum silicon slice and top-layer silicon are bonded to form a closed cavity structure; the upper of the top-layer silicon is provided with a transducer which is composed of a piezoelectric thin film and thin electrodes plated on the upper surface and the lower surface of the piezoelectric thin film; and a resonator can be tuned, and the thickness of the top-layer silicon can be regulated through controlling the etching time of the top-layer silicon on the upper of the cavity, thus the resonant frequency of the resonator can be regulated. As the preset cavity structure is used, in the invention, no sacrificial layer is needed, thus the chemical mechanical polishing process and the sacrificial layer release process in aboard patents and products, which are used for treating the sacrificial layer are not required; and meanwhile, in the invention, the advantages of small source parasitic capacitance, small drain parasitic capacitance, low voltage, low power consumption and the like of an SOI material are integrated, therefore, the FBAR can be compatible with an integrated circuit (IC), is easy to integrate, has simple process and is applicable to mass production.

An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.

The invention discloses a drive circuit for a P type power MOS switch tube. A push-pull drive circuit and a floating voltage division circuit are connected between a source electrode and a grid electrode of the P type power MOS switch tube. The push-pull drive circuit rapidly controls the charging and discharging of a parasitic capacitor inside the P type power MOS tube by transient current generated when triodes Q1 and Q2 are in alternates; and the floating voltage division circuit provides a stable voltage value of a negative pulse grid source for the P type power MOS tube, thereby improving the dynamic property of the P type power MOS tube and reducing the switch loss of the P type power MOS tube as well as having the advantages of stability, reliability, flexible control and low energy consumption, and the like.

Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.