937 results about "Common line" patented technology

The present invention provides a gaming machine that includes multiple display devices arranged in a common line of sight. An intermediate display device or light filter may be included between the exterior display device and the interior display device. A touchscreen may also be added outside the exterior display device to facilitate player input and gaming machine interaction. The common line of sight arrangement permits a person to view video output on all the display devices simultaneously or without substantially changing their position or line of sight. The interior display device may include a digital display device that includes a curved surface.

Apparatuses, methods, systems and computer-readable media for using proximity inputs on or near a touch screen lens to select objects within a field of view are presented. In some embodiments, a viewing apparatus (e.g. head mounted display, augmented reality goggles) may include at least one lens, wherein the lens can sense touches or near-touches and output data indicative of a location of the proximity input by the user. A processor may receive the data and may select an object within the field of view of the user corresponding to the data, wherein the object and the location of the proximity input on or near the lens by the user are on a common line of sight. In some embodiments, the viewing apparatus may include at least one camera that is configured to record at least one image representative of the user's field of view.

A flow management system capable of providing adjustable hydraulic fluid flow or pressure at a common line to supply bidirectional pumps in electro-hydrostatic actuation systems and conditioning re-circulated hydraulic fluid. The system enables flow sharing between multiple actuation systems and minimization of energy consumption by a power-on-demand approach and / or electrical energy regeneration while eliminating the need for an accumulator. The system has particular application to electro-hydrostatic actuation systems that typically include bi-directional electric motor driven pumps and unbalanced hydraulic actuators connected within closed circuits to provide work output against external loads and reversely recover energy from externally applied loads.

Both a connection server and a relay connection server are installed in an IP transfer network; a function similar to a line connection control of a subscriber exchanger is applied to a connection server; a function similar to a line connection control of a relay exchanger is applied to the relay connection server; and a terminal-to-terminal communication connection control method with using the IP transfer network is realized in such a manner that a telephone set and a terminal such as an IP terminal and a video terminal transmit / receive an initial address message, an address completion message, a call pass message, a response message, a release message and a release completion message, which can be made in a 1-to-1 correspondence relationship with line connection control messages of the common line signal system. Furthermore, while an address administration table is set to a network node apparatus of an IP transfer network, means for registering addresses of the terminals into this address administration table is employed, so that an IP packet communication by a multicast manner can be realized with improving information security performance.

The present invention provides a gaming machine that includes multiple display devices arranged in a common line of sight. An intermediate display device or light filter may be included between the exterior display device and the interior display device. A touchscreen may also be added outside the exterior display device to facilitate player input and gaming machine interaction. The common line of sight arrangement permits a person to view video output on all the display devices simultaneously or without substantially changing their position or line of sight. The interior display device may include a digital display device that includes a curved surface.

A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.

The present invention provides a gaming machine that includes multiple display devices arranged in a common line of sight. An intermediate display device or light filter may be included between the exterior display device and the interior display device. A touchscreen may also be added outside the exterior display device to facilitate player input and gaming machine interaction. The common line of sight arrangement permits a person to view video output on all the display devices simultaneously or without substantially changing their position or line of sight. The interior display device may include a digital display device that includes a curved surface.

Described herein is an electroluminescence display apparatus comprising: at least one quad-type pixel circuit unit comprising a plurality of sub-pixel circuit units; at least one gate line disposed between the plurality of sub-pixel circuit units and extending along a first direction; at least one first data line group comprising a first pair of data lines disposed at both sides of the at least one pixel circuit unit and extending along a second direction; at least one second data line group comprising a second pair of data lines disposed between the sub-pixel circuit units and extending along the second direction; and at least one common line and at least one anode line disposed between the first pair of data lines of the first data line group and disposed along the first direction, the at least one gate line crosses with the at least one first data line group and the at least one second data line group.

An array substrate for a liquid crystal display device includes gate and data lines crossing on a substrate, common lines parallel to and between the gate lines, thin film transistors at crossing portions of the gate and data lines, and a pixel electrode. The common lines define pixel regions, which are each divided into first and second regions by the corresponding gate line. The thin film transistors each include a gate electrode in a first direction, a semiconductor layer on the gate electrode, and source and drain electrodes on the semiconductor layer in a second direction. The source and drain electrodes cross the gate electrode in each of the first and second regions. The pixel electrode is connected to the drain electrode.

A nasal dilator comprises a laminate of vertically stacked layers forming a unitary, or single body, truss where each layer includes at least one member. The truss features horizontal regions adapted to engage outer wall tissues of first and second nasal passages and to traverse the bridge of a nose therebetween. When in use the dilator acts to stabilize and / or expand the nasal outer wall tissues and prevent said tissues from drawing inward during breathing. Manufacturing methods produce dilator layers and / or finished nasal dilator devices efficiently at the same or lower cost as traditional methods by fabricating dilator elements in whole or part along common lines or edges. Said common lines define peripheral dimensions and form spaced apart relationships between dilator layers, members and finished dilator devices without sacrificing usable material to do so. Manufacturing steps include cutting through a fabrication laminate along lines defining at least portions of one or more layers, members, and the truss's peripheral edges. Manufacturing methods further maximize material usage by incorporating waste material into a subsequent fabrication process. Dilator embodiments further include means for providing disparate dilating force to opposing nasal passages, and means for incorporating promotional printing into the dilator fabrication process.

An LCD includes a first gate line and a second gate line disposed parallel to each other and perpendicular to a first data line and a second data line, thereby defining a unit pixel region, a first common line disposed parallel to the gate lines, a second common line extending from the first common line, a pixel bar and pixel electrodes disposed in the unit pixel region and electrically connected to a first TFT, a second TFT electrically connected to the second common line, a common bar and common electrodes electrically connected to the second TFT, the common electrodes being disposed alternately with the pixel electrodes.

An IPS mode LCD device is disclosed in which a common voltage drop and delay is decreased. The LCD includes gate and data lines crossing each other to define pixel regions. Thin film transistors are formed at crossing portions of the gate and data lines. Common lines are parallel with the gate lines and common electrodes project from the common lines parallel with the data lines. Pixel electrodes connected with drain electrodes of the thin film transistors are formed in the pixel regions between the parallel common electrodes. A first common voltage supplying line applies a first common voltage or a second common voltage to a closed circuit formed by grouping the adjacent odd numbered common lines. A second common voltage supplying line applies the second common voltage or the first common voltage to a closed circuit formed by grouping the adjacent even numbered common lines.

Sipes extending from one end of a block to the central area of the block and sipes extending from the other end of the block to the central area of the block (sipes 24, 28, 32 and 36) are inclined in directions opposite to each other. The sipes extending from one end of the block and the sipes extending from the other end of the block intersect a common line extending along the circumferential direction of the tire. Due to this structure, the number of portions of the sipes, which portions are located in the central area of the block, is made greater than that in the peripheral area of the block. The density of sipes is thus increased in the central area of a block where water tends to form when driving on ice, for improving braking and traction properties on ice.

The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased.

A thin film transistor array substrate includes a substrate, a gate line and a data line arranged to cross each other and to define a pixel region on the substrate, a first common line disposed to be parallel to the gate line and to cross the data line, a switch element disposed at an intersection of the gate line and data line, a first pixel electrode formed to overlap the first common line, and a second pixel electrode branched from the first pixel electrode in a plurality of strips, a second common line opposite to the first common line in the center of the pixel region, a second common electrode branched from the second common line toward the pixel region into a plurality of strips, and a third common electrode branched to overlap the data line from the second common line, and a first storage electrode branched from the first common line into the pixel region, and a second storage electrode extended to overlap the first storage electrode from the first pixel electrode.

Vertical-color-filter pixel sensors having simplified wiring and reduced transistor counts are disclosed. In an embodiment, a single line is used for reference voltage, pixel reset voltage, and column-output signals in a VCF pixel sensor. In another embodiment, row-reset signals and row-enable signals are sent across a line that is shared between adjacent rows in an array of VCF pixel sensors. The present invention also provides an optimized layout for a VCF pixel sensor with shared row-reset, row-enable, reference voltage and column-output lines as well as a VCF pixel sensor in which source-follower voltage, source-follower amplifier voltage and row-enable signals all share a common line. These combined line embodiments can be used with a single column-output line as well as two row-enable lines. The embodiments can also be implemented in a VCF pixel sensor without a row-enable transistor.

First and second current drivers are connected to one end of corresponding first and second write bit lines, respectively, and the first and second write bit lines are directly connected, at the other end, to a common line. The first and second current drivers receive a first power supply voltage and the ground voltage, while the common line receives a second power supply voltage higher than the ground voltage and lower than the first power supply voltage. The first and second current drivers cause a current for data writing to flow in a first direction based on a voltage difference between the first power supply voltage and the second power supply voltage, and cause a current for data writing to flow in a second direction based on a voltage difference between the second power supply voltage and the ground voltage.

An in-plane switching mode liquid crystal display device includes a first substrate; a gate line disposed in a first direction on the first substrate; a data line disposed in a second direction on the first substrate, the data line crossing the gate line to define a pixel region; pixel electrodes and common electrodes disposed in the first direction in the pixel region, the pixel electrodes and the common electrodes generating an in-plane electric field within the pixel region; first and second common lines disposed parallel to the data line at right and left sides of the pixel region; a first common electrode connection line connecting at least two common electrodes and forming a first common electrode overlapping region by overlapping the first common line; and a second common electrode connection line connecting at least two other common electrodes and forming a second common electrode overlapping region by overlapping the second common line, wherein the first common electrode overlapping region and the second common electrode overlapping region have substantially the same area.

A circuit and method for improving EMI noise performance in a bridgeless PFC boost converter. Such a converter comprises a boost inductor having a first end connected to a first AC input terminal and a second end connected to a first junction defined between the anode of a first diode and a first terminal of a first switch; a second terminal of the first switch connected to a common line; a parallel circuit of a capacitance and a load connected between the cathode of the first diode and the common line; a series circuit of a second diode and a second switch connected between the cathode of the first diode and the common line; and a second AC input terminal connected to a second junction defined between the anode of the second diode and the second switch. High-frequency EMI noise is bypassed by placing a first filter capacitor between the first AC terminal and the common line. A second boost inductor may be connected between the second AC input terminal and the second junction, and a second filter capacitor may be connected between the second AC terminal and the common line. The first and / or second filter capacitor has a lower impedance in a high frequency range than the corresponding first or second boost inductor. Preferably the first and second capacitors have substantially the same capacitance.

A variable cam timing phaser for an internal combustion engine including a piloted valve in the rotor assembly, movable from a first position to a second position, and detent lines communicating with the advance chamber or the retard chamber are restricted and or blocked when the rotor assembly is in or near an intermediate phase angle position. When the piloted valve is in the first position, fluid is blocked from flowing through the piloted valve. When the piloted valve is in a second position, fluid is allowed to flow between the detent line from the advance chamber and the detent line from the retard chamber through the piloted valve and a common line, such that the rotor assembly is moved to and held in the intermediate phase angle position relative to the housing assembly.

A control system and method for an automatic sprinkler system is disclosed. The automatic sprinkler system includes a first control line and a common line coupled to control a first valve. The control system includes a relay coupled in series with the common line, a sensing circuit coupled to detect the assertion and deassertion of the first valve, and a controller coupled to receive a control data. The controller provides a control signal to enable the relay based on the control data. In operation, the relay is turned on or off based on the control data for controlling the on / off duration of the first value. The relay may be incorporated in the sprinkler system. In one embodiment, the control system learns the programming of the sprinkler system by monitoring the common line to determine the start time, the duration, and the irrigation frequency of the first irrigation zone.

A sink system includes a sink and a storage area receiving and storing matter from the sink. The storage area receives air from the bypass line during a flush. Also, matter from the storage area and sink is vacuumed through a common line during the flush. A valve limits an amount of air supplied by the bypass line such that increased suction is applied to the sink through the common line. The valve may be manually operated or operated by a controller.

The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased.

An in-plane switching mode liquid crystal display device includes: first and second substrates facing and spaced apart from each other; a gate line on the first substrate; a data line crossing the gate line to define a pixel region including a plurality of domains; a thin film transistor connected to the gate line and the data line; a common line parallel to and spaced apart from the gate line; a common electrode extending from the common line and having a ring shape; a pixel electrode connected to the thin film transistor and having a ring shape, the pixel electrode alternating with the common electrode; and a liquid crystal layer between the pixel electrode and the second substrate, the liquid crystal layer in neighboring domains having orientation directions different from each other.

An array substrate for an in-plane switching mode liquid crystal display device and its fabrication method are discussed. According to an embodiment, the array substrate includes a gate line and a data line crossing the gate line on a base substrate, so as to define a pixel region; a thin film transistor connected to the gate line and the data line; a plurality of pixel electrodes disposed in the pixel region and connected to the thin film transistor; a common line extending substantially parallel to the gate line; and a plurality of common electrodes alternately arranged with the plurality of pixel electrodes in the pixel region, wherein the plurality of common electrodes include at least one first common electrode adjacent to the data line and connected to the common line, and at least one second common electrode extending substantially parallel to the date line and not directly connected to the common line.

In a liquid crystal display device of the in-plane switching mode (IPS mode), the potential of data that is output from a data driver is set at values between potentials that are given to common lines. Two levels, i.e., high and low levels, are prepared for the potential to be given to the common lines and the potential is inverted between those levels in every field, whereby the polarity of a voltage between both electrodes of a pixel is inverted. As a result, the potential variation ranges of signals that are output from the data driver and a scan driver can be greatly reduced from those of the conventional case, which contributes to reduction in the power consumption of the drivers. Since the voltage applied to a switching element for controlling each pixel can be reduced, the load of the switching element can also be reduced.

A pixel array including first scan lines, second scan lines, data lines, and sub-pixels is provided. Each sub-pixel includes a first switch, a second switch, a first pixel electrode electrically connected to the first switch, a second pixel electrode electrically connected to the second switch, a third switch, and common lines connected with each other and disposed under the first and the second pixel electrode. The first and the second switch are electrically connected to the same first scan line and data line. The first scan line is located between the first and second pixel electrode. The third switch is electrically connected to the second scan line and the first pixel electrode and has a floating terminal. The floating terminal is capacitively coupled to the second pixel electrode to form a first capacitor and capacitively coupled to the common line under the second pixel electrode to form a second capacitor.

A method for driving an IPS mode LCD device prevents leakage current by swing of a common voltage. The IPS mode LCD device includes multiple gate and data lines crossing each other to define a plurality of pixel regions, multiple thin film transistors (TFT) alternately positioned at lower and upper side pixel regions adjacent to the corresponding gate line, and multiple common lines in a zigzag type along the thin film transistors in the pixel regions. A common voltage is applied so that a first common voltage or a second common voltage is inversely applied to even numbered common lines or odd numbered common lines in one vertical period to be synchronized with a scanning signal supplied to the first gate line, and a gate Low voltage applied to each gate line is lower than a pixel voltage on transition of the common voltage from “High” to “Low”.

A battery management system includes a sensing module, a feeding module, a control module, and a common line adapted for connection to a battery when in use. In some embodiments, a battery management apparatus for managing a substring of cells in a string of cells includes a DC bus, a multiplexer / demultiplexer circuit operative to selectively couple nodes of the substring of cells to the DC bus, a DC / DC converter circuit having a first port configured to be coupled across a plurality of cells of the string and a second port coupled to the DC bus, the DC / DC converter operative to transfer energy between the first and second ports, a sensor circuit coupled to the DC bus, and a controller circuit configured to connect to a communications bus and operatively associated with the multiplexer / demultiplexer circuit, the DC / DC converter and the sensor circuit.

An array substrate for a transflective liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line to define a pixel region having a transmissive portion and a reflective portion; a common line parallel to and spaced apart from the gate line; a thin film transistor connected to the gate and data lines, the thin film transistor including a gate electrode, an active layer, and source and drain electrodes; a capacitor electrode extending from the drain electrode and overlapping the common line; a reflective layer covering the common line and the thin film transistor and corresponding to the reflective portion; and a transparent electrode connected to the drain electrode and disposed in the pixel region.