102 results about "Write bit" patented technology

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

A 3T gain cell includes a write transistor, a storage transistor and a read transistor. The write transistor has a first diffusion connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. The storage transistor has a gate connected to said second diffusion of said write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. The read transistor has a gate connected to a read word line (RWL) a first diffusion connected to said second diffusion of said storage transistor, and a second diffusion connected to a reference voltage.

The application provides a call record processing method and device, equipment and a storage medium, and belongs to the technical field of data processing. The method comprises the following steps: in response to generation of any call record, acquiring the any call record, wherein the any call record comprises a calling number and a call time; reading a target call time bitmap corresponding to the call time, wherein the target call time bitmap corresponds to the call time, and a bit of the target call time bitmap corresponds to time; determining a written bit in the target call time bitmap as a written bit; and determining whether the any call record is a repeated call sheet according to the call time and the written bit. The method solves the problem of a large amount of calculation required for determining a repeated call sheet.

The embodiment of the invention provides a memory and an operation method thereof, relates to the technical field of storage, and realizes a simultaneous read-write function of the memory. According to the specific scheme, the memory comprises a time schedule controller, a memory array, a plurality of writing word lines, a plurality of reading word lines, a plurality of writing bit lines and a plurality of reading bit lines. The storage array comprises a plurality of storage units, the storage units located in the same row are coupled with the same writing word line and the same reading word line, and the storage units located in the same column are coupled with the same writing bit line and the same reading bit line. The time schedule controller is configured to apply a writing line voltage to a writing line corresponding to a first storage unit in the plurality of storage units in any clock period, and the writing line voltage is greater than the word line voltage. The time schedule controller is further configured to apply a read word line voltage to a read word line corresponding to a second storage unit in the plurality of storage units in a clock period, and the first storage unit and the second storage unit are storage units in different rows.

The utility model provides a semiconductor structure. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines including a write bit line and a complementary write bit line positioned at a first interconnect layer disposed over the gate structure; and a read word line positioned at the second interconnect layer and electrically coupled to the gate structure, the second interconnect layer disposed below the gate structure.

The invention provides a memory device and an error correction method thereof. The error correction method of the memory device comprises the following steps: generating a first write bit and a second write bit according to write data, and respectively writing the first write bit and the second write bit into a corresponding first memory cell and a corresponding second memory cell; in a read mode, a page buffer circuit is provided to read a first read bit of a first memory cell and a second read bit of a second memory cell; and causing the page buffer circuit to generate correct read data according to the fixed error mode, the first read bit, and the second read bit of the memory device.

This disclosure provides a method and apparatus for measuring the bit line contact node resistance. The method includes: measuring a first resistance of a DRAM bit line; measuring a second resistance of a first path when a first transistor connected to the bit line is in a conducting state, the first path including: a node contact of the first transistor, a word line channel, a bit line contact node, and a read / write bit line; measuring a third resistance of a second path when two adjacent transistors connected to the bit line are in a conducting state, the second path including: a word line channel and a node contact of the two adjacent transistors; and determining the bit line contact node resistance based on the first, second, and third resistances. This disclosure determines the bit line contact node resistance by performing multiple measurements to determine the first to third resistances respectively. The bit line contact node resistance is equivalent to being obtained from solving multiple equations, eliminating bit line resistance and channel resistance, thus improving the accuracy of the bit line contact node resistance.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

The invention discloses a semiconductor structure, a method for forming the same, and a three-dimensional memory, the semiconductor structure comprising: a substrate having a read word line and a read bit line; a read transistor, the read transistor comprising a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, the read transistor being coupled to the read word line and the read bit line respectively; a write word line and a write bit line; a write transistor, the write transistor being located on the read transistor, the write transistor comprising a second channel layer and a second gate layer, the second channel layer at least partially surrounding the second gate layer from the bottom to the top of the second gate layer, the write transistor being coupled to the write bit line, the write word line, and the first gate layer respectively. According to the semiconductor structure of the embodiment of the present invention, the control capability and integration can be improved, which is conducive to further miniaturization.

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

The capacitor-free memory includes: a substrate; an isolation layer; a read bit line layer; a columnar first stack on an upper surface of the read bit line layer which including a first channel layer, a read word line layer, and a first hard mask layer; a first gate dielectric layer surrounding a side surface and an upper surface of the first stack, and the upper surface of the read bit line layer; a first gate layer covering a surface of the first gate dielectric layer; a columnar second stack on an upper surface of the first gate layer which including a second channel layer, a write bit line layer, and a second hard mask layer; a second gate dielectric layer surrounding a side surface of the second stack, an upper surface of the second stack, and the upper surface of the first gate layer; and a second gate layer.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.

This application provides an SRAM cell and an SRAM memory device. The SRAM cell includes a substrate, and a latch module, a write module, and a read module integrated on the substrate. The latch module includes a pull-up transistor group and a pull-down transistor group, forming a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node. The write module includes a first transmission gate transistor group, which connects a first write word line and a first write bit line pair. The first transmission gate transistor group includes a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first memory node, and the second transmission gate transistor is connected to the second memory node. The read module includes a first read module and a second read module, which are connected to the first memory node and the second read module is connected to the second memory node. This application improves parallel access capabilities.

A memory structure includes: a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a first direction; a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, and a second write-port PG transistor arranged in the first direction; a first read-port PD transistor, a second read-port PD transistor, a first read-port PG transistor, and a second read-port PG transistor arranged in the first direction; a write bit-line conductor extending in the first direction, wherein the write bit-line conductor is under and electrically coupled to a source / drain feature of the first write-port PG transistor; and a write bit-line-bar conductor extending in the first direction, wherein the write bit-line-bar conductor is under and electrically coupled to a source / drain feature of the second write-port PG transistor.

A memory and an access control method therefor, and an electronic device. The memory comprises: at least one storage array layer and a plurality of common bit lines (CBL) having one-to-one correspondence to each storage array layer. Each storage array layer comprises a plurality of read bit lines (BLr) and a plurality of write bit lines (BLw) extending in a first direction parallel to a substrate. The read bit lines (BLr) and the write bit lines (BLw) on the same layer are connected to a corresponding common bit line (CBL). Each write bit line (BLw) is connected to a corresponding common bit line (CBL) by means of a first write gating sub-circuit (11), and each read bit line (BLr) is connected to a corresponding common bit line by means of a first read gating sub-circuit (12). The first write gating sub-circuit (11) is further connected to a first write gating control line, and is configured to connect / disconnect the write bit line to / from the common bit line under the control of the first write gating control line. The first read gating sub-circuit (12) is further connected to a first read gating control line, and is configured to connect / disconnect the read bit line to / from the common bit line under the control of the first read gating control line.

A static random access memory (SRAM) bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors form a first inverter. The third and fourth transistors form a second inverter. The first inverter and the second inverter are cross-coupled. The write driver circuit is coupled to one reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to connection terminals of the first transistor and the third transistor. The second transistor circuit is coupled between the write driver circuit and another reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a word line.

The embodiment of the invention discloses a shared cache device and method of a chip, and the device comprises a data distribution module which is used for receiving data in a data stream sent by a data bus and sending an instruction for outputting an effective pointer to a pointer processing module, and a shared cache write operation module which is used for receiving the effective pointer output by the pointer processing module and sending the effective pointer to the pointer processing module. The data processing module is used for receiving the data sent by the data distribution module, writing the valid data into the RAM based on the bit number of the valid data in the data and the write bit width of a cache memory in the RAM, determining a cache pointer corresponding to the valid data, and sending the cache pointer to the pointer processing module; the pointer processing module is used for reading a pointer from a pointer pool set in a cache module corresponding to the RAM, and is also used for receiving a read request for reading effective data in the RAM, reading the effective data in the RAM according to a cache pointer corresponding to the read request, and inputting the cache pointer after reading the effective data as a pointer to be recycled into the pointer pool for sharing the RAM by a plurality of data streams; the utilization rate of the shared cache space is improved.

The invention provides a memory based on a transistor and a ferroelectric capacitor, a preparation method, a reading method and electronic equipment, relates to the field of memories, and aims to solve the problems that the integration level of a current memory still needs to be improved and the crosstalk is relatively large. Comprising a writing transistor, a reading transistor, a writing word line, a reading bit line, a reading induction line, a plurality of ferroelectric capacitors and a plurality of writing bit lines, the memory comprises a substrate, a first stack structure, a second stack structure, a third stack structure, an active layer, a ferroelectric layer and a conductive layer. The first stack structure comprises a plurality of write bit line layers and a plurality of first dielectric layers; the second stacking structure comprises a second dielectric layer, a reading bit line layer, a third dielectric layer and a grid electrode of the reading transistor which are stacked in sequence; the third stacking structure comprises a fourth dielectric layer, a reading induction line layer, a fifth dielectric layer, a writing word line layer, a sixth dielectric layer and a connecting layer which are stacked. According to the invention, the miniature capability of the array can be improved, and the integration level is further improved.

A dynamic random access memory (DRAM) includes a plurality of main bit cells, a first set of write bit lines, a first set of write word lines, a plurality of canary cells, a second set of write bit lines, and a second set of write word lines. Each main bit cell has a capacitive storage element and is coupled to a corresponding write bit line of the first set of bit lines and a corresponding write word line of the first set of write word lines. The plurality of canary cells are configured to be more susceptible to leakage currents as compared the plurality of main bit cells. Each canary cell has a capacitive storage element and is coupled to a corresponding write bit line of the second set of bit lines and a corresponding write word line of the second set of write word lines.

The application discloses a dual-mode communication chip and belongs to the technical field of communication. The dual-mode communication chip comprises an HPLC signal sending end and an HPLC signal receiving end; the HPLC signal sending end is configured as an encoding module, is used for encoding load data, and obtains encoded load data; a first storage module is used for storing the encoded load data; a channel interleaving module is used for performing interleaving processing on bit data read from the first storage module; a first bit cache queue is used for sequentially writing bit data from the channel interleaving module in a first bit number and sequentially reading out the bit data in a second bit number according to the writing order; and a bit mapping module is used for mapping bit data from the first bit cache queue to each subcarrier in the second bit number. The application realizes efficient matching of the rate of data processing under a high-order modulation mode and data transmission without subcarrier across physical blocks.

A memory cell of a dynamic random access memory, an array, a memory, and a device are provided. The memory cell includes a write word line, a write bit line, a write transistor, a read word line, a read bit line and a read transistor. The read transistor includes multiple channel layers composed of different materials. A gate electrode, a first electrode and a second electrode of the write transistor are connected to the write word line, the write bit line and a gate electrode of the read transistor respectively. The first and second electrodes of the write transistor are respectively source and drain electrodes of the write transistor. First and second electrodes of the read transistor are connected to the read bit line and the read word line respectively. The first and second electrodes of the read transistor are respectively source and drain electrodes of the read transistor.

This invention provides a memory device and a memory array. The memory device includes memory cells. Each memory cell includes a first switching element, a second switching element, and a storage element. The first switching element is used to receive a write bit line signal and is coupled to a storage node. The second switching element is used to receive a read bit line signal and is coupled to the storage node. The storage element is coupled to the storage node and is used to receive a voltage signal and store a first data bit, wherein the memory cell is used to store a second data bit, different from the first data bit, in the storage node.

The invention relates to the technical field of time-to-digital converters, and provides a time-to-digital converter based on a magnetic track memory, comprising: a magnetic track memory array having m rows and n columns of units, each unit representing a magnetic nanowire, all units in each row sharing the same word line, all units in each column share one writing bit line and one reading bit line; an output port of the word line driver is connected with a word line input port of the magnetic track memory array; an output port of the write-in and reset controller is connected with a write bit line input port of the magnetic track memory array; the input port of the SA array is connected with the read bit line output port of the magnetic track memory array; and the storage controller is used for generating a control signal and pulse current. The time-to-digital converter has the functions of time-to-digital signal conversion and nonvolatile storage, can realize high-precision time measurement and reliable storage, and is convenient to construct a large-scale time-to-digital converter array.

The application discloses a kind of asymmetric write dual-voltage magnetic random access memory (MRAM) structure, including magnetic random access array, write drive circuit, readout circuit, write bit line selection circuit, read bit line selection circuit, word line drive circuit and control circuit.The application is designed using two voltage domains transistor, to guarantee that memory can work normally under dual power supply voltage.When writing, control part works in low voltage domain, and write circuit part works in high voltage domain, which can shorten write delay and improve write yield;When reading, readout circuit and control part work in low voltage domain, which can reduce read power consumption and reduce read damage.At the same time, for the asymmetry of MRAM memory cell structure, the application proposes an asymmetric write mode, which effectively reduces the power waste in the writing process.Compared with the traditional MRAM memory, the application effectively improves the write yield and reduces the write delay while considering the area and energy efficiency.

The present application relates to a write word line enable circuit and enable control method, memory, and electronic device. The write word line enable circuit is used to connect to a memory cell, which includes a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor. The write word line enable circuit includes a sensing control circuit connected to the write bit line and configured to: obtain a data signal transmitted by the write bit line and output a write control signal based on the data signal; and a startup control circuit connected to the sensing control circuit and to the write word line and configured to: output an enable signal to the write word line based on the write control signal. Using the write word line enable circuit of the present application can improve the read and write fault tolerance rate.

A computing-in-memory unit and a control method therefor, and an electronic device. The computing-in-memory unit comprises: at least one column of memory cells, each memory cell comprising a read transistor (T1) and a write transistor (T2), wherein a first electrode (E1) of the read transistor (T1) is connected to a summing line (SL), a second electrode (E2) thereof is connected to a reference voltage terminal (Vrefn), and a first gate electrode (G1) thereof is connected to an action line (act); and a third electrode (G3) of the write transistor (T2) is connected to a second gate electrode (G2) of the read transistor, a fourth electrode (E4) thereof is connected to a write bit line (WBL), and a third gate electrode (G3) thereof is connected to a write word line (WWL). First electrodes (E1) of memory cells in the same column are connected to the same summing line (SL); the action line is connected to a data input circuit; and the data input circuit is configured to determine the level of a voltage signal that corresponds to data to be operated, and input the voltage signal of the corresponding level to the action line (act), wherein voltage values of the voltage signal of different levels are different.

The application belongs to the technical field of integrated circuits, and discloses an in-memory logic operation circuit and system based on DRAM. The in-memory logic operation circuit comprises two DRAM units and a sense amplifier for generating a logic operation result. The in-memory logic operation circuit defines a group of logic input signals as the storage content of the DRAM units, defines another group of logic input signals as the readout control signals of the circuit, and defines the double-phase output signals of the sense amplifier as the positive and negative phase output results of the logic operation. On this basis, the in-memory logic operation system provided by the application comprises at least one in-memory logic operation circuit, a write word line, a write bit line, a read word line decoding and driving circuit, a logic configuration circuit, and a control circuit. The application provides an in-memory logic operation circuit scheme while keeping the storage function of the in-memory logic operation circuit from being destroyed, and improves the compatibility of the in-memory logic operation and the memory array.