52 results about "Write bit" patented technology

The application provides a call record processing method and device, equipment and a storage medium, and belongs to the technical field of data processing. The method comprises the following steps: in response to generation of any call record, acquiring the any call record, wherein the any call record comprises a calling number and a call time; reading a target call time bitmap corresponding to the call time, wherein the target call time bitmap corresponds to the call time, and a bit of the target call time bitmap corresponds to time; determining a written bit in the target call time bitmap as a written bit; and determining whether the any call record is a repeated call sheet according to the call time and the written bit. The method solves the problem of a large amount of calculation required for determining a repeated call sheet.

The embodiment of the invention provides a memory and an operation method thereof, relates to the technical field of storage, and realizes a simultaneous read-write function of the memory. According to the specific scheme, the memory comprises a time schedule controller, a memory array, a plurality of writing word lines, a plurality of reading word lines, a plurality of writing bit lines and a plurality of reading bit lines. The storage array comprises a plurality of storage units, the storage units located in the same row are coupled with the same writing word line and the same reading word line, and the storage units located in the same column are coupled with the same writing bit line and the same reading bit line. The time schedule controller is configured to apply a writing line voltage to a writing line corresponding to a first storage unit in the plurality of storage units in any clock period, and the writing line voltage is greater than the word line voltage. The time schedule controller is further configured to apply a read word line voltage to a read word line corresponding to a second storage unit in the plurality of storage units in a clock period, and the first storage unit and the second storage unit are storage units in different rows.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.

This application provides an SRAM cell and an SRAM memory device. The SRAM cell includes a substrate, and a latch module, a write module, and a read module integrated on the substrate. The latch module includes a pull-up transistor group and a pull-down transistor group, forming a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node. The write module includes a first transmission gate transistor group, which connects a first write word line and a first write bit line pair. The first transmission gate transistor group includes a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first memory node, and the second transmission gate transistor is connected to the second memory node. The read module includes a first read module and a second read module, which are connected to the first memory node and the second read module is connected to the second memory node. This application improves parallel access capabilities.

A static random access memory (SRAM) bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors form a first inverter. The third and fourth transistors form a second inverter. The first inverter and the second inverter are cross-coupled. The write driver circuit is coupled to one reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to connection terminals of the first transistor and the third transistor. The second transistor circuit is coupled between the write driver circuit and another reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a word line.

The invention provides a memory based on a transistor and a ferroelectric capacitor, a preparation method, a reading method and electronic equipment, relates to the field of memories, and aims to solve the problems that the integration level of a current memory still needs to be improved and the crosstalk is relatively large. Comprising a writing transistor, a reading transistor, a writing word line, a reading bit line, a reading induction line, a plurality of ferroelectric capacitors and a plurality of writing bit lines, the memory comprises a substrate, a first stack structure, a second stack structure, a third stack structure, an active layer, a ferroelectric layer and a conductive layer. The first stack structure comprises a plurality of write bit line layers and a plurality of first dielectric layers; the second stacking structure comprises a second dielectric layer, a reading bit line layer, a third dielectric layer and a grid electrode of the reading transistor which are stacked in sequence; the third stacking structure comprises a fourth dielectric layer, a reading induction line layer, a fifth dielectric layer, a writing word line layer, a sixth dielectric layer and a connecting layer which are stacked. According to the invention, the miniature capability of the array can be improved, and the integration level is further improved.

The application discloses a dual-mode communication chip and belongs to the technical field of communication. The dual-mode communication chip comprises an HPLC signal sending end and an HPLC signal receiving end; the HPLC signal sending end is configured as an encoding module, is used for encoding load data, and obtains encoded load data; a first storage module is used for storing the encoded load data; a channel interleaving module is used for performing interleaving processing on bit data read from the first storage module; a first bit cache queue is used for sequentially writing bit data from the channel interleaving module in a first bit number and sequentially reading out the bit data in a second bit number according to the writing order; and a bit mapping module is used for mapping bit data from the first bit cache queue to each subcarrier in the second bit number. The application realizes efficient matching of the rate of data processing under a high-order modulation mode and data transmission without subcarrier across physical blocks.

This invention provides a memory device and a memory array. The memory device includes memory cells. Each memory cell includes a first switching element, a second switching element, and a storage element. The first switching element is used to receive a write bit line signal and is coupled to a storage node. The second switching element is used to receive a read bit line signal and is coupled to the storage node. The storage element is coupled to the storage node and is used to receive a voltage signal and store a first data bit, wherein the memory cell is used to store a second data bit, different from the first data bit, in the storage node.

The invention relates to the technical field of time-to-digital converters, and provides a time-to-digital converter based on a magnetic track memory, comprising: a magnetic track memory array having m rows and n columns of units, each unit representing a magnetic nanowire, all units in each row sharing the same word line, all units in each column share one writing bit line and one reading bit line; an output port of the word line driver is connected with a word line input port of the magnetic track memory array; an output port of the write-in and reset controller is connected with a write bit line input port of the magnetic track memory array; the input port of the SA array is connected with the read bit line output port of the magnetic track memory array; and the storage controller is used for generating a control signal and pulse current. The time-to-digital converter has the functions of time-to-digital signal conversion and nonvolatile storage, can realize high-precision time measurement and reliable storage, and is convenient to construct a large-scale time-to-digital converter array.

A computing-in-memory unit and a control method therefor, and an electronic device. The computing-in-memory unit comprises: at least one column of memory cells, each memory cell comprising a read transistor (T1) and a write transistor (T2), wherein a first electrode (E1) of the read transistor (T1) is connected to a summing line (SL), a second electrode (E2) thereof is connected to a reference voltage terminal (Vrefn), and a first gate electrode (G1) thereof is connected to an action line (act); and a third electrode (G3) of the write transistor (T2) is connected to a second gate electrode (G2) of the read transistor, a fourth electrode (E4) thereof is connected to a write bit line (WBL), and a third gate electrode (G3) thereof is connected to a write word line (WWL). First electrodes (E1) of memory cells in the same column are connected to the same summing line (SL); the action line is connected to a data input circuit; and the data input circuit is configured to determine the level of a voltage signal that corresponds to data to be operated, and input the voltage signal of the corresponding level to the action line (act), wherein voltage values of the voltage signal of different levels are different.

A Content-Addressable Memory (CAM) cell has a latch of cross-coupled inverters and transmission gates to bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing. A node in the latch is applied to a gate of a data transistor in series with a select transistor to discharge a match line when select and latch data mismatch. Second data and select transistors receive inverse data from the latch for a CAM but receive data from a second cell latch for a Ternary Content-Addressable Memory (TCAM) cell with two latches per pair of select lines. When mismatches occur, even cells discharge the match line using n-channel data and select transistors while odd cells charge a complement match line using p-channel data and select transistors. The total number of p-channel and n-channel transistors in the cell can be equal when using complementary match lines.

An in-memory computing unit and a control method thereof, and an electronic device, the in-memory computing unit comprising: at least one column of memory cells, the memory cells comprising a read transistor and a write transistor, a first electrode of the read transistor being connected to a summation line, a second electrode being connected to a reference voltage terminal, a first gate electrode being connected to an operation line, and a second gate electrode being connected to an operation line; the third electrode of the write transistor is connected with the second gate electrode of the read transistor, the fourth electrode is connected with a write bit line, the third gate electrode is connected with a write word line, and the first electrodes of the memory cells in the same column are connected with the same summation line; the operation line is connected with the data input circuit; the data input circuit is configured to determine the grade of a voltage signal corresponding to data to be operated and input the voltage signal of the corresponding grade to the operation line, and the voltage values of the voltage signals of different grades are different. According to the scheme provided by the embodiment, the double-gate storage unit is used, different voltage values are loaded to the operation line according to different data, and the summing line can be detected in a voltage and current mode.

This disclosure provides a voltage configuration method for a memory array, applicable to the field of circuit technology. The method includes: configuring the write word line and the write bit line to a first voltage in response to a read operation, such that the write transistor is in a turned-off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selection state of the read word line of the memory array, the selection state indicating whether a memory cell associated with the read word line performs a read operation; and configuring the voltage of the read word line according to the selection state and the second voltage to control the conduction state of the read transistor.

Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.

The invention provides a physical unclonable function generator, a generation method and electronic equipment, relates to the field of electronic devices, and aims to solve the problem that existing physical unclonable function generators have certain limitations. The physical unclonable function generator comprises a write transistor and a read transistor; a control electrode of the writing transistor is electrically connected with a writing word line, a first electrode of the writing transistor is electrically connected with a writing bit line, and a second electrode of the writing transistor is electrically connected with a control electrode of the reading transistor; a first electrode of the reading transistor is electrically connected with a reading word line, and a second electrode of the reading transistor is electrically connected with a reading bit line; and the controller is electrically connected with the write bit lines and the read bit lines of the plurality of gain units, and the controller is used for adjusting the write voltage of each gain unit and determining a key value according to the magnitude relationship between the read current of each gain unit and the reference current. The physical unclonable function generator provided by the invention has extremely high randomness and better entropy source quality.

The application provides an access circuit and a storage unit circuit. The access circuit comprises a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit line. A second end of the second transistor is coupled to a gate end of the first transistor as a storage end point. A gate end of the second transistor is coupled to a write word line. A base end of the first transistor is coupled to the gate end of the first transistor.

A semiconductor memory cell structure and method of fabricating same structure includes one or more bit cells including a stacked read transistor and write transistor, each bit cell further including read bit line(s), read word line(s), write bit line(s), write word line(s), and a storage node isolated from other bit cell structures. The bit cell(s) further include a read word line to storage node voltage coupler structure which is proximately located near the read word line and storage node, and the voltage coupler is configured as a winged gate or a wraparound read word line.

A latch array having mask write functionality includes a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; and a slave latch in the column of the array, wherein the slave latch of the array includes a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

The invention relates to a 12T-SRAM (Static Random Access Memory) storage unit for ultra-low-voltage rapid read-write, and relates to the technical field of memory integrated circuits, the 12T-SRAM storage unit comprises eight NMOS (N-channel Metal Oxide Semiconductor) transistors (N1, N2, N3, N4, N5, N6, N7 and N8) and four PMOS (P-channel Metal Oxide Semiconductor) transistors (P1, P2, P3 and P4); a writing word line WWL controls the transistors N6 and N5; a read-write control signal WL controls PMOS (P-channel Metal Oxide Semiconductor) tubes P4 and P3; an inversion signal WL'is read and written to control NMOS (N-channel Metal Oxide Semiconductor) tubes N4 and N3; a read word line RWL controls transistors N8 and N7; the writing bit line BL and the writing bit line non-BLB are respectively connected with the N5 and the N6; the read bit line RBL and the read bit line non-RBLB are respectively connected with the N7 and the N8; a bit line is directly driven to read by combining a dynamic cut-off feedback device with an internal phase inverter, and complex latch writing is simplified into direct driving of the phase inverter, so that the flip critical voltage is remarkably reduced; under the ultra-low-voltage working condition, the SRAM still has strong write-in capability and higher write-in speed, and the problem of write-in failure of a traditional SRAM under the near-threshold voltage is effectively solved.

A memory cell, a data read-write circuit, a memory, and a memory manufacturing method are provided. The memory cell includes: a horizontal semiconductor layer extending along a first direction, and a write bit line, a write transistor, a read transistor, and a read word line which are located on the horizontal semiconductor layer and sequentially arranged along the first direction. The write bit line and the read word line each extend along a second direction intersecting the first direction. The read transistor extends along a third direction perpendicular to the first direction and the second direction and penetrates through the horizontal semiconductor layer. A source line, the read transistor, and a read bit line are arranged along the third direction. Simultaneous photolithography of multiple layers of stacked memory cells can be supported and meanwhile an area overhead of a single layer of memory cells is reduced.

The invention provides a 6T memory cell of a static random access memory, a related method and a product. The 6T memory cell comprises a write line, a write bit line, a read line, a read bit line, a first P-type tube, a second P-type tube, a first N-type tube, a second N-type tube, a third N-type tube, a fourth N-type tube, a first memory node and a second memory node. Wherein inverters respectively formed by the first P-type tube, the second P-type tube and the first N-type tube adopt asymmetric structures, and the storage unit adopts a read-write separated control mechanism, so that the voltage of a storage node is prevented from being lowered during data reading, and the stability of data storage is improved.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

The semiconductor memory device includes: a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and spaced apart from each other in a first horizontal direction; a capacitor electrode having a first portion and a second portion; a capacitor dielectric layer; a first gate dielectric layer covering a side surface of the first portion; the first channel layer covers the first gate dielectric layer; a second gate dielectric layer covering a portion of a side surface of the write word line; and a second channel layer connected to a second portion of the capacitor electrode and connected to the write bit line, and covering the second gate dielectric layer.

The present disclosure relates to the field of semiconductors, and relates to a semiconductor device and a manufacturing method therefor, and an electronic device, used for reducing the area of a memory cell. The semiconductor device comprises memory cells (30). Each memory cell (30) comprises a write transistor (500) and a read transistor (300). The write transistor (500) comprises a write gate extending in a second direction, and a write gate dielectric layer (510) and a write channel layer (520) successively surrounding the write gate, and the write channel layer (520) is connected to a write bit line. The read transistor (300) and the write transistor (500) are arranged in a first direction. The read transistor (300) comprises a read channel layer (330), a first gate dielectric layer (320), a read floating gate (310), a second gate dielectric layer, and a read control gate. The read channel layer (330) is in an annular configuration, and the axis of the annular configuration extends in the second direction. The first gate dielectric layer (320) and the read floating gate (310) successively surround the outer sidewall of the read channel layer (330). The second gate dielectric layer and the read control gate are successively located on the outer sidewall of the read floating gate (310) in a third direction.

The invention provides a double-transistor dynamic random access memory. The double-transistor dynamic random access memory comprises a writing transistor, a reading transistor, a writing word line, a writing bit line, a reading word line and a reading bit line, wherein the write transistor comprises a source electrode, a grid electrode and a drain electrode, and the read transistor comprises a source electrode, a grid electrode and a drain electrode; a grid electrode of the writing transistor is connected with a writing word line, a drain electrode of the writing transistor is connected with a writing bit line, a drain electrode of the reading transistor is connected with a reading word line, and a source electrode of the reading transistor is connected with a reading bit line; no overlapping area is arranged between the grid electrode of the write transistor and the source electrode of the write transistor. According to the invention, the overlapping area between the grid electrode of the write transistor and the source electrode of the write transistor is eliminated, the capacitance coupling effect of the write transistor is reduced, the leakage current of the grid electrode of the write transistor is reduced, and the retention time of the dynamic random access memory is prolonged.

Disclosed are an access circuit and a memory cell circuit. The access circuit includes a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit-line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit-line. A second end of the second transistor is coupled to a gate terminal of the first transistor to serve as the storage endpoint. A gate terminal of the second transistor is coupled to the write word-line. A base terminal of the first transistor is coupled to the gate terminal of the first transistor.

To provide a semiconductor device with improved operation speed.SOLUTION: The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes first to third transistors having the same conductivity type and a capacitor. Gates of the first to third transistors are electrically connected to a write word line, a first terminal of the capacitor, and a read word line. A second terminal of the capacitor is electrically connected to the read bit line. One of a source and a drain of the first transistor is electrically connected to the write bit line, and the other is electrically connected to a gate of the second transistor. The second transistor and the third transistor are electrically connected in series between the read bit line and the first wiring. Channel formation regions of the first to third transistors each include a metal oxide layer, for example.SELECTED DRAWING: Figure 5