126 results about "Write bit" patented technology

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

A 3T gain cell includes a write transistor, a storage transistor and a read transistor. The write transistor has a first diffusion connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. The storage transistor has a gate connected to said second diffusion of said write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. The read transistor has a gate connected to a read word line (RWL) a first diffusion connected to said second diffusion of said storage transistor, and a second diffusion connected to a reference voltage.

The invention provides a static memory cell and a memory architecture which can improve the storage stability and reduce the area overhead at the same time. The static memory cell includes: a first inverter circuit having an output electrically connected to a first storage node and an input electrically connected to a second storage node; the output end of the second inverter circuit is electrically connected to the second storage node, and the input end of the second inverter circuit is electrically connected to the first storage node; a read operation transistor having a gate electrically connected to the first storage node, a drain electrically connected to a read bit line, and a source electrically connected to a read word line; and a write pass transistor having a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

An eDRAM cell for a CIM according to the present disclosure includes a first transistor which is connected between a read word line and a read bit line and has a gate connected to a storage node; a second transistor which is connected between a write bit line and the storage node and has a gate connected to a write word line; a first capacitor connected between the storage node and a ground; a third transistor which is connected between a local MAC bit line and a fourth transistor and has a gate connected to the storage node; and a fourth transistor which is connected between the third transistor and the ground and has a gate connected to a MAC word line.

A cryogenic quasi-static embedded DRAM (CQS-eDRAM) for energy-efficient computing-in-memory (CIM) is provided. A CQS-eDRAM array includes four-transistor transmission gate gain-cell (4T TGGC) memory cells, and each of the 4T TGGC memory cells includes a P-channel metal oxide semiconductor (PMOS) transistor P1 and three N-channel metal oxide semiconductor (NMOS) transistors N1, N2, and N3. A cryogenic 4T TGGC topology is provided. A quasi-static storage operation is achieved at a cryogenic temperature by fully utilizing advantages of the cryogenic 4T TGGC topology in reducing leakage and a line transmission delay. In addition, a cryogenic write bit line (WBL) bias technology and a dedicated readout circuit are adopted to optimize power consumptions of read and write operations.

The application provides a call record processing method and device, equipment and a storage medium, and belongs to the technical field of data processing. The method comprises the following steps: in response to generation of any call record, acquiring the any call record, wherein the any call record comprises a calling number and a call time; reading a target call time bitmap corresponding to the call time, wherein the target call time bitmap corresponds to the call time, and a bit of the target call time bitmap corresponds to time; determining a written bit in the target call time bitmap as a written bit; and determining whether the any call record is a repeated call sheet according to the call time and the written bit. The method solves the problem of a large amount of calculation required for determining a repeated call sheet.

The embodiment of the invention provides a memory and an operation method thereof, relates to the technical field of storage, and realizes a simultaneous read-write function of the memory. According to the specific scheme, the memory comprises a time schedule controller, a memory array, a plurality of writing word lines, a plurality of reading word lines, a plurality of writing bit lines and a plurality of reading bit lines. The storage array comprises a plurality of storage units, the storage units located in the same row are coupled with the same writing word line and the same reading word line, and the storage units located in the same column are coupled with the same writing bit line and the same reading bit line. The time schedule controller is configured to apply a writing line voltage to a writing line corresponding to a first storage unit in the plurality of storage units in any clock period, and the writing line voltage is greater than the word line voltage. The time schedule controller is further configured to apply a read word line voltage to a read word line corresponding to a second storage unit in the plurality of storage units in a clock period, and the first storage unit and the second storage unit are storage units in different rows.

The invention discloses a storage and calculation integrated hardware accelerator and system based on high-density cache. In the accelerator, a storage unit array comprises a plurality of 2T eDRAM units, and a read word line decoder is used for selecting storage units storing operands to be operated from the storage unit array; the induction amplifier is used for reading an operand to be operated of the storage unit array as a digital signal according to a set reference voltage to obtain a corresponding logical operation result; the shifter is used for performing shifting operation on the logic operation result output by the induction amplifier as required; and the write bit line driving module is used for selecting an operation result from the output end of the induction amplifier or the output end of the shifter and storing the operation result to a corresponding storage unit of the storage unit array through write-back operation. According to the accelerator designed by the invention, an analog-to-digital converter is not needed, relatively high storage density can be achieved, large-scale logic parallel operation can be realized, addition and multiplication can also be realized, and an application scene is expanded.

The utility model provides a semiconductor structure. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines including a write bit line and a complementary write bit line positioned at a first interconnect layer disposed over the gate structure; and a read word line positioned at the second interconnect layer and electrically coupled to the gate structure, the second interconnect layer disposed below the gate structure.

The invention provides a memory device and an error correction method thereof. The error correction method of the memory device comprises the following steps: generating a first write bit and a second write bit according to write data, and respectively writing the first write bit and the second write bit into a corresponding first memory cell and a corresponding second memory cell; in a read mode, a page buffer circuit is provided to read a first read bit of a first memory cell and a second read bit of a second memory cell; and causing the page buffer circuit to generate correct read data according to the fixed error mode, the first read bit, and the second read bit of the memory device.

The utility model discloses a storage circuit of a video switcher, which relates to the technical field of storage circuits, and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube I and an NMOS (N-channel Metal Oxide Semiconductor) tube II, the source electrode of the PMOS tube I is electrically connected with the source electrode of the PMOS tube II, the PMOS tube I is electrically connected with power supply voltage, the grid electrode of the PMOS tube I is electrically connected with the grid electrode of the NMOS tube I, the grid electrode of the PMOS tube I is electrically connected with the drain electrode of the NMOS tube II, and the source electrode of the NMOS tube II is electrically connected with the drain electrode of the NMOS tube II. The grid electrode of the first PMOS tube is electrically connected with the grid electrode of a third NMOS tube. According to the storage circuit of the video switcher, when a write operation is carried out, if a storage point Q is at a high level, a word line WL is pulled to be at a high level, a write bit line WBL is at a low level and charges of the storage point Q are released to be 0 through a sixth NMOS tube and the write bit line WBL during a write low level 0 operation period, so that the write 0 operation is realized; and the connection path of the storage nodes is blocked, the aging influence is reduced, and the reading fault and the semi-selection fault are reduced.

This disclosure provides a method and apparatus for measuring the bit line contact node resistance. The method includes: measuring a first resistance of a DRAM bit line; measuring a second resistance of a first path when a first transistor connected to the bit line is in a conducting state, the first path including: a node contact of the first transistor, a word line channel, a bit line contact node, and a read / write bit line; measuring a third resistance of a second path when two adjacent transistors connected to the bit line are in a conducting state, the second path including: a word line channel and a node contact of the two adjacent transistors; and determining the bit line contact node resistance based on the first, second, and third resistances. This disclosure determines the bit line contact node resistance by performing multiple measurements to determine the first to third resistances respectively. The bit line contact node resistance is equivalent to being obtained from solving multiple equations, eliminating bit line resistance and channel resistance, thus improving the accuracy of the bit line contact node resistance.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

The invention discloses a semiconductor structure, a method for forming the same, and a three-dimensional memory, the semiconductor structure comprising: a substrate having a read word line and a read bit line; a read transistor, the read transistor comprising a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, the read transistor being coupled to the read word line and the read bit line respectively; a write word line and a write bit line; a write transistor, the write transistor being located on the read transistor, the write transistor comprising a second channel layer and a second gate layer, the second channel layer at least partially surrounding the second gate layer from the bottom to the top of the second gate layer, the write transistor being coupled to the write bit line, the write word line, and the first gate layer respectively. According to the semiconductor structure of the embodiment of the present invention, the control capability and integration can be improved, which is conducive to further miniaturization.

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

The capacitor-free memory includes: a substrate; an isolation layer; a read bit line layer; a columnar first stack on an upper surface of the read bit line layer which including a first channel layer, a read word line layer, and a first hard mask layer; a first gate dielectric layer surrounding a side surface and an upper surface of the first stack, and the upper surface of the read bit line layer; a first gate layer covering a surface of the first gate dielectric layer; a columnar second stack on an upper surface of the first gate layer which including a second channel layer, a write bit line layer, and a second hard mask layer; a second gate dielectric layer surrounding a side surface of the second stack, an upper surface of the second stack, and the upper surface of the first gate layer; and a second gate layer.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

The present disclosure provides a memory writing method and writing device. The memory writing method includes: detecting whether a write operation of a first memory cell among a plurality of memory cells of the memory is completed, wherein the plurality of memory cells are respectively used to perform writing of a plurality of write bits of write data in parallel; in response to detecting that the write operation of the first memory cell is completed, independently generating write completion information for the first memory cell; and in response to receiving the write completion information, stopping the write operation of the first memory cell. The memory writing method can detect whether the write operation of the memory cells performing the write operation in parallel is completed, and independently stop the write operation of the memory cell after the write operation of the memory cell is completed, thereby stopping the write driver circuit from continuing to drive the memory cell, reducing the power consumption of the write driver circuit and / or increasing the write speed of the write data.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.

This application provides an SRAM cell and an SRAM memory device. The SRAM cell includes a substrate, and a latch module, a write module, and a read module integrated on the substrate. The latch module includes a pull-up transistor group and a pull-down transistor group, forming a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node. The write module includes a first transmission gate transistor group, which connects a first write word line and a first write bit line pair. The first transmission gate transistor group includes a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first memory node, and the second transmission gate transistor is connected to the second memory node. The read module includes a first read module and a second read module, which are connected to the first memory node and the second read module is connected to the second memory node. This application improves parallel access capabilities.

A memory structure includes: a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a first direction; a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, and a second write-port PG transistor arranged in the first direction; a first read-port PD transistor, a second read-port PD transistor, a first read-port PG transistor, and a second read-port PG transistor arranged in the first direction; a write bit-line conductor extending in the first direction, wherein the write bit-line conductor is under and electrically coupled to a source / drain feature of the first write-port PG transistor; and a write bit-line-bar conductor extending in the first direction, wherein the write bit-line-bar conductor is under and electrically coupled to a source / drain feature of the second write-port PG transistor.

The present application provides a read-write circuit, a method and an array, relating to the technical field of integrated circuits. The read-write circuit at least includes a first switching transistor, a second switching transistor, a spin-orbit torque layer, a plurality of magnetic tunnel junctions, a write bit line, a read bit line and a source line; the plurality of magnetic tunnel junctions are arranged in sequence on the spin-orbit torque layer, and the tops of the plurality of magnetic tunnel junctions are connected to the same read bit line; both ends of the spin-orbit torque layer are respectively connected to the write bit line and the source line. The first switching transistor is used to control the write bit line to apply a write voltage to the spin-orbit torque layer; the second switching transistor is used to control the read bit line to apply a read voltage to the plurality of magnetic tunnel junctions; when reading data, by controlling the conduction or cutoff of the first switching transistor and the second switching transistor, two storage data can be obtained, and the specific storage state of the plurality of magnetic tunnel junctions can be obtained based on the two storage data. The present application can provide a technical solution that can obtain a larger number of resistance states without increasing the storage density.

A memory and an access control method therefor, and an electronic device. The memory comprises: at least one storage array layer and a plurality of common bit lines (CBL) having one-to-one correspondence to each storage array layer. Each storage array layer comprises a plurality of read bit lines (BLr) and a plurality of write bit lines (BLw) extending in a first direction parallel to a substrate. The read bit lines (BLr) and the write bit lines (BLw) on the same layer are connected to a corresponding common bit line (CBL). Each write bit line (BLw) is connected to a corresponding common bit line (CBL) by means of a first write gating sub-circuit (11), and each read bit line (BLr) is connected to a corresponding common bit line by means of a first read gating sub-circuit (12). The first write gating sub-circuit (11) is further connected to a first write gating control line, and is configured to connect / disconnect the write bit line to / from the common bit line under the control of the first write gating control line. The first read gating sub-circuit (12) is further connected to a first read gating control line, and is configured to connect / disconnect the read bit line to / from the common bit line under the control of the first read gating control line.

A static random access memory (SRAM) bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors form a first inverter. The third and fourth transistors form a second inverter. The first inverter and the second inverter are cross-coupled. The write driver circuit is coupled to one reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to connection terminals of the first transistor and the third transistor. The second transistor circuit is coupled between the write driver circuit and another reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a word line.

The embodiment of the invention discloses a shared cache device and method of a chip, and the device comprises a data distribution module which is used for receiving data in a data stream sent by a data bus and sending an instruction for outputting an effective pointer to a pointer processing module, and a shared cache write operation module which is used for receiving the effective pointer output by the pointer processing module and sending the effective pointer to the pointer processing module. The data processing module is used for receiving the data sent by the data distribution module, writing the valid data into the RAM based on the bit number of the valid data in the data and the write bit width of a cache memory in the RAM, determining a cache pointer corresponding to the valid data, and sending the cache pointer to the pointer processing module; the pointer processing module is used for reading a pointer from a pointer pool set in a cache module corresponding to the RAM, and is also used for receiving a read request for reading effective data in the RAM, reading the effective data in the RAM according to a cache pointer corresponding to the read request, and inputting the cache pointer after reading the effective data as a pointer to be recycled into the pointer pool for sharing the RAM by a plurality of data streams; the utilization rate of the shared cache space is improved.

The invention discloses a static random access memory, which comprises Q storage arrays, and the storage arrays comprise M rows of storage units; the row decoding circuit is used for decoding an input address signal to obtain a chip selection signal and a row selection signal; the line-by-line voltage control circuit is used for selecting the first storage array corresponding to the chip selection signal and the target line storage unit corresponding to the line selection signal to perform read-write operation; the column data shifting circuit is used for shifting data in at least one clock period during writing operation, and performing data writing for a target row storage unit through a writing bit line under the control of an input column enable signal; the read-out selection circuit is used for pre-charging the read-out bit line of the target row storage unit during read operation and then reading out data from the target row storage unit through the multi-stage read-out bit line; a data IO port, a DC / DC circuit and a time sequence control circuit. The invention relates to a novel circuit architecture of a low-power-consumption static random access memory.