Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same

a technology of semiconductor memory and transistors, applied in transistors, solid-state devices, instruments, etc., can solve the problems of difficult miniaturization of lsi and large size of write circuits

Active Publication Date: 2007-01-02
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of the write circuit is relatively large and therefore miniaturization of LSI is difficult.

Method used

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  • Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same
  • Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same
  • Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0125]As described above, the flash memory produces the following effects.

[0126](1) The flash memory can be made smaller

[0127]With configuration of the first embodiment, the switch group 150 which transfers the input data from the data input buffer 180 to the write circuit 100 includes only n-channel MOS transistors 151. Therefore, the size of the switch group can be made smaller than when the switch group includes p-channel MOS transistors or when it includes a combination of n-channel MOS transistors and p-channel MOS transistors. Consequently, the flash memory can be made smaller.

[0128](2) The read operation reliability can be improved

[0129]With the configuration of the first embodiment, in a read operation, the reset transistor 106 causes the potentials on the write global bit lines to go to 0V. This reduces noise on the read global bit lines caused by the write global bit lines, when the write global bit lines are close to the read global bit lines. As a result, the read opera...

second embodiment

[0138]Next, a data latch operation in the flash memory of the second embodiment will be explained using FIGS. 15 and 16. FIG. 15 is a flowchart for a data latch operation. FIG. 16 is a circuit diagram to help explain the write circuit 100 and write inhibit control circuit 190 in a data latch operation.

[0139]First, after step S20 to step S22 explained in FIG. 7, write data is input (step S40). Here, as shown in FIG. 16, it is assumed that the number of write global bit lines is 512. If the externally input data are for 512 lines, that is, if the externally input data contain 512 bits (step S41), the latch circuits 101 latch the data allocated to the respective latch circuits by the processes in step S24 to step S27. On the other hand, if the externally input data contains less than 512 bits (step S41), the write inhibit control circuit 190 inputs “1” data to the latch circuits 101 to which no data is input (step S42). The process in step S42 will be explained using FIG. 16.

[0140]As s...

third embodiment

[0177]The LSI of the third embodiment produces not only the effects in items (1) to (4) but also the following effect in item (5).

[0178](5) It is possible to mount a plurality of types of flash memories on a single chip, while suppressing the manufacturing cost.

[0179]The memory cell transistors MT and select transistors ST1, ST2, ST included in the NAND flash memory 500, 3Tr-NAND flash memory 600, and 2Tr flash memory 10 are formed in the same processes. That is, the individual MOS transistors are formed in the same oxidizing process, film-forming process, impurity implanting process, and photolithographic etching process. As a result, the gate insulating film 240, inter-gate insulating film 260, the floating gates 250 and control gates 270 of the memory cell transistors MT, and the select gates 250, 270 of the select transistors are the same in the three flash memories 10, 500, 600. In such a manufacturing method, the memory cell arrays of the three flash memories can be formed by ...

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Abstract

A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-128156, filed Apr. 23, 2004, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a semiconductor memory device and a control method for the semiconductor memory device. More particularly, this invention relates to a nonvolatile semiconductor memory device including MOS transistors, each having a floating gate and a control gate.[0004]2. Description of the Related Art[0005]NOR and NAND flash memories have been widely used as nonvolatile semiconductor memories.[0006]In recent years, a flash memory combining the features of both the NOR and the NAND flash memory has been proposed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C16/04G11C16/06G11C7/00G11C16/10G11C16/26H01L21/8247H01L27/115H01L29/788H01L29/792
CPCG11C16/10H01L27/11524H01L27/115H01L27/11521G11C16/26G11C16/0433G11C16/0483H10B69/00H10B41/30H10B41/35G06K19/077
Inventor KASAI, NOZOMIFUJIMOTO, TAKUYAHIRATA, YOSHIHARU
Owner KK TOSHIBA
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