183 results about "Anisotropic etching" patented technology

The invention discloses a polycrystalline silicon etching method, which comprises the following steps of: firstly, carrying out a polycrystalline silicon etching process for the first time, and carrying out a certain amount of transverse etching; an isotropic dry etching process is adopted, so that the polycrystalline silicon has transverse etching. And then a polycrystalline silicon etching process with a high selection ratio is carried out, and an anisotropic etching process is adopted to ensure that the polycrystalline silicon on the surface is etched cleanly. According to the etching process, a step-by-step etching process method is adopted, the isotropic etching process is firstly carried out to control the etching amount of transverse etching, then the anisotropic etching method and the high-selectivity etching method are adopted to carry out etching of different etching amounts on areas with inconsistent feature sizes, and accurate etching of polycrystalline silicon is guaranteed.

The invention relates to a method for forming a semiconductor structure. The forming method comprises the following steps: after a hard mask lamination covering a gate structure and a substrate is formed, protecting an NMOS (N-channel Metal Oxide Semiconductor) forming region by using a graphical mask, and performing first anisotropic etching to expose the substrate on two sides of the gate structure in a PMOS (P-channel Metal Oxide Semiconductor) forming region; removing the patterned mask, performing second anisotropic etching, and removing a part of the nitride film in the hard mask laminated layer in the NMOS forming region while forming a source drain groove in the PMOS forming region; protecting the substrate in the NMOS forming region by using an oxide film in the hard mask lamination, forming a sigma-shaped groove in the PMOS forming region, and performing heteroepitaxy; and finally, removing the residual hard mask laminated layer and the gate upper oxide layer and the gate upper nitride layer in the gate structure by using a maskless process. According to the method, a photomask process is only used when the patterned mask is formed, so that the cost of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process can be reduced, the damage to the substrate can be reduced, and the performance of a device can be improved.

The invention provides a crystalline silicon solar cell and a preparation method thereof. The preparation method comprises the following steps: carrying out anisotropic corrosion treatment on a silicon wafer, and carrying out first texturing; carrying out isotropic corrosion treatment on the silicon wafer; and carrying out anisotropic corrosion treatment on the silicon wafer, and carrying out second texturing. According to the invention, after the first time of texturing, the silicon wafer is subjected to isotropic corrosion treatment, and the bottom of the textured pyramid is corroded, so that the small pyramid at the tower bottom is removed, and finally, the textured pyramid tower bottom is modified through the second time of texturing, so that the textured uniformity is improved, the reflectivity is reduced, and the photoelectric conversion efficiency of the solar cell is improved.

Techniques are presented for fabricating an integrated circuit with conductive backside contacts beneath source or drain regions. Backside cavities beneath the source or drain regions are formed using backside lithography and anisotropic etching. Subsequently, the backside cavities are filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region extending from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a sub-fin region, which is also removed using backside etching and replaced with a dielectric material.Suitable lithographic operations can be performed on the dielectric backing material along with anisotropic etching to create any number of cavities through the dielectric material. The conductive backing contacts are then formed within these cavities.

The invention discloses a manufacturing method of a PNM IGBT. According to the method, a hard mask technology is adopted, and a multi-time etching technology combining anisotropic etching and isotropic etching is adopted. High-precision table top control is achieved in a low-cost mode, good production and manufacturing control can be achieved, and large-scale mass production is achieved. By means of the method, the feasibility of producing and manufacturing the PNM IGBT device is remarkably improved.

The utility model discloses a kind of clamp type silicon wafer wet depth anisotropic etching equipment, including body, the body inside one side vertical direction is equipped with etching box, the etching box inside near inner wall four sides position are equipped with the wafer sealing clamp for wafer positioning, and wafer sealing clamp top is uniformly equipped with positive pressure gas supply system, equipment overall volume is smaller, mobile convenient, reduce more than 90% organic solvent use, replace traditional adhesive by clamp sealing, internal circulation heating+real-time temperature feedback makes etching uniformity improve 30%, integrated design supports 24 hours continuous operation, failure rate reduces 40%.

The purpose of the present invention is to provide: an etching method with which anisotropic etching of silicon is possible even if a gas having a low GWP is used; a method for manufacturing a semiconductor device; and an etching apparatus. The present invention relates to an etching method for etching silicon at 40°C or lower with use of a plasma gas that is obtained by converting, into plasma, an etching gas composition that contains at least one gas selected from the group consisting of fluorine-containing interhalogens, F2, Cl2, Br2, and I2.　

The embodiment of the invention provides a preparation method of an inner side wall, which comprises the following steps: before forming a first dielectric layer, firstly removing false side walls at two sides of a false gate structure and forming cavities at two sides of a sacrificial layer, and then forming a first part covering the side wall of the false gate structure and a second part filling the cavities and covering the side wall of a stack structure, the first part exposes at least part of the surface, facing the dummy gate structure, of the target channel layer, so that a step structure of which the second part protrudes towards two sides is formed on one side, facing the dummy gate structure, of the first channel layer; and finally, when the inner side wall is formed, anisotropic etching can be performed on the first dielectric layer and the stacked structure by taking the first part as a self-alignment structure so as to form the inner side wall and the outer side wall, and the first part is taken as the self-alignment structure, so that transverse undercutting of the inner side wall is avoided, and the over-etching problem of the inner side wall is improved.

One aspect of this invention is a photoresist composition comprising a thiol derivatives where the thiol moiety is attached to an SP2 carbon which is part of ring which has structures (H1), (H2) (H3), or (H4), and where this thiol additive is present in a range of about 0.5 wt. % to about 3 wt. % of total solids. Another aspect of this invention is to use this photoresist composition on a metal substrate a patterned photoresist which is use as a etch mask in anisotropic wet chemical etching of the metal substate to produce a patterned metallic substrate. Yet Another aspect of this invention is a composition which comprises the above-described thiol derivatives in a spin casting solution and the process of treating a metal substrate which allows overlaid patterned photo resist to be used as an etch mask for wet chemical etching to affect anisotropic etching of the metal substate to also generate patterned metallic substate.

The invention provides a three-dimensional memory preparation process which comprises the following steps: forming a first hard mask layer on a three-dimensional memory substrate, forming a first mesh mask layer on the first hard mask layer, the mesh width of the first mesh mask layer being a, and the mesh width of the first mesh mask layer being b; performing anisotropic etching on the first hard mask layer by taking the first mesh mask layer as a mask to form a circular through hole array, and etching the three-dimensional memory substrate by taking the first hard mask layer as a mask to form a circular through hole array; a fourth hard mask layer is formed on the three-dimensional memory substrate, an annular cylinder array is formed above the fourth hard mask layer, connection lines of cylinder opening circle centers of any four adjacent annular cylinders form a rhombus, and the height of the rhombus is e; a third filling layer is deposited, the top end of the annular cylinder array is exposed through the planarization technology, the annular cylinder array is selectively removed, the remaining third filling layer serves as a mask to etch the fourth hard mask layer, an annular groove array is formed, and the height e of the rhombus is equal to a + b. According to the invention, the memory with a smaller size is prepared.

A method for local removal of semiconductor wires (SW) including the following steps: —Provide a stack of layers including at least a substrate, a nucleation layer, a growth masking layer, and a layer including SW being grown from the nucleation layer through the growth masking layer, —Encapsulate the SW with an encapsulation layer so as to form a composite layer including SW and encapsulating material, —Pattern a hard mask on the composite layer, so as to expose regions of the composite layer, —Perform anisotropic etching of the composite layer in the exposed regions, the anisotropic etching having a selectivity Ssemicon:Sencaps between semiconductor-based material and encapsulating material such as 0.9:1<Ssemicon:Sencaps<1.1:1.

This application discloses the formation of vias using imprint lithography and the formation of repositioning vias by imprint lithography. A resist layer is formed on top of a dielectric layer. For example, a pattern of via openings is imprinted in the resist layer using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. Anisotropic etching has low etch selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with a conductive material to form vias in the dielectric layer. The centerline of at least one repositioning via is not parallel to the centerline of at least one other via.

The present description concerns a method of manufacturing a device comprising memory cells comprising the following steps: a) forming of trenches in a first insulating layer; b) deposition of a layer made of an electrically-resistive material; c) deposition of a second insulating layer on the layer made of the resistive material; d) anisotropic etching of the second layer and of the layer made of the electrically-resistive material so as to only let them remain on the flanks of the first layer and to form resistive heating elements; e) deposition of a third insulating layer into the trenches, so as to completely fill them; f) deposition of a layer made of a phase-change material on the resistive heating elements and the third layer, wherein the first, second, and third layers are made of silicon nitride.

The method includes: etching a dielectric layer to form a dielectric fin; depositing a transition metal dichalcogenide layer on the dielectric fin; and performing an anisotropic etching process on the transition metal dichalcogenide layer. A horizontal portion of the transition metal dichalcogenide layer is removed, while a vertical portion of the transition metal dichalcogenide layer located on the sidewalls of the dielectric fin is retained to form a vertical semiconductor ring. The method also includes: forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring; and forming source / drain contact plugs, wherein the source / drain contact plugs contact the sidewalls of a second portion of the vertical semiconductor ring. Embodiments of the present application also relate to semiconductor devices and methods of forming semiconductor devices.

The invention provides a side wall structure, a forming method thereof and a semiconductor device, and the forming method of the side wall structure comprises the steps: providing a substrate which is provided with a gate structure; sequentially forming a first side wall material layer, a second side wall material layer and a third side wall material layer to cover the surface of the substrate and the outer wall of the gate structure along the shape, and forming a convex structure above the gate structure; forming a hard sacrificial material layer to cover the surface of the third side wall material layer in a conformal manner; executing a first anisotropic etching process to etch the hard sacrificial material layer, exposing the surface of the third side wall material layer, and reserving a part of the hard sacrificial material layer on the side wall of the convex structure; and executing a second anisotropic etching process to sequentially etch the third side wall material layer, the second side wall material layer and the first side wall material layer so as to form a side wall structure on the side wall of the gate structure. According to the invention, a thicker side wall structure can be easily formed.

The invention belongs to the field of integrated circuit electronic chemicals, and particularly relates to an etching solution for removing a polycrystalline silicon false gate, which mainly comprises quaternary ammonium hydroxide, alcohol, an organic solvent, an anisotropic etching weakening additive and water. The etching liquid is mainly used for removing polycrystalline silicon false gates in the semiconductor manufacturing process, and the liquid medicine has certain organic polymer cleaning capacity and can synchronize polymer residues formed after dry etching. After being treated by the liquid medicine, no polymer or polycrystalline silicon is left on the surface of the structure, and the liquid medicine has high stability and long service life.

The present invention discloses a method for manufacturing a MOSFET with an undoped channel. The method includes: manufacturing a semiconductor structure with a pseudo polysilicon gate, a pseudo interlayer (IL) oxide and a doped channel on a substrate. The method also includes removing the pseudo polysilicon gate and the pseudo IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the above-mentioned area on the substrate, and forming a metal gate for the semiconductor structure. Removing the pseudo polysilicon gate may include dry and wet etching operations. Removing the pseudo IL oxide may include dry etching operations. Removing the doped channel may include performing an anisotropic etching operation on the substrate. Forming the undoped channel may include using an epitaxial process to grow the undoped channel. The method may also include growing IL oxide above the undoped channel.

This invention relates to the field of printed circuit board manufacturing technology and discloses a fine etching process for PCB circuit patterns. The process includes injecting a fine etching composition comprising deionized water, hydrochloric acid, copper chloride dihydrate, anhydrous magnesium chloride, p-toluenesulfonic acid monohydrate, polyethylene glycol, and 2-mercaptobenzimidazole into a circulating working tank of an etching machine; setting the temperature of the working solution in the circulating working tank; sending the substrate to be etched, after dry film development, into a spray section; activating the spray array and setting the spray pressure to etch the substrate; and rapidly rinsing the etched substrate in a deionized water washing section, followed by strong air drying to obtain the circuit pattern. This invention reduces surface tension through specific components to promote solution penetration into the microstructure, utilizes an organic corrosion inhibitor to form a stable protective layer on the trench sidewalls, and combines the vertical impact of the nozzle jet on the bottom, leveraging the difference between mechanical force and chemical adsorption force to achieve anisotropic etching, thus suppressing lateral corrosion of fine circuits.

The present invention provides a method for processing a system-level double-sided fan-out packaging structure using an aluminum substrate, comprising: using an aluminum alloy substrate as a bottom plate; making a double-sided cavity mask on the aluminum alloy substrate and performing a non-penetrating anodization on the substrate; making a structural and functional integrated carrier by selectively penetrating aluminum anodization and the anisotropic etching characteristics of anodized aluminum; mounting chips in the cavity of the structural and functional integrated carrier and wiring on the surface of the carrier; making a redistribution layer on the surface of the carrier; completely encapsulating one side of the carrier with epoxy plastic encapsulant and planting balls on the other side to form a system-level double-sided fan-out packaging structure. The method of the present invention uses an aluminum anodized structural and functional integrated carrier, has the characteristics of simple process flow, low cost, high precision of the anisotropic etching processing cavity, good thermal conductivity, etc., and can improve the precision, density, support strength, heat dissipation capacity and signal transmission integrity of the chip double-sided fan-out packaging.

A semiconductor device that operates at high speed is provided. The semiconductor device is fabricated in the following manner: a first coating film over a first insulator and a second coating film over the first coating film are formed; a first layer is formed by partly removing the second coating film; a second layer is formed by partly removing the first coating film using the first layer as a mask; heat treatment is performed; a first oxide semiconductor is formed to cover a top surface of the first insulator, a side surface of the second layer, and a side surface and a top surface of the first layer; a second oxide semiconductor is formed in contact with the side surface of the second layer by processing the first oxide semiconductor by anisotropic etching; the first layer is removed; and a side surface of the second oxide semiconductor that is covered with the second layer is exposed by removing the second layer.

The invention provides a manufacturing method of a field effect transistor and the field effect transistor, and the method comprises the steps: forming a first groove in a first conductive type semiconductor drift region, forming a second groove on the basis of the first groove, carrying out the anisotropic etching of a first oxide layer formed in the second groove, and forming a second oxide layer formed in the second groove; and carrying out ion implantation on the etched second groove to form a super junction column-like region, and forming a shield gate polycrystalline silicon electrode in the second groove. According to the manufacturing method of the field effect transistor provided by the invention, the super junction structure and the shield gate structure are integrated in the same field effect transistor, so that the field effect transistor has the advantages of the super junction structure and the shield gate structure, the on-resistance is remarkably reduced, the breakdown voltage is improved, and the field effect transistor is more compact. The limitation of ion diffusion in the traditional super-junction process is overcome, the forming width of the super-junction structure is controlled, and the process is simpler to implement.

Methods for manufacturing a large number of memory cells, including: Providing a substrate (99) that includes an access circuit for the plurality of memory cells and that has a contact surface (100) with an array of conductive contact plugs (120, 141) connected to the access circuit; Forming a layer of bottom electrode material (200) on the contact surface (100) of the substrate (99); Formation of mask structures (201, 202) on the layer of bottom electrode material (200); Preparing the mask structures (201, 202) on the layer of bottom electrode material (200) by isotropic etching of the mask structures (201, 202) to create a pattern of prepared mask structures (201A, 202A); Removal of material from the layer of bottom electrode material (200) by anisotropic etching using the prepared mask structures (201A, 202A) as an etch mask to form a pattern of electrode columns (210, 211) on corresponding conductive contact plugs (120, 141) in the field of conductive contact plugs (120, 141); Forming a layer of dielectric material (212) covering the pattern of electrode columns (210, 211) and exposed sections of the contact surface (100); Planarizing the layer of dielectric material (212) and the electrode columns (210, 211) to create an electrode surface in which one top surface (222, 223) of each electrode column (210, 211) in the pattern of electrode columns is exposed; Forming a layer of programmable resistive material (230) on the electrode surface; Forming a layer of top electrode material (231) over the layer of programmable resistive material (230); and Patterns of the layer of programmable resistive material (230) and the layer of top electrode material (231).

The present application discloses a cell structure of an image sensor, comprising: a semiconductor substrate, and a photoelectric conversion diode formed in the semiconductor substrate. More than one grooves are formed in a back region of the semiconductor substrate, and the grooves have cross sections in a triangle shape or an inverted trapezoid shape with a downward apex. The grooves are filled with a first dielectric layer having a refractive index less than that of the semiconductor substrate. The first dielectric layer filled in the grooves forms an optical path increasing structure for increasing an effective optical path of back incoming light. The grooves have sides along a first crystalline surface of the semiconductor substrate, and the first crystalline surface is a stop surface for anisotropic etching of the semiconductor substrate. The present application also discloses a method of making an image sensor.

The present application belongs to the technical field of semiconductors. Disclosed are a transistor preparation method and an electronic device. The method comprises: etching a first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303), so as to form a plurality of first silicon pillars (304) in a first direction; etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to a plurality of columns of second masks (305); forming laterally epitaxial silicon on the first silicon layer (301), a lateral groove and the second silicon layer (303); depositing a gate material above the first silicon layer (301); performing anisotropic etching of the gate material according to a plurality of side walls (305-1), so as to form a plurality of second silicon pillars (306); and forming a vertical gate-all-around transistor on the basis of the plurality of second silicon pillars (306). The method prevents a source / drain from being contaminated with metal.

According to one embodiment, a manufacturing method is to manufacture a display device in which a partition including a lower portion and an upper portion arranged on the lower portion to protrude from a side surface of the lower portion is arranged on a boundary between adjacent sub-pixels, and the method comprises forming a metal layer above a substrate, forming the upper portion on the metal layer, reducing a thickness of a first portion of the metal layer exposed from the upper portion by anisotropic etching, and forming the lower portion by reducing a width of a second portion of the metal layer located under the upper portion by isotropic etching.

To provide a method for manufacturing a double-sided texture substrate capable of easily and surely manufacturing the double-sided texture substrate having textures of different sizes on the front and rear surfaces.SOLUTION: A method of manufacturing a double-sided texture substrate according to one aspect of the present invention includes forming a first texture on a first main surface on one side and a second main surface on the other side of a semiconductor substrate by first anisotropic etching, forming an etching mask that wraps around to an end portion of the second main surface on the first main surface, removing the first texture together with a wrapped portion of the etching mask by polishing the second main surface, and forming a second texture smaller than the first texture on the second main surface by second anisotropic etching.SELECTED DRAWING: Figure 1

The present disclosure provides a method of manufacturing a semiconductor structure having fins. The method includes providing a semiconductor substrate including a plurality of initial fin structures. The method also includes forming an isolation material covering the plurality of initial fin structures. The method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. The method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.

This invention relates to a method for etching away residual material on the side of a device, comprising: Step 1: preparing a substrate material, which is one of silicon-based materials, organic materials, or metallic materials; Step 2: fabricating a mask pattern on the surface of the substrate material using a mask material, which is one of metal, silicon oxide, silicon nitride, or photoresist, to obtain a sample to be processed; Step 3: if the sample to be processed does not have a preset pattern, depositing a target material on the surface of the sample and completing a secondary pattern transfer; if the sample to be processed contains a preset pattern, proceeding to Step 4; Step 4: etching the sample to be processed using an anisotropic etching method to perform preliminary etching on the areas to be etched; Step 5: continuing etching using an isotropic etching method to remove residual material on the side and in the pits of the sample to be processed. This invention can efficiently remove residual material on the side while reducing damage to the sample surface caused by etching.

The invention discloses a processing method of a nano microneedle, which relates to the technical field of nano microneedles and comprises the following steps: cleaning the surface of a monocrystalline silicon or gold wafer, coating photoresist on the surface of the monocrystalline silicon or gold wafer, drying, transferring a microneedle array pattern to a photoresist layer through a photoetching process, putting the wafer into a vacuum reaction cavity, introducing reaction gas, and carrying out vacuum reaction on the wafer and the photoresist layer to obtain the nano microneedle. The processing method comprises the following steps: applying radio frequency power to generate plasma, carrying out anisotropic etching on a wafer, forming a microneedle cylinder, removing residual photoresist and cleaning to obtain a microneedle array, applying UV glue to a preset position of a plastic part, mounting the microneedle array to the glue dispensing position of the plastic part, and then carrying out UV irradiation on a mounted product to cure the UV glue. The size, the shape and the position of the microneedle and the nanostructure can be controlled by accurately designing a mask and etching parameters, the size range is from dozens of micrometers to hundreds of micrometers, the shape is from a cylinder to a cone, and the design freedom degree is large.

The invention provides a complementary field effect transistor and a manufacturing method thereof, and a static random access memory, and the method comprises the steps: providing a substrate, forming a laminated structure, forming a second type work function layer in a plurality of to-be-filled gaps, filling a protection material to form a protection layer, and etching the protection layer with a first thickness through employing an anisotropic technology, the isotropic process is continuously utilized to etch the protective layer with the second thickness, and the difference value between the second thickness and 1 / 2 of the width of the gap to be filled is smaller than the target threshold value, that is, the anisotropic process is utilized to etch the protective layer with the first thickness, and then the isotropic process is continuously utilized to etch the protective layer with the second thickness; therefore, accurate etching of the protection layer is realized. Therefore, the anisotropic etching is combined with the isotropic etching, so that the accurate etching of the protective layer can be realized, the accurate control of the position of the protective layer is realized, the work function layer is prevented from covering wrong transistors, and the risk of confusion of transistor types is reduced.