1024 results about "Anisotropic etching" patented technology

A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

Etch profile control with pulsed gas flow and its applications to etching such as anisotropic etching of high aspect ratio features and etching of self-aligned contact structures in various processes. Pulsing can be applied according to this invention to the flow rate of a gas such as an etchant gas, a gas that leads to the deposition of a protective layer, a gas that modifies the deposition of a protective layer, and a gas that modifies etching.

In an embodiment, a method for transferring a pattern constituted by vertical spacers arranged on a template with intervals to the template, includes depositing by plasma-enhanced cyclic deposition a layer as a spacer umbrella layer substantially only on a top surface of each vertical spacer made of silicon or metal oxide, wherein substantially no layer is deposited on sidewalls of the vertical spacers and on an exposed surface of the template, followed by transferring the pattern constituted by the vertical spacers to the template by anisotropic etching using the vertical spacers with the spacer umbrella layers.

A first trench and a second trench having width wider than the first trench are simultaneously formed in a main surface area of a semiconductor substrate. The width of an opening portion of the first trench is made narrower by forming a first insulating film on the main surface of the semiconductor substrate and in the first and second trenches. A second insulating film is formed on the first insulating film by use of a high-density plasma-CVD method to form a void in the first trench while covering the opening portion of the first trench, and the second trench is filled with the second insulating film. Then, part of the second insulating film which covers the opening portion is removed by anisotropic etching and the void is filled with an insulating film having fluidity at the film formation time.

An LED can include a silicon substrate and a pair of electrodes formed inside a horn that is formed on the silicon substrate by anisotropic etching. The LED can include an LED chip mounted inside the horn, the LED chip being electrically connected to the pair of electrodes. A resin mold made of a resin material can be filled in the horn.

A manufacturing method for an ink jet head having an ink ejection pressure generation element for generating energy for ejecting ink, and an ink supply port for supplying the ink to an ink jet head, including the steps of preparing a silicon substrate; forming, on a surface of the silicon substrate, the ink ejection pressure generation element and silicon oxide film or silicon nitride film; forming anti-etching mask for forming an ink supply port on a back side of the silicon substrate; removing silicon on the back side of the silicon substrate at a position corresponding to the ink supply port portion through anisotropic etching; forming an ink ejection portion on a surface of the silicon substrate; and removing the silicon oxide film or silicon nitride film from the surface of the silicon substrate of the ink supply port portion.

The invention provides a method of producing a through-hole, a substrate used to produce a through-hole, a substrate having a through-hole, and a device using such a through-hole or a substrate having such a through-hole, which are characterized in that: a through-hole can be produced only by etching a silicon substrate from its back side; the opening length d can be precisely controlled to a desired value regardless of the variations in the silicon wafer thickness, and the orientation flat angle, and also regardless of the type of a silicon crystal orientation-dependent anisotropic etchant employed; high productivity, high production reproducibility, and ease of production can be achieved; a high-liberality can be achieved in the shape of the opening end even if temperature treatment is performed at a high temperature for a long time; and a high-precision through-hole can be produced regardless of the shape of a device formed on the surface of a substrate.

Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl₂ plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl₂ plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.

An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.

A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

The invention discloses a micro fluid control detection device based on surface-enhanced Raman scattering active substrate. The micro fluid control detection device is obtained by the method including the following steps: photoresist is coated on substrate in spinning way, prebaking, exposure, developing and fixing are sequentially carried out on the photoresist, so as to form photoresist graph in micro fluid shape; plasma dry etching is carried out on the photoresist, thus forming nano granular structure or nano fiber upright structure in vertical distribution on the substrate; the nano granular structure is a mask, anisotropic etching is carried out on the substrate, thus forming nano column on the substrate; metal nano granular layer is sputtered on the silicon nano column or nano fiber upright structure, so as to obtain surface-enhanced Raman scattering active substrate; and a silicon-PDMS double-layer structure SERS micro fluid control detection device which has no impurity interference and can be monitored in real time is formed by combining micro fluid device and processing technology thereof. The micro fluid control device not only can be used for detection of liquid analyte to be analyzed but also can be used for detection of colloid and gas analyte to be analyzed.

A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

A probe card has first contact terminals electrically connected to the fine-pitch electrodes of a test target; wirings drawn from the first contact terminals; and second contact terminals electrically connected to the wirings, wherein the first contact terminals are formed each using an anisotropically etched hole in a crystalline substrate, and a semiconductor device test method (fabrication method) using the probe card.

Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.