78 results about "Anisotropic etching" patented technology

Techniques are presented for fabricating an integrated circuit with conductive backside contacts beneath source or drain regions. Backside cavities beneath the source or drain regions are formed using backside lithography and anisotropic etching. Subsequently, the backside cavities are filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region extending from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a sub-fin region, which is also removed using backside etching and replaced with a dielectric material.Suitable lithographic operations can be performed on the dielectric backing material along with anisotropic etching to create any number of cavities through the dielectric material. The conductive backing contacts are then formed within these cavities.

The utility model discloses a kind of clamp type silicon wafer wet depth anisotropic etching equipment, including body, the body inside one side vertical direction is equipped with etching box, the etching box inside near inner wall four sides position are equipped with the wafer sealing clamp for wafer positioning, and wafer sealing clamp top is uniformly equipped with positive pressure gas supply system, equipment overall volume is smaller, mobile convenient, reduce more than 90% organic solvent use, replace traditional adhesive by clamp sealing, internal circulation heating+real-time temperature feedback makes etching uniformity improve 30%, integrated design supports 24 hours continuous operation, failure rate reduces 40%.

The purpose of the present invention is to provide: an etching method with which anisotropic etching of silicon is possible even if a gas having a low GWP is used; a method for manufacturing a semiconductor device; and an etching apparatus. The present invention relates to an etching method for etching silicon at 40°C or lower with use of a plasma gas that is obtained by converting, into plasma, an etching gas composition that contains at least one gas selected from the group consisting of fluorine-containing interhalogens, F2, Cl2, Br2, and I2.　

The embodiment of the invention provides a preparation method of an inner side wall, which comprises the following steps: before forming a first dielectric layer, firstly removing false side walls at two sides of a false gate structure and forming cavities at two sides of a sacrificial layer, and then forming a first part covering the side wall of the false gate structure and a second part filling the cavities and covering the side wall of a stack structure, the first part exposes at least part of the surface, facing the dummy gate structure, of the target channel layer, so that a step structure of which the second part protrudes towards two sides is formed on one side, facing the dummy gate structure, of the first channel layer; and finally, when the inner side wall is formed, anisotropic etching can be performed on the first dielectric layer and the stacked structure by taking the first part as a self-alignment structure so as to form the inner side wall and the outer side wall, and the first part is taken as the self-alignment structure, so that transverse undercutting of the inner side wall is avoided, and the over-etching problem of the inner side wall is improved.

A method for local removal of semiconductor wires (SW) including the following steps: —Provide a stack of layers including at least a substrate, a nucleation layer, a growth masking layer, and a layer including SW being grown from the nucleation layer through the growth masking layer, —Encapsulate the SW with an encapsulation layer so as to form a composite layer including SW and encapsulating material, —Pattern a hard mask on the composite layer, so as to expose regions of the composite layer, —Perform anisotropic etching of the composite layer in the exposed regions, the anisotropic etching having a selectivity Ssemicon:Sencaps between semiconductor-based material and encapsulating material such as 0.9:1<Ssemicon:Sencaps<1.1:1.

This application discloses the formation of vias using imprint lithography and the formation of repositioning vias by imprint lithography. A resist layer is formed on top of a dielectric layer. For example, a pattern of via openings is imprinted in the resist layer using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. Anisotropic etching has low etch selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with a conductive material to form vias in the dielectric layer. The centerline of at least one repositioning via is not parallel to the centerline of at least one other via.

The present description concerns a method of manufacturing a device comprising memory cells comprising the following steps: a) forming of trenches in a first insulating layer; b) deposition of a layer made of an electrically-resistive material; c) deposition of a second insulating layer on the layer made of the resistive material; d) anisotropic etching of the second layer and of the layer made of the electrically-resistive material so as to only let them remain on the flanks of the first layer and to form resistive heating elements; e) deposition of a third insulating layer into the trenches, so as to completely fill them; f) deposition of a layer made of a phase-change material on the resistive heating elements and the third layer, wherein the first, second, and third layers are made of silicon nitride.

The invention belongs to the field of integrated circuit electronic chemicals, and particularly relates to an etching solution for removing a polycrystalline silicon false gate, which mainly comprises quaternary ammonium hydroxide, alcohol, an organic solvent, an anisotropic etching weakening additive and water. The etching liquid is mainly used for removing polycrystalline silicon false gates in the semiconductor manufacturing process, and the liquid medicine has certain organic polymer cleaning capacity and can synchronize polymer residues formed after dry etching. After being treated by the liquid medicine, no polymer or polycrystalline silicon is left on the surface of the structure, and the liquid medicine has high stability and long service life.

This invention relates to the field of printed circuit board manufacturing technology and discloses a fine etching process for PCB circuit patterns. The process includes injecting a fine etching composition comprising deionized water, hydrochloric acid, copper chloride dihydrate, anhydrous magnesium chloride, p-toluenesulfonic acid monohydrate, polyethylene glycol, and 2-mercaptobenzimidazole into a circulating working tank of an etching machine; setting the temperature of the working solution in the circulating working tank; sending the substrate to be etched, after dry film development, into a spray section; activating the spray array and setting the spray pressure to etch the substrate; and rapidly rinsing the etched substrate in a deionized water washing section, followed by strong air drying to obtain the circuit pattern. This invention reduces surface tension through specific components to promote solution penetration into the microstructure, utilizes an organic corrosion inhibitor to form a stable protective layer on the trench sidewalls, and combines the vertical impact of the nozzle jet on the bottom, leveraging the difference between mechanical force and chemical adsorption force to achieve anisotropic etching, thus suppressing lateral corrosion of fine circuits.

The invention provides a manufacturing method of a field effect transistor and the field effect transistor, and the method comprises the steps: forming a first groove in a first conductive type semiconductor drift region, forming a second groove on the basis of the first groove, carrying out the anisotropic etching of a first oxide layer formed in the second groove, and forming a second oxide layer formed in the second groove; and carrying out ion implantation on the etched second groove to form a super junction column-like region, and forming a shield gate polycrystalline silicon electrode in the second groove. According to the manufacturing method of the field effect transistor provided by the invention, the super junction structure and the shield gate structure are integrated in the same field effect transistor, so that the field effect transistor has the advantages of the super junction structure and the shield gate structure, the on-resistance is remarkably reduced, the breakdown voltage is improved, and the field effect transistor is more compact. The limitation of ion diffusion in the traditional super-junction process is overcome, the forming width of the super-junction structure is controlled, and the process is simpler to implement.

Methods for manufacturing a large number of memory cells, including: Providing a substrate (99) that includes an access circuit for the plurality of memory cells and that has a contact surface (100) with an array of conductive contact plugs (120, 141) connected to the access circuit; Forming a layer of bottom electrode material (200) on the contact surface (100) of the substrate (99); Formation of mask structures (201, 202) on the layer of bottom electrode material (200); Preparing the mask structures (201, 202) on the layer of bottom electrode material (200) by isotropic etching of the mask structures (201, 202) to create a pattern of prepared mask structures (201A, 202A); Removal of material from the layer of bottom electrode material (200) by anisotropic etching using the prepared mask structures (201A, 202A) as an etch mask to form a pattern of electrode columns (210, 211) on corresponding conductive contact plugs (120, 141) in the field of conductive contact plugs (120, 141); Forming a layer of dielectric material (212) covering the pattern of electrode columns (210, 211) and exposed sections of the contact surface (100); Planarizing the layer of dielectric material (212) and the electrode columns (210, 211) to create an electrode surface in which one top surface (222, 223) of each electrode column (210, 211) in the pattern of electrode columns is exposed; Forming a layer of programmable resistive material (230) on the electrode surface; Forming a layer of top electrode material (231) over the layer of programmable resistive material (230); and Patterns of the layer of programmable resistive material (230) and the layer of top electrode material (231).

The present application discloses a cell structure of an image sensor, comprising: a semiconductor substrate, and a photoelectric conversion diode formed in the semiconductor substrate. More than one grooves are formed in a back region of the semiconductor substrate, and the grooves have cross sections in a triangle shape or an inverted trapezoid shape with a downward apex. The grooves are filled with a first dielectric layer having a refractive index less than that of the semiconductor substrate. The first dielectric layer filled in the grooves forms an optical path increasing structure for increasing an effective optical path of back incoming light. The grooves have sides along a first crystalline surface of the semiconductor substrate, and the first crystalline surface is a stop surface for anisotropic etching of the semiconductor substrate. The present application also discloses a method of making an image sensor.

According to one embodiment, a manufacturing method is to manufacture a display device in which a partition including a lower portion and an upper portion arranged on the lower portion to protrude from a side surface of the lower portion is arranged on a boundary between adjacent sub-pixels, and the method comprises forming a metal layer above a substrate, forming the upper portion on the metal layer, reducing a thickness of a first portion of the metal layer exposed from the upper portion by anisotropic etching, and forming the lower portion by reducing a width of a second portion of the metal layer located under the upper portion by isotropic etching.

To provide a method for manufacturing a double-sided texture substrate capable of easily and surely manufacturing the double-sided texture substrate having textures of different sizes on the front and rear surfaces.SOLUTION: A method of manufacturing a double-sided texture substrate according to one aspect of the present invention includes forming a first texture on a first main surface on one side and a second main surface on the other side of a semiconductor substrate by first anisotropic etching, forming an etching mask that wraps around to an end portion of the second main surface on the first main surface, removing the first texture together with a wrapped portion of the etching mask by polishing the second main surface, and forming a second texture smaller than the first texture on the second main surface by second anisotropic etching.SELECTED DRAWING: Figure 1

This invention relates to a method for etching away residual material on the side of a device, comprising: Step 1: preparing a substrate material, which is one of silicon-based materials, organic materials, or metallic materials; Step 2: fabricating a mask pattern on the surface of the substrate material using a mask material, which is one of metal, silicon oxide, silicon nitride, or photoresist, to obtain a sample to be processed; Step 3: if the sample to be processed does not have a preset pattern, depositing a target material on the surface of the sample and completing a secondary pattern transfer; if the sample to be processed contains a preset pattern, proceeding to Step 4; Step 4: etching the sample to be processed using an anisotropic etching method to perform preliminary etching on the areas to be etched; Step 5: continuing etching using an isotropic etching method to remove residual material on the side and in the pits of the sample to be processed. This invention can efficiently remove residual material on the side while reducing damage to the sample surface caused by etching.

The invention discloses a processing method of a nano microneedle, which relates to the technical field of nano microneedles and comprises the following steps: cleaning the surface of a monocrystalline silicon or gold wafer, coating photoresist on the surface of the monocrystalline silicon or gold wafer, drying, transferring a microneedle array pattern to a photoresist layer through a photoetching process, putting the wafer into a vacuum reaction cavity, introducing reaction gas, and carrying out vacuum reaction on the wafer and the photoresist layer to obtain the nano microneedle. The processing method comprises the following steps: applying radio frequency power to generate plasma, carrying out anisotropic etching on a wafer, forming a microneedle cylinder, removing residual photoresist and cleaning to obtain a microneedle array, applying UV glue to a preset position of a plastic part, mounting the microneedle array to the glue dispensing position of the plastic part, and then carrying out UV irradiation on a mounted product to cure the UV glue. The size, the shape and the position of the microneedle and the nanostructure can be controlled by accurately designing a mask and etching parameters, the size range is from dozens of micrometers to hundreds of micrometers, the shape is from a cylinder to a cone, and the design freedom degree is large.

The present application relates to a fabrication method for a micro-opto-electro-mechanical element. The fabrication method comprises: providing a substrate; forming a matrix material layer on the substrate; forming a first groove on the matrix material layer; forming a second mask material layer on the bottom wall and the side wall of the first groove; using an anisotropic etching process to etch the second mask material layer, so as to remove the second mask material layer located on the bottom wall of the first groove while retaining the second mask material layer located on the side wall of the first groove; etching an exposed region of the bottom wall of the first groove to form a second groove; and forming a lens layer in the first groove and the second groove. The present application can not only improve the symmetry of an optical element to enhance the optical performance of the optical element, but also reduce fabrication costs.

The invention discloses a convex corner protection technology during deep corrosion of a silicon island. Each silicon island (4) adopts four lt; 110gt, 110gt; and the crystal orientation two-end clamped beam (5) and the two cantilever beams (6) form a convex angle protection pattern. Lt; 110gt, 110gt; and one end of the crystal orientation two-end clamped beam (5) is clamped on the frame (8), and the other clamped end of the crystal orientation two-end clamped beam (5) is connected with the free end of the cantilever beam (6). And the clamped end of the cantilever beam (6) is connected with the silicon island (4) and is as wide as the silicon island (4). The anisotropic corrosive liquid is firstly undercut; 110gt, 110gt; and beams (5) are clamped at two ends of the crystal orientation. Then, mask-free corrosion fault is carried out; 110gt, 110gt; a silicon wedge (9) below the beam (5) is clamped and supported at the two ends of the crystal orientation so as to obtain a flat corrosion surface, and at the same time, the corrosion liquid undercuts the cantilever beam (6) from the free end of the cantilever beam (6), 110gt, 110gt; the silicon wedges (9) below the clamped beams (5) at the two ends of the crystal orientation are completely corroded, the cantilever beam (6) is undercut when a flat corrosion surface is formed, and the part of the left silicon island (4) is not undercut. The convex angle protection pattern is small in occupied area, leads can be arranged on the convex angle protection pattern, and the convex angle protection pattern is particularly suitable for the condition that the silicon island (4) is small in size and close to the frame (8).

After a silicon oxide film is formed on a main surface of a semiconductor substrate so as to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film with a photoresist pattern formed thereon used as an etching mask, and an anisotropic etching is further performed on the silicon oxide film. Accordingly, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining below the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

This invention relates to the field of silicon capacitor technology and is widely used in various radio frequency and optical communication products. The main technology is a silicon capacitor comprising: a through-silicon via (TSV) substrate, a dielectric layer, a second electrode layer, an insulating layer, a first electrode layer, through-hole leads, and upper and lower pads. The TSVs in the TSV substrate are cylindrical, prismatic, or dumbbell-shaped. The cylindrical and prismatic sidewalls are vertical, while the dumbbell-shaped sidewalls are inclined. Inverted truncated pyramids are formed by anisotropic etching of silicon on both sides. The TSV array forms a repeating structure, with the opening diameter of a single TSV ranging from 2μm to 20μm. This invention utilizes TSV technology, opening on both sides, overcoming the problems of poor uniformity in U-shaped deep trench etching and inconsistent hole depth in existing technologies, as well as the high stress and fragmentation during capacitor fabrication caused by U-shaped deep trenches opening on only one side.

The present disclosure relates to a manufacturing method of a semiconductor device. After a silicon oxide film is formed on a main surface of a semiconductor substrate to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film using a photoresist pattern formed thereon as an etching mask, and then a further anisotropic etching is performed on the silicon oxide film. Thus, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining under the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

The invention discloses a diamond micro-nano structure and a preparation method thereof, and relates to the technical field of material preparation. The method comprises the following steps: growing a diamond film on the surface of a pretreated base material; a metal mask layer corresponding to the micro-nano structure is formed on the surface of the diamond film through patterning treatment, and a first intermediate product is obtained; anisotropic etching treatment is carried out on the first intermediate product to remove the diamond film except the micro-nano structure, and a second intermediate product is obtained; performing secondary etching treatment on the second intermediate product to obtain a third intermediate product; carrying out isotropic etching treatment on a base material of the third intermediate product by adopting an etching solution to obtain a fourth intermediate product; and the fourth intermediate product is sequentially put into an acidic mixed solution and an alkaline solution to be treated, so that residual impurities in the fourth intermediate product are removed, and the diamond micro-nano structure is prepared. The invention aims to solve the problems that the edge of the micro-nano structure is burnt and the micro-nano structures with different styles and different sizes cannot be prepared on a large scale.

A manufacturing method of a semiconductor structure including the following steps is disclosed. A definition layer is formed on a substrate. The definition layer includes a first dielectric layer and a second dielectric layer. A first isotropic etching process is performed on the second dielectric layer to form a first opening in the second dielectric layer. A portion of the first opening is located under the patterned photoresist layer. A first anisotropic etching process is performed on the first dielectric layer to form a second opening in the first dielectric layer. The first opening is connected to the second opening to form a third opening. The patterned photoresist layer is removed. An etch back process is performed on the first dielectric layer and the second dielectric layer, so that a sidewall of the definition layer exposed by the third opening is an inclined surface.

The present disclosure relates to a method for obtaining a miniaturised structure from a bulk anisotropic material, the method comprising: forming, by way of patterning the bulk anisotropic material, a miniaturised structure in an upper surface of a bulk anisotropic material; removing bulk anisotropic material around the miniaturised structure to form a pillar including the miniaturised structure on an upper surface thereof, wherein the upper surface of the pillar is laterally isolated from the surrounding bulk anisotropic material; etching the pillar below the upper surface to reduce a perimeter of at least part of the pillar below the upper surface to thereby form a bottom profile beneath the upper surface, wherein the anisotropic properties of the bulk material result in anisotropic etching of the material of the pillar.

A thinned semiconductor substrate is provided, the front side of which has a front-end-of-process portion. The portion includes conductive structures on the front side of the substrate that need to be contacted by connections through the substrate. An opening is etched from the back side of the substrate, and the opening is to be filled with a conductive material. The bottom of the opening at least partially overlaps the end surface of the conductive structure to be contacted and partially overlaps the semiconductor material of the substrate. The etching of the opening continues beyond the end surface into the semiconductor portion to create a cavity. A first dielectric layer is formed on the sidewalls and bottom of the opening such that the cavity is filled with the material of the first layer. The material is then removed everywhere other than the cavity. If necessary, a second dielectric layer may be formed on the sidewalls and bottom of the opening as a liner, and the opening at the bottom is anisotropically etched to expose the end surface, but the dielectric material of the first layer remains in the cavity. These dielectrically filled cavities thereby suppress the formation of a short circuit between the final punch-through connection obtained by filling the opening and the semiconductor material of the substrate.

A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

The invention provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors, and the method comprises the steps: providing a substrate structure which comprises a substrate, a gate structure located on the substrate, a source region and a drain region which are located at the two sides of the gate structure, and a dielectric layer which covers the gate structure, the source region and the drain region; a hard mask layer is formed on the substrate structure, the hard mask layer is provided with an initial pattern, the expected target pattern comprises a plurality of target openings extending in the first direction, and the initial pattern comprises a plurality of initial openings in one-to-one correspondence with the target openings; anisotropic etching is performed on the hard mask layer to change the initial pattern into a target pattern, and the anisotropic etching enables the size of each initial opening in the first direction to be increased by a target size to form a corresponding target opening.

The present invention provides a method for manufacturing a fiber-waveguide coupler comprising depositing a mask layer on a first surface on a front side of a substrate, wherein the mask layer has at least one opening mark; depositing an intermediate layer on the mask layer; bonding a first oxide layer on the intermediate layer; depositing a stress compensation layer on a second surface on a back side of the substrate, wherein at least one of a material and a thickness of the stress compensation layer are selected for reducing a bow of the substrate; depositing a waveguide structure on the first oxide layer, wherein the waveguide structure has a core layer and a cladding layer, wherein the core layer has a predetermined width and a predetermined thickness and is aligned with the opening mark; and anisotropic etching of a V-groove into the substrate at the opening marker of the mask layer such that when a fiber having a predetermined size is placed inside the V-groove, a core of the fiber is centered with respect to the core layer of the waveguide structure. Further, the present invention provides a corresponding fiber-waveguide coupler, a further method for manufacturing a fiber-waveguide coupler as well as a corresponding further fiber-waveguide coupler.

A method for fabricating a semiconductor device includes forming an active pattern on a substrate, forming sacrificial and semiconductor layers alternately stacked on the active pattern, forming a dummy gate and first source / drain trench on one side of the dummy gate by etching the stacked structure, forming a second source / drain trench on the active pattern by etching a sidewall of the sacrificial layer exposed to the first source / drain trench, forming a first inner spacer material layer along sidewall and bottom surfaces of the second source / drain trench, forming a second inner spacer material layer by anisotropic etching a first inner spacer material layer, and forming a third source / drain trench on the active pattern by isotropic etching.

The invention belongs to the technical field of pressure sensors, and particularly relates to a preparation method of a high-temperature pressure sensor. Comprising the following steps: providing an N-type monocrystalline silicon wafer as a substrate; anisotropic etching is carried out on the substrate to form a deep groove I for isolating the two sides of the piezoresistor body; performing isotropic etching on the basis of the deep groove I to form a deep groove II for isolating the bottom area of the piezoresistor body; filling the deep groove I and the deep groove II with an insulating medium, and performing chemical mechanical polishing and leveling treatment on the redundant insulating medium on the surface of the substrate; anisotropic etching is carried out on the substrate again so as to form a deep groove III for isolating the two ends of the piezoresistor body; filling the deep groove III with an insulating medium, and performing chemical mechanical polishing and leveling treatment on the redundant insulating medium on the surface of the substrate; according to the invention, all-dielectric isolation filling is carried out twice to form a physically isolated piezoresistor body, so that the defect of high-temperature electric leakage of PN isolation is avoided, and the cost of an SOI scheme is reduced.