198 results about "Isotropic etching" patented technology

The invention discloses a polycrystalline silicon etching method, which comprises the following steps of: firstly, carrying out a polycrystalline silicon etching process for the first time, and carrying out a certain amount of transverse etching; an isotropic dry etching process is adopted, so that the polycrystalline silicon has transverse etching. And then a polycrystalline silicon etching process with a high selection ratio is carried out, and an anisotropic etching process is adopted to ensure that the polycrystalline silicon on the surface is etched cleanly. According to the etching process, a step-by-step etching process method is adopted, the isotropic etching process is firstly carried out to control the etching amount of transverse etching, then the anisotropic etching method and the high-selectivity etching method are adopted to carry out etching of different etching amounts on areas with inconsistent feature sizes, and accurate etching of polycrystalline silicon is guaranteed.

The invention provides a crystalline silicon solar cell and a preparation method thereof. The preparation method comprises the following steps: carrying out anisotropic corrosion treatment on a silicon wafer, and carrying out first texturing; carrying out isotropic corrosion treatment on the silicon wafer; and carrying out anisotropic corrosion treatment on the silicon wafer, and carrying out second texturing. According to the invention, after the first time of texturing, the silicon wafer is subjected to isotropic corrosion treatment, and the bottom of the textured pyramid is corroded, so that the small pyramid at the tower bottom is removed, and finally, the textured pyramid tower bottom is modified through the second time of texturing, so that the textured uniformity is improved, the reflectivity is reduced, and the photoelectric conversion efficiency of the solar cell is improved.

The invention discloses a manufacturing and temperature compensation method of a Pirani vacuum gauge compatible with a CMOS, and relates to the field of Pirani vacuum gauges, and the manufacturing method comprises the steps: sequentially depositing a first layer of silicon dioxide, a polycrystalline silicon sacrificial layer, a second layer of silicon dioxide, a polycrystalline silicon thermistor part, a third layer of silicon dioxide and an aluminum layer on a silicon substrate; the aluminum layer is used for forming a lead and a bonding pad; silicon dioxide is selectively removed through reactive ion etching, and the polycrystalline silicon sacrificial layer or the silicon substrate needing to be etched is exposed; etching the polycrystalline silicon sacrificial layer by adopting an isotropic etching technology to obtain a T-shaped device structure; or etching the silicon substrate by adopting a deep silicon etching technology and an isotropic etching technology to obtain an L-shaped device structure. According to the invention, two kinds of Pirani vacuum gauges compatible with CMOS can be manufactured; and meanwhile, through the temperature compensation method, the influence on the output performance can be specifically analyzed based on the environment temperature.

In a gate replacement process, a dummy gate and adjacent structure, such as a source / drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

A finFET device includes a doped source and / or drain extension disposed between a gate spacer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which an n-doped or p-doped source or drain extension is disposed. A doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate to the gate spacer. After forming the cavity, advanced process control (APC) (i.e., integrated metrology) is used to determine the recess distance without exposing the substrate to an oxidizing environment. The isotropic etch process, metrology, and selective epitaxial growth may be performed in the same stage.

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source / drain recess in a source / drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source / drain tip. A depth of the source / drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source / drain recess to the target depth. The source / drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source / drain recess is spaced a distance from a gate footing that can minimize DIBL. The source / drain recess is filled with an epitaxial semiconductor material.

The invention discloses a manufacturing method of a PNM IGBT. According to the method, a hard mask technology is adopted, and a multi-time etching technology combining anisotropic etching and isotropic etching is adopted. High-precision table top control is achieved in a low-cost mode, good production and manufacturing control can be achieved, and large-scale mass production is achieved. By means of the method, the feasibility of producing and manufacturing the PNM IGBT device is remarkably improved.

A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described in which carbon is used as a removable mold material for forming DRAM capacitors. A dense high temperature (500 DEG C or higher) PECVD carbon material is used as a removable mold material (e.g., a core material) in place of an oxide. The carbon material may be removed by isotropic etch under exposure to free radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

The present application relates to a memory array including a string of memory cells and a method for forming a memory array including a string of memory cells. A stack including a first layer and a second layer alternating vertically is formed above the conductor layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. A string of channel material extends through the first layer and the second layer. The material of the first layer has a composition different from that of the material of the second layer. The lowermost first layer of the first layer includes a sacrificial material having a composition different from that of the first layer material above it and the second layer material layer above it. The sacrificial material has a composition different from that of the uppermost portion of the conductor material of the conductor layer. The sacrificial material is selectively etched isotropically relative to the uppermost portion of the conductor material of the conductor layer, selectively relative to the first layer material above it, and selectively relative to the second layer material above it.

Microfabrication process with the following steps: Providing a structure (800) comprising a layer stack (30, 40, 50) containing, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40), and a second silicon oxide layer (50), and a conductive material part (20) below the layer stack (30, 40, 50) and above a substrate (10); Producing a patterned etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Producing a via cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top side of the conductive material part (20) by isotropic etching of parts of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) with an isotropic etching process in which an etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30), wherein: the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical vapor deposition at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) comprises a second silicon oxide material produced by decomposition of tetraethyl orthosilicate.

A method for manufacturing a semiconductor substrate according to one embodiment includes: a first step of forming a groove portion having a bottom surface and side surfaces on which corrugations are formed by performing a process including isotropic etching on a main surface of a substrate; a second step for performing at least one of a hydrophilization treatment performed on a side surface of the groove part and a degassing treatment performed on the groove part; and a third step for removing corrugations formed on the side surfaces of the groove portion by performing anisotropic wet etching treatment in a state where the bottom surface of the groove portion is present, and planarizing the side surfaces.

The invention provides a flash memory and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and sequentially forming a gate oxide layer, a floating gate layer and a mask layer on the substrate; isotropic etching is carried out on the floating gate layer by taking the mask layer as a mask, so that the upper surface of the floating gate layer exposed out of the opening is arc-shaped; a spacer layer, a control gate, an offset layer and an HTO layer are sequentially formed on the side walls of the two sides of the opening of the mask layer; etching to remove the floating gate layer and the gate oxide layer between the HTO layers on the two sides to expose the substrate; forming a tunneling oxide layer, wherein the tunneling oxide layer at least covers the side wall surfaces of the offset layer and the floating gate and the exposed surface of the substrate; and forming a word line, wherein the word line fills the concave cavity region in the tunneling oxide layer. According to the invention, isotropic etching is carried out on the floating gate layer, so that the upper surface of the floating gate layer exposed by the opening is arc-shaped. And the coupling area of the arc-shaped surface of the floating gate and the control gate is increased, so that the coupling rate from the control gate to the floating gate layer is improved, and the coupling efficiency is improved.

The invention discloses a patterned semiconductor substrate, a preparation method thereof and a micro-nano photoelectric / photonic device, the semiconductor substrate comprises at least one of a lithium niobate substrate and a lithium tantalate substrate, and the method comprises the following steps: forming a patterned mask layer on the surface of the semiconductor substrate; performing ion implantation treatment on the semiconductor substrate with the mask layer on the surface so as to form a damaged layer in an area, which is not covered by the mask layer, of the semiconductor substrate; and removing the mask layer, and carrying out wet etching treatment on the damaged layer to obtain a patterned semiconductor substrate. Therefore, according to the preparation method, the lithium niobate substrate or the lithium tantalate substrate can be damaged, then the damaged layer is selectively removed through wet etching, and the preparation method is beneficial for eliminating the isotropic etching problem easily occurring in the traditional wet etching process.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S / D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.

Provided are semiconductor structures and methods for fabricating semiconductor structures. A method includes in a first device region and in a second device region: forming a stack of first epitaxial layers and second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form gaps; and depositing an interposer material over the bottom surface and in the gaps; in the first device region: performing an anisotropic etch of the interposer material located over the bottom surface; and in the first device region and in the second device region: performing an isotropic etch of the interposer material to remove the interposer material located over the bottom surface and to laterally recess the interposer material in the gaps.

The present invention provides a method for doping micro-nano structure fixed-point defects based on a self-alignment process, comprising: S1, forming a sacrificial layer and a photoresist layer on the surface of a crystal substrate in sequence; S2, photoetching a mask hole in the photoresist layer according to a micro-nano pattern; S3, isotropically etching the sacrificial layer through the mask hole, and enlarging the mask hole pattern to the sacrificial layer; S4, performing ion implantation doping on the exposed crystal surface below the mask hole; S5, removing the photoresist layer, and depositing a mask material; S6, removing the sacrificial layer, and transferring the micro-nano enlarged pattern in the sacrificial layer to a mask material pattern; S7, etching the exposed crystal surface, removing the surface mask material, and annealing to form a specific defect. The method provided by the present invention is based on a self-alignment process, does not require alignment operations, has high precision and a simple process, and does not have alignment errors.

The application relates to a silicon nanowire manufacturing method and belongs to the technical field of MEMS. The steps comprise the following: S1, providing an SOI substrate; S2, forming a mask layer on the SOI substrate; S3, patterning the mask layer to form an etching window; S4, performing isotropic etching on the SOI substrate through the etching window to form a cavity and a silicon nanocolumn; S5, oxidizing the silicon nanocolumn to form an oxide layer and a silicon nanowire; and S6, removing the buried oxygen layer and the oxide layer to obtain a suspended silicon nanowire. The application solves the problems of the prior art, such as complex preparation method of the silicon nanowire, high requirement for equipment and poor batch consistency.

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

According to the electrochemical etching method for the anode foil of the high-voltage tantalum capacitor, the tantalum foil is pre-oxidized before etching processing, isotropic etching of the tantalum foil can be achieved by controlling the thickness of an oxidation film on the surface of the tantalum foil, and therefore circular corrosion holes are formed; the corrosion hole with the morphology can eliminate the limitation of adverse crystal face orientation on the depth of the corrosion hole to the greatest extent; then, pulse current is used for hole forming, so that the density of initial corrosion holes can be improved; on the basis, direct current and constant current are used for reaming, so that the diameter and depth of a corrosion hole can be further increased; and finally, enabling the etched tantalum foil to form the high-voltage tantalum capacitor anode foil with high specific volume. The capacitance density of the tantalum anode foil formed by the method can reach 92.6 nF / mm < 2 > under the voltage of 100V, which is about 6 times higher than that before the process is improved. Therefore, the performance of the anode foil of the high-voltage tantalum capacitor is effectively improved.

The invention relates to a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially stacked along a first direction on the substrate, wherein the first semiconductor layer covers the top surface of the substrate; the second semiconductor layer comprises a first element and a second element; wherein the second semiconductor layer comprises a first interface layer, a middle layer and a second interface layer adjacent to the third semiconductor layer which are sequentially arranged in the first direction, and the content of a second element in the first interface layer is gradually reduced in the direction away from the top surface of the substrate; the content of the second element in the second interface layer is gradually increased in the direction away from the top surface of the middle layer; and etching the second semiconductor layer by adopting an isotropic etching process to obtain a rectangular groove. The arc effect of the lateral etching process can be inhibited, and a steeper morphology is formed, so that the squareness of an etching section is improved, and the performance and the reliability of a device are improved.

Methods for manufacturing a large number of memory cells, including: Providing a substrate (99) that includes an access circuit for the plurality of memory cells and that has a contact surface (100) with an array of conductive contact plugs (120, 141) connected to the access circuit; Forming a layer of bottom electrode material (200) on the contact surface (100) of the substrate (99); Formation of mask structures (201, 202) on the layer of bottom electrode material (200); Preparing the mask structures (201, 202) on the layer of bottom electrode material (200) by isotropic etching of the mask structures (201, 202) to create a pattern of prepared mask structures (201A, 202A); Removal of material from the layer of bottom electrode material (200) by anisotropic etching using the prepared mask structures (201A, 202A) as an etch mask to form a pattern of electrode columns (210, 211) on corresponding conductive contact plugs (120, 141) in the field of conductive contact plugs (120, 141); Forming a layer of dielectric material (212) covering the pattern of electrode columns (210, 211) and exposed sections of the contact surface (100); Planarizing the layer of dielectric material (212) and the electrode columns (210, 211) to create an electrode surface in which one top surface (222, 223) of each electrode column (210, 211) in the pattern of electrode columns is exposed; Forming a layer of programmable resistive material (230) on the electrode surface; Forming a layer of top electrode material (231) over the layer of programmable resistive material (230); and Patterns of the layer of programmable resistive material (230) and the layer of top electrode material (231).

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source / drain (S / D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S / D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S / D recesses by the nitride layers and form ILD recesses.

According to one embodiment, a manufacturing method is to manufacture a display device in which a partition including a lower portion and an upper portion arranged on the lower portion to protrude from a side surface of the lower portion is arranged on a boundary between adjacent sub-pixels, and the method comprises forming a metal layer above a substrate, forming the upper portion on the metal layer, reducing a thickness of a first portion of the metal layer exposed from the upper portion by anisotropic etching, and forming the lower portion by reducing a width of a second portion of the metal layer located under the upper portion by isotropic etching.

The present disclosure provides a method of manufacturing a semiconductor structure having fins. The method includes providing a semiconductor substrate including a plurality of initial fin structures. The method also includes forming an isolation material covering the plurality of initial fin structures. The method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. The method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.

This invention relates to a method for etching away residual material on the side of a device, comprising: Step 1: preparing a substrate material, which is one of silicon-based materials, organic materials, or metallic materials; Step 2: fabricating a mask pattern on the surface of the substrate material using a mask material, which is one of metal, silicon oxide, silicon nitride, or photoresist, to obtain a sample to be processed; Step 3: if the sample to be processed does not have a preset pattern, depositing a target material on the surface of the sample and completing a secondary pattern transfer; if the sample to be processed contains a preset pattern, proceeding to Step 4; Step 4: etching the sample to be processed using an anisotropic etching method to perform preliminary etching on the areas to be etched; Step 5: continuing etching using an isotropic etching method to remove residual material on the side and in the pits of the sample to be processed. This invention can efficiently remove residual material on the side while reducing damage to the sample surface caused by etching.

A method of forming a portion of a gate all around field effect transistor (GAA FET) includes forming reserved locations in a recess formed in a portion of a substrate isolated by shallow trench isolation (STI), each reserved location interfacing with an extension region via a cap layer, the recess extending into an interlayer dielectric (ILD) formed on the substrate; selectively removing the reserved location relative to the substrate, the cap layer, and the STI; forming a selective cap layer at the bottom of the groove; performing a substrate removal process to perform isotropic etching on the substrate in the recess; performing a conformal deposition process to form spacer pads on exposed surfaces of the substrate and the selective cap layer within the recess; carving spacing pads on the side walls of the substrate and the STI in the groove; executing a cap layer removal process to remove the cap layer in the groove; and forming a metal contact in the groove.

The invention provides a complementary field effect transistor and a manufacturing method thereof, and a static random access memory, and the method comprises the steps: providing a substrate, forming a laminated structure, forming a second type work function layer in a plurality of to-be-filled gaps, filling a protection material to form a protection layer, and etching the protection layer with a first thickness through employing an anisotropic technology, the isotropic process is continuously utilized to etch the protective layer with the second thickness, and the difference value between the second thickness and 1 / 2 of the width of the gap to be filled is smaller than the target threshold value, that is, the anisotropic process is utilized to etch the protective layer with the first thickness, and then the isotropic process is continuously utilized to etch the protective layer with the second thickness; therefore, accurate etching of the protection layer is realized. Therefore, the anisotropic etching is combined with the isotropic etching, so that the accurate etching of the protective layer can be realized, the accurate control of the position of the protective layer is realized, the work function layer is prevented from covering wrong transistors, and the risk of confusion of transistor types is reduced.

Nanostructured field effect transistor devices and methods of forming the same are provided. A method of forming a semiconductor device includes forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer around the gate structure over the fin; forming a first dielectric plug and a second dielectric plug on opposite sides of the fin and in the gate structure, where the first dielectric plug and the second dielectric plug cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a section of the gate structure between the first dielectric plug and the second dielectric plug; etching a section of the gate structure using an isotropic etching process using the patterned mask layer as an etch mask to form a recess in the gate structure; extending the recess into the fin, where extending the recess includes performing an anisotropic etch process; and after extending the recess, filling the recess with a dielectric material.