13 results about "Isotropic etching" patented technology

Provided are semiconductor structures and methods for fabricating semiconductor structures. A method includes in a first device region and in a second device region: forming a stack of first epitaxial layers and second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form gaps; and depositing an interposer material over the bottom surface and in the gaps; in the first device region: performing an anisotropic etch of the interposer material located over the bottom surface; and in the first device region and in the second device region: performing an isotropic etch of the interposer material to remove the interposer material located over the bottom surface and to laterally recess the interposer material in the gaps.

This invention relates to a method for etching away residual material on the side of a device, comprising: Step 1: preparing a substrate material, which is one of silicon-based materials, organic materials, or metallic materials; Step 2: fabricating a mask pattern on the surface of the substrate material using a mask material, which is one of metal, silicon oxide, silicon nitride, or photoresist, to obtain a sample to be processed; Step 3: if the sample to be processed does not have a preset pattern, depositing a target material on the surface of the sample and completing a secondary pattern transfer; if the sample to be processed contains a preset pattern, proceeding to Step 4; Step 4: etching the sample to be processed using an anisotropic etching method to perform preliminary etching on the areas to be etched; Step 5: continuing etching using an isotropic etching method to remove residual material on the side and in the pits of the sample to be processed. This invention can efficiently remove residual material on the side while reducing damage to the sample surface caused by etching.

After a silicon oxide film is formed on a main surface of a semiconductor substrate so as to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film with a photoresist pattern formed thereon used as an etching mask, and an anisotropic etching is further performed on the silicon oxide film. Accordingly, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining below the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

The present disclosure relates to a manufacturing method of a semiconductor device. After a silicon oxide film is formed on a main surface of a semiconductor substrate to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film using a photoresist pattern formed thereon as an etching mask, and then a further anisotropic etching is performed on the silicon oxide film. Thus, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining under the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

This invention provides a method for fabricating a stepped metal structure and a silicon photonic device, comprising: 1) forming a stepped structure on a substrate; 2) depositing an isolation dielectric layer on the stepped structure; 3) depositing a metal layer, wherein the thickness of the top surface metal is greater than the thickness of the sidewall metal; 4) forming a pattern barrier layer on the metal layer; 5) dry etching the exposed second portion of the top surface metal, such that the thickness of the second portion of the top surface metal is approximately equal to that of the second portion of the sidewall metal; 6) removing the exposed second portion of the top surface metal and the second portion of the sidewall metal using an isotropic etching process. This invention combines dry metal etching and isotropic etching techniques. By further adjusting the etching thickness ratio of dry metal etching and isotropic etching, the lateral corrosion of the metal layer at the cross-sectional position of the top surface of the stepped structure can be reduced, and the lateral corrosion size of the metal layer can be more controllable.

The application provides a semiconductor vertical field effect device preparation method, which comprises the following steps: S100, processing a wafer to form a vertical field effect device prototype with exposed gate part, performing isotropic etching on the exposed gate part to form a gate trench; S200, forming an oxide layer on the gate by oxidation growth; S300, filling metal in the gate trench to form a self-aligned word line; and S400, forming a drain on the upper part of the silicon surface of the wafer by epitaxial growth process. In the preparation process, the length and diameter of the transistor channel and the height and thickness of the gate word line can be accurately adjusted according to the requirement, meanwhile, the flatness of the bottom of the gate oxide layer and the bit line metal is better, so that the current can be adjusted and the leakage current can be reduced, and due to the overall integration of the bit line, the process flow is simplified and the preparation cost is reduced.

A semiconductor terminal structure and its formation method are disclosed. The method includes: forming a hard mask layer on the surface of an epitaxial layer, comprising a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer, wherein the hard mask layer has a plurality of first openings, the width of the plurality of first openings gradually decreasing along a first direction, or gradually decreasing and then remaining constant; forming a plurality of first doped regions in the epitaxial layer using the hard mask layer as a mask and employing a first doping process; etching the first hard mask layer using an isotropic etching process using the second hard mask layer as a mask, thereby exposing one end of the top surface of the main junction region; and forming a second doped region in the epitaxial layer using a second doping process using the first hard mask layer as a mask, wherein the second doped region and the first doped region have a partially overlapping region, and the doping concentration of the overlapping region is less than or equal to the doping concentration of the main junction region. This structure can effectively reduce the terminal's occupied area, improve the process window, and improve the terminal's breakdown voltage.

A method for producing a magnetic sensor. The method includes: arranging a first material having a first etch rate on a substrate to form a first layer; arranging a second material having a second etch rate on the first layer to form a second layer, the first etch rate being smaller than the second; arranging a third material on the second layer to form a third layer; structuring the third layer to create a structure having at least one open window in the third layer; etching, isotropically, the second layer through the at least one open window, as a result of which the third layer is undercut; after the through-etching of the second layer, the first layer is etched to create at least one inclined surface in the etched first layer, forming a magnetic sensing element on the at least one inclined surface of the first layer.

This invention discloses a laser-based pretreatment method for texturing monocrystalline silicon and its application. To address the problems of uncontrollable texture and poor uniformity in traditional alkaline texturing due to its reliance on anisotropic etching, and the complexity of existing laser-assisted texturing processes, the method includes: performing laser scanning pretreatment on the surface of the monocrystalline silicon wafer to be texturized, forming a uniform amorphous silicon layer with long-range disordered atomic arrangement on the wafer surface; then immersing the monocrystalline silicon wafer with the amorphous silicon layer into an alkaline etching solution for wet chemical etching, forming a nanoscale textured surface structure through isotropic etching. This invention uses a laser-induced amorphization layer as the etching starting point, eliminating the root cause of the traditional process's reliance on random defect nucleation, transforming the etching mechanism from anisotropic to isotropic, and obtaining a highly uniform nanoscale textured surface; simultaneously, the process requires only one laser pretreatment step and one wet etching step, significantly simplifying the process and making it suitable for texturing high-efficiency solar cells such as PERC, TOPCon, and HJT.

The application provides a manufacturing method of a semiconductor structure, and applies to the technical field of semiconductors. In the application, a first etching process is performed on an intergate dielectric layer of a peripheral device area by using an isotropic etching gas with a first selected ratio, so that after the first etching process is completed, only a small amount of oxide is left on the side surface of a floating gate layer, and no nitride is left; then, a second etching process is performed on the floating gate layer of the peripheral device area by using an etching gas with a second selected ratio, so that the floating gate layer, the oxide left in the intergate dielectric layer and the shallow trench isolation structure are partially removed, so that the oxide left in the intergate dielectric layer is completely exposed, and the shallow trench isolation forms a horn near the floating gate layer; finally, a third etching process is performed on the floating gate layer of the peripheral device area, the horn and the shallow trench isolation by using an isotropic etching gas with a third selected ratio, so that the horn is removed.

The application provides a method for improving polysilicon etching residue, which comprises the following steps: providing a substrate formed with a laminated structure, forming a filling groove on the laminated structure, forming a nitridation layer on the peripheral side of a control gate polysilicon layer and a hard mask layer during the formation of the filling groove; forming a polysilicon layer on the filling groove and the exposed surface of the laminated structure, and the polysilicon layer fills the filling groove; removing the polysilicon on the surface of the laminated structure; forming a photoresist pattern on the laminated structure, and exposing the surface area of the hard mask and the filling groove in a target area; performing anisotropic dry etching with the photoresist pattern as a mask, until the polysilicon in the filling groove in the target area is removed by 70%-80% of the thickness, and the hard mask in the target area remains a preset thickness; performing isotropic etching, and the remaining polysilicon is removed, and in the etching process, the remaining hard mask in the target area protects the control gate polysilicon below. The application can effectively avoid the residue of the polysilicon after the etching process.

The present invention relates to a semiconductor device manufacturing method, a substrate processing apparatus, and a recording medium. A technology capable of realizing isotropic etching while reducing the influence of plasma directivity is provided. The semiconductor device manufacturing method has a modification step of supplying a modification gas to modify a deposited film on a substrate on which no pattern is provided to form a modified film, and a modified film removal step of removing the modified film at a time point at which at least a plasma-activated removal gas and a protective film forming gas are supplied simultaneously.

A method of forming a semiconductor device includes: forming an opening in a dielectric layer to expose an underlying conductive feature; conformally forming a first protection layer and a second protection layer in the opening; performing an anisotropic etching to remove a first portion of the second protection layer from the bottom of the opening while keeping a second portion of the second protection layer along the sidewalls of the opening; after the anisotropic etching, performing an isotropic etching to remove, from the sidewalls of the opening, an upper portion and a lower portion of the first protection layer while keeping a middle portion of the first protection layer along the sidewalls of the opening; after the isotropic etching, performing an anneal to at least partially convert the second portion of the second protection layer into an oxide; and after the anneal, filling the opening with a conductive material.