130 results about "Isotropic etching" patented technology

The invention discloses a polycrystalline silicon etching method, which comprises the following steps of: firstly, carrying out a polycrystalline silicon etching process for the first time, and carrying out a certain amount of transverse etching; an isotropic dry etching process is adopted, so that the polycrystalline silicon has transverse etching. And then a polycrystalline silicon etching process with a high selection ratio is carried out, and an anisotropic etching process is adopted to ensure that the polycrystalline silicon on the surface is etched cleanly. According to the etching process, a step-by-step etching process method is adopted, the isotropic etching process is firstly carried out to control the etching amount of transverse etching, then the anisotropic etching method and the high-selectivity etching method are adopted to carry out etching of different etching amounts on areas with inconsistent feature sizes, and accurate etching of polycrystalline silicon is guaranteed.

A finFET device includes a doped source and / or drain extension disposed between a gate spacer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which an n-doped or p-doped source or drain extension is disposed. A doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate to the gate spacer. After forming the cavity, advanced process control (APC) (i.e., integrated metrology) is used to determine the recess distance without exposing the substrate to an oxidizing environment. The isotropic etch process, metrology, and selective epitaxial growth may be performed in the same stage.

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source / drain recess in a source / drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source / drain tip. A depth of the source / drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source / drain recess to the target depth. The source / drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source / drain recess is spaced a distance from a gate footing that can minimize DIBL. The source / drain recess is filled with an epitaxial semiconductor material.

The invention discloses a manufacturing method of a PNM IGBT. According to the method, a hard mask technology is adopted, and a multi-time etching technology combining anisotropic etching and isotropic etching is adopted. High-precision table top control is achieved in a low-cost mode, good production and manufacturing control can be achieved, and large-scale mass production is achieved. By means of the method, the feasibility of producing and manufacturing the PNM IGBT device is remarkably improved.

A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

Microfabrication process with the following steps: Providing a structure (800) comprising a layer stack (30, 40, 50) containing, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40), and a second silicon oxide layer (50), and a conductive material part (20) below the layer stack (30, 40, 50) and above a substrate (10); Producing a patterned etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Producing a via cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top side of the conductive material part (20) by isotropic etching of parts of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) with an isotropic etching process in which an etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30), wherein: the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical vapor deposition at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) comprises a second silicon oxide material produced by decomposition of tetraethyl orthosilicate.