94 results about "Isotropic etching" patented technology

The invention discloses a manufacturing method of a PNM IGBT. According to the method, a hard mask technology is adopted, and a multi-time etching technology combining anisotropic etching and isotropic etching is adopted. High-precision table top control is achieved in a low-cost mode, good production and manufacturing control can be achieved, and large-scale mass production is achieved. By means of the method, the feasibility of producing and manufacturing the PNM IGBT device is remarkably improved.

Microfabrication process with the following steps: Providing a structure (800) comprising a layer stack (30, 40, 50) containing, from bottom to top, a first silicon oxide layer (30), a stoichiometric silicon nitride layer (40), and a second silicon oxide layer (50), and a conductive material part (20) below the layer stack (30, 40, 50) and above a substrate (10); Producing a patterned etch mask layer (57) having an opening through this layer over the layer stack (30, 40, 50); and Producing a via cavity (59) extending through the layer stack (30, 40, 50) and downwards to a top side of the conductive material part (20) by isotropic etching of parts of the second silicon oxide layer (50), the silicon nitride layer (40) and the first silicon oxide layer (30) with an isotropic etching process in which an etch rate of the silicon nitride layer (40) is 1 / 10 to 1 / 2 of the etch rate of the first silicon oxide layer (30), wherein: the first silicon oxide layer (30) comprises a first silicon oxide material produced by decomposition of tetraethyl orthosilicate, the stoichiometric silicon nitride layer (40) is produced by chemical vapor deposition at a temperature of less than 300°C, in which a silicon precursor gas and a nitrogen precursor gas are used together to produce a silicon nitride material, and the second silicon oxide layer (50) comprises a second silicon oxide material produced by decomposition of tetraethyl orthosilicate.

The invention provides a flash memory and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and sequentially forming a gate oxide layer, a floating gate layer and a mask layer on the substrate; isotropic etching is carried out on the floating gate layer by taking the mask layer as a mask, so that the upper surface of the floating gate layer exposed out of the opening is arc-shaped; a spacer layer, a control gate, an offset layer and an HTO layer are sequentially formed on the side walls of the two sides of the opening of the mask layer; etching to remove the floating gate layer and the gate oxide layer between the HTO layers on the two sides to expose the substrate; forming a tunneling oxide layer, wherein the tunneling oxide layer at least covers the side wall surfaces of the offset layer and the floating gate and the exposed surface of the substrate; and forming a word line, wherein the word line fills the concave cavity region in the tunneling oxide layer. According to the invention, isotropic etching is carried out on the floating gate layer, so that the upper surface of the floating gate layer exposed by the opening is arc-shaped. And the coupling area of the arc-shaped surface of the floating gate and the control gate is increased, so that the coupling rate from the control gate to the floating gate layer is improved, and the coupling efficiency is improved.

Provided are semiconductor structures and methods for fabricating semiconductor structures. A method includes in a first device region and in a second device region: forming a stack of first epitaxial layers and second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form gaps; and depositing an interposer material over the bottom surface and in the gaps; in the first device region: performing an anisotropic etch of the interposer material located over the bottom surface; and in the first device region and in the second device region: performing an isotropic etch of the interposer material to remove the interposer material located over the bottom surface and to laterally recess the interposer material in the gaps.

The application relates to a silicon nanowire manufacturing method and belongs to the technical field of MEMS. The steps comprise the following: S1, providing an SOI substrate; S2, forming a mask layer on the SOI substrate; S3, patterning the mask layer to form an etching window; S4, performing isotropic etching on the SOI substrate through the etching window to form a cavity and a silicon nanocolumn; S5, oxidizing the silicon nanocolumn to form an oxide layer and a silicon nanowire; and S6, removing the buried oxygen layer and the oxide layer to obtain a suspended silicon nanowire. The application solves the problems of the prior art, such as complex preparation method of the silicon nanowire, high requirement for equipment and poor batch consistency.

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

Methods for manufacturing a large number of memory cells, including: Providing a substrate (99) that includes an access circuit for the plurality of memory cells and that has a contact surface (100) with an array of conductive contact plugs (120, 141) connected to the access circuit; Forming a layer of bottom electrode material (200) on the contact surface (100) of the substrate (99); Formation of mask structures (201, 202) on the layer of bottom electrode material (200); Preparing the mask structures (201, 202) on the layer of bottom electrode material (200) by isotropic etching of the mask structures (201, 202) to create a pattern of prepared mask structures (201A, 202A); Removal of material from the layer of bottom electrode material (200) by anisotropic etching using the prepared mask structures (201A, 202A) as an etch mask to form a pattern of electrode columns (210, 211) on corresponding conductive contact plugs (120, 141) in the field of conductive contact plugs (120, 141); Forming a layer of dielectric material (212) covering the pattern of electrode columns (210, 211) and exposed sections of the contact surface (100); Planarizing the layer of dielectric material (212) and the electrode columns (210, 211) to create an electrode surface in which one top surface (222, 223) of each electrode column (210, 211) in the pattern of electrode columns is exposed; Forming a layer of programmable resistive material (230) on the electrode surface; Forming a layer of top electrode material (231) over the layer of programmable resistive material (230); and Patterns of the layer of programmable resistive material (230) and the layer of top electrode material (231).

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source / drain (S / D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S / D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S / D recesses by the nitride layers and form ILD recesses.

According to one embodiment, a manufacturing method is to manufacture a display device in which a partition including a lower portion and an upper portion arranged on the lower portion to protrude from a side surface of the lower portion is arranged on a boundary between adjacent sub-pixels, and the method comprises forming a metal layer above a substrate, forming the upper portion on the metal layer, reducing a thickness of a first portion of the metal layer exposed from the upper portion by anisotropic etching, and forming the lower portion by reducing a width of a second portion of the metal layer located under the upper portion by isotropic etching.

The present disclosure provides a method of manufacturing a semiconductor structure having fins. The method includes providing a semiconductor substrate including a plurality of initial fin structures. The method also includes forming an isolation material covering the plurality of initial fin structures. The method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. The method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.

This invention relates to a method for etching away residual material on the side of a device, comprising: Step 1: preparing a substrate material, which is one of silicon-based materials, organic materials, or metallic materials; Step 2: fabricating a mask pattern on the surface of the substrate material using a mask material, which is one of metal, silicon oxide, silicon nitride, or photoresist, to obtain a sample to be processed; Step 3: if the sample to be processed does not have a preset pattern, depositing a target material on the surface of the sample and completing a secondary pattern transfer; if the sample to be processed contains a preset pattern, proceeding to Step 4; Step 4: etching the sample to be processed using an anisotropic etching method to perform preliminary etching on the areas to be etched; Step 5: continuing etching using an isotropic etching method to remove residual material on the side and in the pits of the sample to be processed. This invention can efficiently remove residual material on the side while reducing damage to the sample surface caused by etching.

A method of forming a portion of a gate all around field effect transistor (GAA FET) includes forming reserved locations in a recess formed in a portion of a substrate isolated by shallow trench isolation (STI), each reserved location interfacing with an extension region via a cap layer, the recess extending into an interlayer dielectric (ILD) formed on the substrate; selectively removing the reserved location relative to the substrate, the cap layer, and the STI; forming a selective cap layer at the bottom of the groove; performing a substrate removal process to perform isotropic etching on the substrate in the recess; performing a conformal deposition process to form spacer pads on exposed surfaces of the substrate and the selective cap layer within the recess; carving spacing pads on the side walls of the substrate and the STI in the groove; executing a cap layer removal process to remove the cap layer in the groove; and forming a metal contact in the groove.

The present invention relates to a frame used in a connector of a mask and a frame for OLED pixel formation and a method for manufacturing the same. The frame according to the present invention is used in a connector between a mask for OLED pixel formation and a frame, the frame comprising: an edge frame part having a hollow region; and a unit sheet part in which a plurality of mask unit regions are formed and which is connected to the edge frame part, the side surface shape of the mask unit regions and the side surface shape of the outer edge of the unit sheet part having a curved shape based on isotropic etching. The invention relates to a laminated body of a mask and a moving plate and a manufacturing method thereof.

A semiconductor manufacturing apparatus and a semiconductor manufacturing method are provided that can improve the bonding strength between materials by controlling a natural oxide film formed on the surface of a semiconductor material during the transport process of the semiconductor material. [Solution] This method includes a measurement process S1000 in which a first oxide film on the surface of semiconductor materials W1, W2 is measured; a stripping process S1300 in which the first oxide film is stripped and removed by isotropic etching or plasma etching based on the measurement results of the first oxide film; a transport process S1400 in which the semiconductor materials W1, W2 are transported in a predetermined environment; and a bonding process S1500 in which the semiconductor materials W1, W2 are plasma-treated to activate their surfaces, and then a high-vacuum state is created within a predetermined time period to polarize ions on the surfaces of the semiconductor materials W1, W2, and a high-frequency power source is applied to the semiconductor materials W1, W2, thereby removing the second oxide film formed on the surfaces of the semiconductor materials W1, W2 in the transport process S1400, and the ions move over the surfaces of the semiconductor materials W1, W2 to bond them.

After a silicon oxide film is formed on a main surface of a semiconductor substrate so as to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film with a photoresist pattern formed thereon used as an etching mask, and an anisotropic etching is further performed on the silicon oxide film. Accordingly, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining below the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

The present disclosure relates to a manufacturing method of a semiconductor device. After a silicon oxide film is formed on a main surface of a semiconductor substrate to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film using a photoresist pattern formed thereon as an etching mask, and then a further anisotropic etching is performed on the silicon oxide film. Thus, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining under the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.

The invention discloses a diamond micro-nano structure and a preparation method thereof, and relates to the technical field of material preparation. The method comprises the following steps: growing a diamond film on the surface of a pretreated base material; a metal mask layer corresponding to the micro-nano structure is formed on the surface of the diamond film through patterning treatment, and a first intermediate product is obtained; anisotropic etching treatment is carried out on the first intermediate product to remove the diamond film except the micro-nano structure, and a second intermediate product is obtained; performing secondary etching treatment on the second intermediate product to obtain a third intermediate product; carrying out isotropic etching treatment on a base material of the third intermediate product by adopting an etching solution to obtain a fourth intermediate product; and the fourth intermediate product is sequentially put into an acidic mixed solution and an alkaline solution to be treated, so that residual impurities in the fourth intermediate product are removed, and the diamond micro-nano structure is prepared. The invention aims to solve the problems that the edge of the micro-nano structure is burnt and the micro-nano structures with different styles and different sizes cannot be prepared on a large scale.

The invention provides an etching method of a semiconductor device and plasma etching equipment. The etching method comprises the following steps: providing the semiconductor device, wherein the surface of the semiconductor device is provided with a high dielectric constant material layer; a modification etching step: introducing a process gas containing a chlorine-based gas into the chamber, performing ionization by exciting radio frequency power to form plasma, and performing isotropic modification etching on the high dielectric constant material layer to form a modified layer; and a cleaning step: introducing process gas containing inert gas and chlorine-based gas into the chamber, ionizing by exciting radio-frequency power to form plasma, and performing isotropic etching to remove the modified layer until the high-dielectric-constant material layer is exposed. Taking the high dielectric constant material layer as the hafnium oxide layer as an example, isotropic modification etching of the hafnium oxide layer can be realized to form the modified layer, and isotropic etching removal of the modified layer can be realized, so that the stability of the dielectric property of the hafnium oxide layer can be maintained.

A manufacturing method of a semiconductor structure including the following steps is disclosed. A definition layer is formed on a substrate. The definition layer includes a first dielectric layer and a second dielectric layer. A first isotropic etching process is performed on the second dielectric layer to form a first opening in the second dielectric layer. A portion of the first opening is located under the patterned photoresist layer. A first anisotropic etching process is performed on the first dielectric layer to form a second opening in the first dielectric layer. The first opening is connected to the second opening to form a third opening. The patterned photoresist layer is removed. An etch back process is performed on the first dielectric layer and the second dielectric layer, so that a sidewall of the definition layer exposed by the third opening is an inclined surface.

The present disclosure provides a fixed-position defect doping method for a micro-nanostructure based on a self-alignment process, including: S1, sequentially forming a sacrificial layer and a photoresist layer on a surface of a crystal substrate; S2, performing a lithography on the photoresist layer to form a mask hole according to a micro-nano pattern; S3, performing an isotropic etching on the sacrificial layer through the mask hole, and amplifying the micro-nano pattern to the sacrificial layer; S4, performing an ion implantation doping on an exposed crystal surface below the mask hole; S5, removing the photoresist layer, and depositing a mask material; S6, removing the sacrificial layer, and transferring a micro-nano amplified pattern in the sacrificial layer to a mask material pattern; and S7, etching an exposed crystal surface, and removing the mask material on the surface and forming a specific defect by annealing.

A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

A method of forming a portion of a gate all around field effect transistor includes performing a selective deposition process to form a selective capping layer at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolation (STI), where the contact trenches each interface with an S / D epitaxial (epi) layer through an extension region, the method includes performing a contact trench on a substrate, performing a substrate angled etch process to etch sidewalls of the contact trench, enlarging a top critical dimension (CD) of the contact trench, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trench, performing a recess filling process to fill the contact trench with a dielectric layer, and performing a trench etching process to isotropically etch the substrate within the contact trench. In one embodiment, an inter-layer dielectric (ILD) recess process is performed to partially remove the substrate between the dielectric layers within the contact trench and form an ILD recess, and a substrate isotropic etch process is performed to partially remove the substrate within the ILD recess.

This invention provides a method for fabricating a stepped metal structure and a silicon photonic device, comprising: 1) forming a stepped structure on a substrate; 2) depositing an isolation dielectric layer on the stepped structure; 3) depositing a metal layer, wherein the thickness of the top surface metal is greater than the thickness of the sidewall metal; 4) forming a pattern barrier layer on the metal layer; 5) dry etching the exposed second portion of the top surface metal, such that the thickness of the second portion of the top surface metal is approximately equal to that of the second portion of the sidewall metal; 6) removing the exposed second portion of the top surface metal and the second portion of the sidewall metal using an isotropic etching process. This invention combines dry metal etching and isotropic etching techniques. By further adjusting the etching thickness ratio of dry metal etching and isotropic etching, the lateral corrosion of the metal layer at the cross-sectional position of the top surface of the stepped structure can be reduced, and the lateral corrosion size of the metal layer can be more controllable.

The application provides a semiconductor vertical field effect device preparation method, which comprises the following steps: S100, processing a wafer to form a vertical field effect device prototype with exposed gate part, performing isotropic etching on the exposed gate part to form a gate trench; S200, forming an oxide layer on the gate by oxidation growth; S300, filling metal in the gate trench to form a self-aligned word line; and S400, forming a drain on the upper part of the silicon surface of the wafer by epitaxial growth process. In the preparation process, the length and diameter of the transistor channel and the height and thickness of the gate word line can be accurately adjusted according to the requirement, meanwhile, the flatness of the bottom of the gate oxide layer and the bit line metal is better, so that the current can be adjusted and the leakage current can be reduced, and due to the overall integration of the bit line, the process flow is simplified and the preparation cost is reduced.

The invention discloses a preparation method of an advanced node-oriented semiconductor structure and the semiconductor structure, relates to the technical field of semiconductor preparation, and aims to solve the problems of tedious preparation process and deteriorated structure pattern edge quality when the advanced node-oriented semiconductor structure is prepared in the prior art. The method comprises the following steps: forming a lamination layer on a bottom layer structure; forming an initial pattern on the surface of the mask layer, transferring the initial pattern to the mask layer and the target layer, and forming an initial structured pattern of the target layer, which is consistent with the initial pattern in size, on the target layer; performing isotropic etching on the initial structured graph of the target layer by adopting a remote plasma etching machine, and reducing the initial structured graph of the target layer into a graph with a target size; wherein the ratio of the etching rate of the target layer to the etching rate of the stop layer is greater than or equal to a preset ratio; and finally forming a target semiconductor structure. The method is used for improving the preparation efficiency and the pattern quality of the semiconductor structure facing the advanced node.

The invention provides a space-time shaping ultrafast laser high-precision hard and brittle material machining method and device, and belongs to the technical field of laser precision manufacturing. The method comprises the following steps of: splitting a single ultrafast laser pulse into double sub-pulse sequences which are orthogonal in space and have controllable time delay; by accurately regulating and controlling the energy and time delay of the double pulses and the change of the double pulses in the machining depth direction, material modification only occurs in an overlapping area of the double pulses, and modification strength distribution with gradient decreasing from inside to outside is formed; and in combination with selective chemical etching, the influence of isotropic etching is counteracted by utilizing the gradient difference of the etching rate. According to the method, the problems of poor axial resolution, low process controllability and etching morphology distortion in large-depth and high-precision three-dimensional microstructure processing are effectively solved, and the preparation of the nanoscale-precision and high-fidelity complex three-dimensional microstructure on hard and brittle materials such as quartz glass can be realized.

A method for fabricating a semiconductor device includes forming an active pattern on a substrate, forming sacrificial and semiconductor layers alternately stacked on the active pattern, forming a dummy gate and first source / drain trench on one side of the dummy gate by etching the stacked structure, forming a second source / drain trench on the active pattern by etching a sidewall of the sacrificial layer exposed to the first source / drain trench, forming a first inner spacer material layer along sidewall and bottom surfaces of the second source / drain trench, forming a second inner spacer material layer by anisotropic etching a first inner spacer material layer, and forming a third source / drain trench on the active pattern by isotropic etching.

The invention belongs to the technical field of pressure sensors, and particularly relates to a preparation method of a high-temperature pressure sensor. Comprising the following steps: providing an N-type monocrystalline silicon wafer as a substrate; anisotropic etching is carried out on the substrate to form a deep groove I for isolating the two sides of the piezoresistor body; performing isotropic etching on the basis of the deep groove I to form a deep groove II for isolating the bottom area of the piezoresistor body; filling the deep groove I and the deep groove II with an insulating medium, and performing chemical mechanical polishing and leveling treatment on the redundant insulating medium on the surface of the substrate; anisotropic etching is carried out on the substrate again so as to form a deep groove III for isolating the two ends of the piezoresistor body; filling the deep groove III with an insulating medium, and performing chemical mechanical polishing and leveling treatment on the redundant insulating medium on the surface of the substrate; according to the invention, all-dielectric isolation filling is carried out twice to form a physically isolated piezoresistor body, so that the defect of high-temperature electric leakage of PN isolation is avoided, and the cost of an SOI scheme is reduced.

Trenching in a Substrate This description relates to a process comprising the following steps: a) providing a structure comprising a semiconductor substrate (11), and, on the side of a first face (11B) of the substrate, at least one first trench (15) filled with an insulating material, extending vertically in the substrate; b) forming, by anisotropic etching from a second face (11T) of the semiconductor substrate opposite the first face (11B), at least one second trench (13) extending vertically in the substrate and opening onto said at least one first trench (15); and c) widening said at least one second trench (13) by isotropic etching. Figure for the abstract: Fig. 2B