298 results about "Active devices" patented technology

A computing system and method are disclosed for converting network configurations across different platforms using a language model. This system preprocesses a source network configuration from a first network platform, generates a prompt based on the preprocessed source network configuration and additional network data for input to the language model. In response to the prompt, the language model converts the source network configuration into a target network configuration for a second platform, ensuring that common configuration elements are preserved while unsupported protocols are adapted to supported alternatives on the second network platform. The system outputs the converted configuration, facilitating seamless network migration with minimal, or no, manual intervention. Additional features include the ability to receive and process active device states and network diagrams, suggesting alternative solutions for unsupported protocols, validating the target configuration against the second platform's specifications, and interacting with users to refine the conversion based on their input.

The present application provides a chiplet, a chip module, an electronic device, and a manufacturing method for a chiplet. The chiplet comprises a substrate, an active device, and a passive device. The active device is arranged on a first side of the substrate, the passive device is arranged on a second side of the substrate, and the orthographic projection of the active device on the substrate at least partially overlaps with the orthographic projection of the passive device on the substrate, thereby reducing the sum of the projection areas occupied by the two devices. The chiplet further comprises conductive holes, and the conductive holes include a first conductive hole. The active device comprises a first connecting piece, and the first connecting piece covers one end surface of the first conductive hole and is electrically connected to the first conductive hole; the passive device comprises a second connecting piece, and the second connecting piece covers the other end surface of the first conductive hole and is electrically connected to the first conductive hole. In this way, the first conductive hole is connected to the active device and the passive device. The miniaturization of the chiplet is improved, and thus, the mounting area of the chip module is reduced, the integration level of the electronic device is improved, and the reliability of the connections between the conductive holes and the devices is high.

The invention discloses a wafer-level heat dissipation structure and a manufacturing method. The wafer-level heat dissipation structure comprises a heat dissipation substrate, a device wafer and a bonding layer, the heat dissipation substrate is a first silicon wafer with a diamond layer growing on the lower surface, and the upper surface of the heat dissipation substrate is plated with a first copper layer; the device wafer is a second silicon wafer of which the upper surface is integrated with an active device, and the lower surface is plated with a second copper layer; the bonding layer is composed of a Cu-Cu bonding interface formed by the first copper layer and the second copper layer through thermocompression bonding. The method comprises the following steps: growing a diamond layer on the lower surface of a first silicon wafer through MPCVD, and sputtering a Cu layer after the upper surface is thinned; sputtering a Cu layer on the back surface of the second silicon wafer of which the surface is integrated with the active device; and finally realizing interconnection of the Cu layers of the two wafers through thermocompression bonding. The problem of multi-interface thermal resistance caused by a traditional thermal interface material is avoided, an ultra-low thermal resistance path from a chip junction to a diamond heat dissipation surface is constructed, and the method is particularly suitable for thermal management of a high-power-density semiconductor device.

This invention provides an interlayer film for sandwich photoactive devices and a sandwich photoactive device. The interlayer film for sandwich photoactive devices has the following characteristics: after heat treatment at 90-140℃ for 30-240 minutes, the shear viscosity is 7000-12000 Pa·s at 90℃ and a shear rate of 20 / s, and 5000-9000 Pa·s at 110℃ and a shear rate of 20 / s. The interlayer film provided by this invention has good adhesion and can effectively solve the problem of delamination in sandwich photoactive devices.

The utility model provides a microwave receiving module, which relates to the technical field of signal processing, and comprises a VGC control temperature compensation circuit, the VGC control temperature compensation circuit comprises a voltage-controlled amplifier and a temperature sensor, and the input end and the output end of the voltage-controlled amplifier are respectively connected with an amplitude-limiting low-noise amplification filter circuit and a noise control circuit. The power supply end of the voltage-controlled amplifier is connected with the voltage conversion circuit, and the temperature sensor is connected with the control voltage input end of the voltage-controlled amplifier through the signal processing circuit. The problem of gain fluctuation caused by electrical characteristic change of active devices such as a transistor and an amplifier chip in the VGC amplification control circuit due to temperature change is effectively solved, the control voltage of the voltage-controlled amplifier is dynamically adjusted, and the voltage-controlled amplifier can stably work at different temperatures; therefore, the gain stability of the whole microwave receiving module is improved, and the signal amplification effect is improved.

The present disclosure relates to IC structures including a porous semiconductor layer located beneath a channel isolation proximate to a source / drain region. An integrated circuit (IC) structure includes an active device located above a bulk semiconductor substrate, and an isolation structure in the bulk semiconductor substrate surrounding the active device. The active device includes a semiconductor layer having a central region, a first end region laterally spaced apart from the central region by a first trench isolation, a second end region laterally spaced apart from the central region by a second trench, a gate located above the central region, and a source / drain region located in each of the first and second end regions. The isolation structure includes a polysilicon isolation layer located beneath the active device, a third trench isolation surrounding the active device, and a porous semiconductor layer located between the first trench isolation and the polysilicon isolation layer and between the second trench isolation and the polysilicon isolation layer.

The application relates to the technical field of switching power supply, and discloses a bridge type low-stress passive soft switching boost power factor correction circuit, which comprises a direct current input power supply, a main power switching tube, an output filter capacitor and a coupling inductor comprising a primary side and a secondary side; a passive soft switching buffer network is connected to a main circuit of the circuit, the network comprises a diode full-bridge structure and a buffer capacitor, and the leakage inductance of the secondary side of the coupling inductor is connected between the midpoints of two bridge arms of the full-bridge structure; the application utilizes the ratio difference of the coupling inductor to generate a forward potential difference, drives the buffer capacitor to reversely charge to establish a negative voltage, and further provides a discharge circuit for the parasitic junction capacitance of the main power switching tube, so that zero voltage turn-on is realized, and high-frequency switching loss is reduced; meanwhile, the highest voltage stress of the semiconductor device is clamped in the range of the direct current output voltage through the potential restriction of the full-bridge network. The application does not need auxiliary active devices, and improves conversion efficiency and reliability while simplifying the system structure.

The invention relates to a converter circuit and electronic equipment. The converter circuit comprises an active clamping circuit, a control circuit and a voltage stabilizing circuit, active devices in the active clamping circuit are controlled through the active clamping circuit to realize soft switching, that is, a first switching tube and a second switching tube are controlled to realize soft switching, so that the conduction loss of the first switching tube and the second switching tube is reduced, and the switching efficiency is improved. The problem that large loss is caused when the PFC converter works at high frequency due to the fact that an existing passive clamping circuit cannot achieve soft switching is solved.

The invention discloses a phase offset configuration method based on a device unique identifier RCA, and belongs to the technical field of storage device management. Comprising the following steps: S1, a host activates all connected eMMC equipment through a standard eMMC initialization command; s2, the host allocates a unique relative device address RCAi for each eMMC device; s3, the host counts the total number n of the currently active devices; s4, calculating a phase deviation angle delta phi i for each eMMC device based on the relative device address RCAi and the total number n of the devices; s5, the host writes the phase deviation angle delta phi i into an extension register of each eMMC device through an extension register configuration command; and S6, the host activates the phase deviation of the target device, and data transmission is carried out in a specified phase window, so that each eMMC device only drives the data bus in the exclusive time slot corresponding to the phase deviation angle delta phi i of the eMMC device. Through innovative combination of protocol layer dynamic configuration and physical layer time isolation, the problems of signal conflict, delay and power consumption in a multi-eMMC equipment system are thoroughly solved.

The application provides a precise simplification method and system of a passive parasitic parameter network. The method comprises the following steps: obtaining a passive parameter parasitic network of a to-be-processed circuit; obtaining device information of all parasitic parameters; labeling node names of active device ports according to an active device naming rule; if a current parasitic parameter crosses multiple active device ports, deleting the current parasitic parameter; if a branch where the current parasitic parameter is located is an open circuit, deleting the branch and the parasitic parameters thereon; after traversing all parasitic parameters, obtaining a precise passive parasitic parameter network; and performing order reduction processing on the precise passive parasitic parameter network to obtain a simplified passive parasitic parameter network. The method precisely processes the passive parasitic parameter network, excludes active device ports and invalid ports, so that the passive parasitic parameter network can be correctly processed during simplification and order reduction processing, and the efficiency and accuracy of the order reduction and simplification processing are improved due to the exclusion of invalid paths.

A communication method comprises the following steps: a microstrip line transmits a first radio frequency signal from an active device to an oscillator, and couples a second radio frequency signal and a third radio frequency signal transmitted by the oscillator to a waveguide; the second radio frequency signal is a part of radio frequency signal transmitted to the oscillator; the third radio-frequency signal is a radio-frequency signal reflected by a capacitor composed of the polar plate and the grounding plate; the communication method is used for the transmission band line waveguide connector. The transmission band line waveguide connector comprises a transmission band line, a dielectric substrate and a grounding plate. The transmission band line is located on the first surface of the dielectric substrate, and the grounding plate is located on the second surface of the dielectric substrate; the grounding plate is provided with a gap which is used for coupling with the waveguide. The transmission band line comprises a microstrip line, a pole plate and an array coupled with the gap; wherein one end of the microstrip line is connected with the polar plate, the other end is connected with an active device, and the oscillator is located between the two ends of the microstrip line and connected with the microstrip line; the pole plate is connected with the direct current feed end, and the pole plate is coupled with the grounding plate.

The application provides a multi-terminal interconnection method, system, electronic device and storage medium, priority of each wireless communication device is preset, and a role state containing independent, central and peripheral three states is initialized, a dynamic self-organizing mechanism taking priority as the only decision basis is constructed. When a first device in the independent state discovers a second device through a device discovery process, priority comparison is triggered: if the first device has higher priority, the first device is switched from the independent state to the central device state after actively establishing a connection, and the second device is assigned to enter the peripheral device state and stop the active device discovery process. The first device in the central device state continuously performs device discovery, actively discovers and connects all other devices with lower priority, and automatically constructs a star-shaped topology network with itself as the center. By completely giving the connection decision-making right to the high-priority device, the network topology from disorder to order is determined to converge.

Aspects of the present application relate to mobile communication devices having active device components and passive device components and, more particularly, to operation of the passive device components to form a backscatter signal from a received forward signal. Forming the backscatter signal may include generating the backscatter signal from the received forward signal without decoding a plurality of sub-signals in the received forward signal, the backscatter signal being a time-domain function of a contiguous subset of the time-domain plurality of sub-signals in the received forward signal. Upon receipt of the backscatter signal, a reception point may obtain information about the mobile communication device that contains the passive device components. Such information may relate to timing, position and identity.

A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source / drain region of one of the second FETs, or connected to a front side signal line and a source / drain region of one of the first FETs.

A circuit board assembly for a pluggable module includes upper and lower interface printed circuit boards that includes first and second data channels, respectively. The interface printed circuit boards includes mating pads at corresponding mating edges thereof forming portions of the data channels and configured to be plugged into corresponding card edge connectors. The circuit board assembly includes a main printed circuit board that includes an active device electrically connected to the first and second data channels restoring signals transmitting along the data channels. The circuit board assembly includes upper and lower flexible circuits connected between the interface printed circuit boards and the main printed circuit board.

The application relates to the technical field of power electronic converter control, and provides a three-port flyback DC-AC converter, characterized in that the three-port flyback DC-AC converter comprises a flyback circuit, a power frequency reverse bridge, an AC-DC converter and a CL filter which are sequentially connected in cascade; the AC-DC converter is an AC-DC three-winding flyback converter which can realize power factor correction function, and is realized through active device multiplexing and magnetic component multiplexing, and comprises a flyback transformer T 2, excitation inductance L f , output switch Q 3, Q 4; the modulation method is to calculate instantaneous output power P o , judge the operation mode of the system, and respectively perform active modulation, reactive modulation or mixed modulation, so that the power factor is adjusted through the modulation method.

A display substrate is provided to include a base substrate and: a first transistor layer including a first active layer and a second transistor layer including a second active layer sequentially along a direction away from the base substrate; the first and second active layers are provided with at least one insulating layer therebetween, and are made of low-temperature polysilicon materials; the first active layer includes first channel region(s) and first source-drain doped region(s); the second active layer includes second channel region(s) and second source-drain doped region(s); orthographic projections of a second source-drain doped region and a first source-drain doped region on the base substrate overlap with each other; and a second source-drain doped region is connected to a first source-drain doped region through a connecting part filled in a corresponding first via in the insulating layer. A method for manufacturing a display substrate and a display apparatus are provided.

Various implementations related to the use of nanosheet transistors formed on a substrate are disclosed. A nanosheet transistor includes an active region with a width that defines an active device width for the transistor. Hybrid cell structures are disclosed that include varying cell heights (e.g., tall and short cells) aligned with fixed width power grid routes. The fixed width of the power grid routes provides spacings for variations of signal route spacing between the power grid routes depending on the size of the underlying cell. These structures provide flexibility for tall to short cell ratios on a partition level in logic blocks.

The embodiment of the application relates to the technical field of optical equipment, and discloses an optical module and a manufacturing method of the optical module, the optical module comprising: a substrate; an active device arranged on the substrate, the active device being used for emitting and / or receiving a light beam; an optical element arranged on the active device in a covering mode; a support arranged on the substrate and surrounding the active device, the support being formed by injection molding; and a lens assembly arranged in a light path direction of the active device and fixedly connected with the support, the lens assembly being used for allowing the light beam to pass through, and an air gap existing between the lens assembly and the optical element. In the manner, the performance of the optical module can be ensured to be not affected.

An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

A semiconductor structure includes a first semiconductor chip having a surface with a plurality of conductive features thereon; a second semiconductor chip having a surface with a plurality of conductive features thereon; and a bridge chip coupling the first and second semiconductor chips through the pluralities of conductive features. The bridge chip includes a first surface facing the surfaces of the first and second chips with the conductive features thereon. The bridge chip has a second surface, a BEOL coupled to conductive features on the first surface that are in turn coupled to the pluralities of conductive features, an active device layer having a plurality of devices below the BEOL, a MOL layer in between the active device layer and the BEOL, and a backside power distribution network (BSPDN) below the active layer and coupled to devices on the active layer of the bridge chip.

The invention relates to a manufacturing method of a power amplifier for improving power back-off efficiency, which belongs to the technical field of radio frequency microwave circuits, and comprises the following steps: step 1, based on load characteristics of an active device, determining an optimal efficiency impedance point under linear output power as optimal impedance of amplifier design; step 2, pulling out the determined optimal impedance by using a load pulling technology or LOADPULL, and drawing the optimal impedance on an SMITH original drawing; 3, based on the optimal impedance obtained through traction, low-loss impedance matching is achieved through the equal Q matching technology, loss and bandwidth are compatible, and impedance change and frequency band shaping are completed; 4, a two-stage or multi-stage amplification structure is adopted, and nonlinear compensation is realized by controlling grid voltages of front-stage and back-stage active devices and utilizing front-stage and back-stage gain compression and expansion characteristics; the method has the beneficial effects that the linear output power optimal efficiency impedance point is selected as the optimal impedance of the amplifier design, and the amplifier maintains higher linear output power and has higher rollback efficiency.

A chip includes an active device, a first backside silicon layer disposed below the active device, a first backside metal path electrically coupled to the active device and extending through the first backside silicon layer, and a first electrical barrier disposed between one or more sides of the first backside metal path and the first backside silicon layer.

Methods, systems, and devices for wireless communications are described for low noise amplifier (LNA) configurations of a user equipment (UE) operating in a dual-subscriber dual-active (DSDA) mode. The UE may establish first and second communications links via two or more antenna ports using a first subscriber identity module (SIM) and a second SIM in the DSDA mode. The UE may identify a LNA configuration from two or more available LNA configurations for receiving at least partially concurrent communications of the first SIM and the second SIM based at least in part on activation of the DSDA mode and a difference between a first received signal strength associated with the first SIM and a second received signal strength associated with the second SIM. The UE may receive the at least partially concurrent communications via the two or more antenna ports based at least in part on the identified LNA configuration.

The present disclosure relates in an aspect to an integrated circuit device. The integrated circuit device comprises an active device tier and a frontside interconnect structure arranged at a frontside of the active device tier and a backside interconnect structure arranged at a backside of the active device tier. The integrated circuit device comprises a plurality of circuit blocks, and a data communication circuit configured to transfer data between the plurality of circuit circuit blocks. The data communication circuit comprises a plurality of switching circuits. Each circuit circuit block is connected to the data communication circuit by a switching circuit. The data communication circuit further comprises a plurality of data communication channels interconnecting the plurality of switching circuits and comprising a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

The application provides a mixing circuit, a transmitter and a communication device. The mixing circuit comprises an I-channel digital-to-analog converter, a Q-channel digital-to-analog converter, a low-pass filter and a passive quadrature mixer; the low-pass filter comprises an active device, so that the output admittance of the mixing circuit has a frequency-dependent conductance. The consistency of the upper sideband and lower sideband gains of the mixing circuit is improved.

A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

The present disclosure provides a heat spreading isolation structure for a semiconductor device. A structure includes an active device over a region of a substrate and a heat spreading isolation structure adjacent to the active device. The isolation structure includes a dielectric layer over a thermally conductive layer. The thermally conductive layer can include polycrystalline graphite. The thermally conductive layer provides a heat spreader that provides a high thermal conduction path with low electrical conduction. The thermally conductive layer can extend into the substrate. The substrate can include an SOI substrate, in which case the thermally conductive layer can extend through the buried insulator thereof.

A semiconductor structure and a method for forming the same, the structure comprising: a first chip; a second chip; a transition plate between the first chip and the second chip, the transition plate electrically connecting the first chip and the second chip, the transition plate having an active device therein, the active device being used to realize a function after the first chip and the second chip are connected. The difficulty of stack integration of the semiconductor structure is reduced.

This invention discloses a linked structure cavity for improving the SPL (Surface Placement) of musical glass, comprising an active device, a microwave cavity, a linked nano-cushion, and a metasurface crystal layer. The active device is disposed on the original glass, and a metasurface crystal layer is horizontally disposed on its end face away from the original glass. A ring-shaped microwave cavity is disposed between the metasurface crystal layer and the original glass, relative to the outside of the active device. The microwave cavity is spaced around the active device and forms a circular region with the metasurface crystal layer and the original glass. A linked nano-cushion is disposed between the metasurface crystal layer and the active device, and the linked nano-cushion and the microwave cavity are configured to not interfere with each other. This multi-dimensional combination of the linked nano-cushion, the microwave cavity, and the metasurface crystal layer forms a strong coupled planar sound field, improving the SPL value of the musical glass. This invention improves the SPL value of musical glass through the multi-dimensional combination of the microwave cavity, the linked nano-cushion, and the metasurface crystal layer.