1182 results about "Active devices" patented technology

System, devices and methods are presented that integrate stretchable or flexible circuitry, including arrays of active devices for enhanced sensing, diagnostic, and therapeutic capabilities. The invention enables conformal sensing contact with tissues of interest, such as the inner wall of a lumen, a the brain, or the surface of the heart. Such direct, conformal contact increases accuracy of measurement and delivery of therapy. Further, the invention enables the incorporation of both sensing and therapeutic devices on the same substrate allowing for faster treatment of diseased tissue and fewer devices to perform the same procedure.

Enables multiple devices of a same user to logon automatically. An example of a method includes: registering the user and the user's multiple user devices with a Multiple Device Authentication (MDA) apparatus; authenticating at least one of the user's registered devices by the MDA apparatus and selecting the authenticated device as a master device; selecting one or more slave devices from the registered user devices; adding the selected master device and one or more selected slave devices to an active device table; if a user device accessing the MDA apparatus is in the active device table, causing the user device logon directly and automatically without first authenticating the user device. Operation of authentication is needed only once to enable user's multiple devices to logon the server automatically and conveniently. Seamless switch between different devices can be implemented, resulting in improved single-sign-on solution over the prior art.

System, devices and methods are presented that integrate stretchable or flexible circuitry, including arrays of active devices for enhanced sensing, diagnostic, and therapeutic capabilities. The invention enables conformal sensing contact with tissues of interest, such as the inner wall of a lumen, a the brain, or the surface of the heart. Such direct, conformal contact increases accuracy of measurement and delivery of therapy. Further, the invention enables the incorporation of both sensing and therapeutic devices on the same substrate allowing for faster treatment of diseased tissue and fewer devices to perform the same procedure.

A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts. By forming a shared contact opening spanning two dice, the backside contact is formed around the die edge and the backside surface area necessary for the contact opening is minimized. The backside contact allows direct placement of the integrated circuit die on contacts within the packaging, such as a ball grid array, eliminating the need for wire bonds. The need for a pad etch through passivation material overlying active devices on the front side of the die is also eliminated, and no mask levels are added for the devices formed on the front side.

An electro-optical device is disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer) having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wiring for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits are constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized in that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.

An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.

An active device provides protection from the sun or other bright light source for improved vision, using a variable opacity medium that is electronically controlled to cast a shadow on an eye of a user and/or to otherwise reduce the amount of the light incident on the eye, thereby reducing glare. Miniature cameras monitor the user's eye movements and the scene in front of the user. If a bright light is detected, one or more dark spots is created in the variable opacity medium that acts as a shade or light filter for a pupil of the eye. The variable opacity medium, cameras, and associated electronics can be used in connection with eyeglasses (including sunglasses), as part of a device worn by the user (such as a helmet), a windshield, mirror, or other optical element having a view port through which light can be seen by the user.

A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

A circuit for matching the impedance of an output load to an active device includes a transformer including a first winding having a terminal for coupling to the output of the active device and a second winding electromagnetically coupled to the first winding, and a plurality of taps, each of the plurality of taps having a first end coupled to a position on the second winding corresponding to a ratio of the second winding to first winding differing from other ones of the plurality of taps, and a second end. The matching circuit further includes a plurality of MEMS switches each having a control input for receiving a corresponding control signal, a first terminal coupled to the second end of a corresponding one of the plurality of taps, and a switched output selectively coupled to a matching junction in response to the corresponding control signal.

Disclosed herein are apparatus and methods for measuring error associated with the rotation of bearings (50) used within a pointing device (11) on board a space-based platform. The apparatus includes inductive, or “eddy current,” proximity sensors (1000) adapted for measuring the positioning of bearing components. The apparatus also includes processing capabilities (1010) for receiving data from the proximity sensors (1000), and producing compensation data. The compensation data is used in one of various techniques for correcting errors in the angular measurement or pointing of the device (11). The techniques disclosed herein include conducting an initial calibration of the proximity sensors (1000) and generating calibration data. Once in active use, sensor measurements are combined with calibration data to produce compensation data. Ongoing measurements may be used to update the calibration data as necessary.

Described is a computer-implemented system and method that dynamically detects which input device (e.g., pen or mouse) is currently in use, and based on the device, varies a program's user interaction model to better optimize the user's ability to interact with the program via that input device. A tablet input subsystem receives pen and touch data, and also obtains keyboard and mouse data. The subsystem analyzes the data and determines which input device is currently active. The active device is mapped to an interaction model, whereby different user interface appearances, behaviors and the like may be presented to the user to facilitate improved interaction. For example, a program may change the size of user interface elements to enable the user to more accurately scroll and make selections. Timing, tolerances and thresholds may change. Pen hovering can become active, and interaction events received at the same location can be handled differently.

A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.

A touch sensing apparatus for receiving input from one or more touch stimulating devices employs a direct sequence spread spectrum (DSSS) signaling arrangement to transmit signals from the touch stimulating devices for identification and location determination. Active devices are powered by an EM field and generate a touch stimulating signal that is spread spectrum encoded for identification, and signal pickups in a propagation layer receive the touch stimulation signals which are identified by the DSSS encoding and located using received signal strength (RSS) techniques. Semi-active devices are powered by an EM field and receive code instructions to generate specific spread spectrum signals and generate a touch-stimulating signal. Touch stimulating devices are either tethered or tether-free, and powered by batteries or EM fields.

3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.

An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.

The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

A switched-mode Class F power amplifier is provided for parallel connection with at least one other like amplifier, within a Chireix architecture, for combining the signals output therefrom. An input component includes at least one active device configured to be alternately switched by a signal input thereto to present an amplified signal corresponding to the input signal and constituting a low output impedance voltage source. A lumped element impedance inverter is provided between the input component and an output resonator component, the impedance inverter being configured for transforming the low output impedance voltage source to instead constitute a high output impedance current source configured for said parallel connection. In accordance with the invention, the negative reactive component values required by the impedance inverter are eliminated and effectively provided by incorporating those values into pre-selected reactive components of the input and output components. Further, a source-drain parasitic capacitance across the active device is eliminated by one or more pre-selected reactive components of the input component, the value(s) of which effectively compensate for the parasitic capacitance.

The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

Microelectromechanical RF and microwave frequency power limiter and electrostatic protection devices for use in high-speed circuits are presented. The devices utilize an airbridge or a cantilever arm including a contact pad positioned operatively adjacent to an electrically conductive and substantially planar transmission line. When the power level in the transmission line exceeds a particular threshold, the airbridge or cantilever arm yields due to force between the contact pad and the transmission line, directing undesired power away from active devices. This characteristic can either serve as a method by which to limit the amount of power passing through the transmission line to a determined value or as a method by which to protect devices along the transmission line from damage due to large electrostatic bursts.

This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying at lease the top surface region of the switching element such that the conductive material is in direct contact with the switching element. The side wall spacer reduces a contact area for the switching element and the conductive material and thus a reduced active device area for the switching device. In a specific embodiment, the reduced area provides for an increase in device ON/OFF current ratio.

The invention relates to an active device having variable energy/light transmission properties (100) comprising an active system (1, 12) between a protective substrate (2) and a protective cover (3), selected from an essentially inorganic electrochromic system, a light valve system, a liquid crystal system, a gasochromic system, a thermochromic system, means leakproof to liquid water and/or water vapor, a surround (50) made from at least one metal based part (5a, 5b) on the periphery of the device, the surround being assembled with the cover and with the substrate by assembling means (61′ to 64′) forming at least part of the means leakproof to water vapor.

An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

An active matrix LED display apparatus and a fabrication method thereof are provided. The active matrix LED display apparatus enables to miniaturize pixel by a formation of wiring on bottom layer and an assembly of each block through each eutectic layer into each transistor block receptor and/or each LED block receptor formed according to each color element unit, and to be embodied with high luminance, low power consumption, high reliability and superior optical property by assembling a transistor block having high electron mobility. And the fabricating method of the present invention enables to make efficiently an AM-LED display apparatus at room temperature in a short time by using different shapes of receptor and block depending on the function of a transistor and/or on the color of an LED.

Optoelectronic devices, such as light-emitting diodes, laser diodes, image sensors, optical detectors, etc., made by depositing (growing) one or more epitaxial semiconductor layers on a monocrystalline lamellar/layered substrate so that each layer has a wurtzite crystal structure. In some embodiments, the layers are deposited and then one or more lamellas of the starting substrate are removed from the rest of the substrate. In one subset of such embodiments, the removed lamella(s) is/are partially or entirely removed. In other embodiments, one or more lamellas of the starting substrate are removed prior to depositing the one or more wurtzite-crystal-structure-containing layer(s).

Photonic passive structure to couple and guide light between photonic active devices (101), such as photo-diodes, light emitting devices and light-valves, which may be arranged into 2D arrays, and the top of the metallization layer stack (110,111,112) interconnecting said devices, with said photonic passive structure comprising a hole (116) between the near surface of said photonic active Ndevices and the top of said metallization stack, said hole being filled with a dielectric (113) having embedded metal films (117) and in which the embedded metal thin films are connected to a planar perforated metal film (123,124) formed on top of the metallization stack.

The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.