2486 results about "Copper-wiring" patented technology

There is provided a barrier film preventing diffusion of copper from a copper wiring layer formed on a semiconductor substrate. The barrier film has a multi-layered structure of first and second films wherein the first film is composed of crystalline metal containing nitrogen therein, and the second film is composed of amorphous metal nitride. The barrier film is constituted of common metal atomic species. The barrier film prevents copper diffusion from a copper wiring layer into a semiconductor device, and has sufficient adhesion characteristic to both a copper film and an interlayer insulating film.

A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

(Problem) It is to provide a stripper having excellent ability to suppress corrosion or damage to the copper wiring or the low-k film, and having excellent photoresist residue removability after ashing. (Solution) The invention provides a photoresist stripper composition characterized in containing salts of at least two different inorganic acids, surfactants and a corrosion inhibitor for metal, and having a pH in the range of 3-10; and a process for preparation of semiconductor devices characterized in that the photoresist residues generated during the preparation of semiconductor devices which employs copper or a copper-dominant alloy as the material for wiring is stripped using said photoresist stripper.

A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and reacting the silicon film with a non-copper metal and/or nitrogen to form a barrier layer in a self-aligned manner relative to the copper wiring. In the method, the capacitance increase in the copper wirings formed is prevented, and the barrier layer formed has a satisfactory barrier property of protecting the copper wirings.

When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess.

A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.

Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

A copper wiring is desirable for a high-speed logic circuit integrated on a semiconductor substrate, and is patterned through a chemical mechanical polishing, wherein polishing particles are brushed away from the major surface of the resultant semiconductor structure by using hydrogen-containing water without damage to the copper wiring, and, thereafter, metallic contaminants such as copper is removed by using washer containing decontaminating agent selected from polycarboxylic acid, ammonium salts thereof and polyaminocarboxylic acid also without damage to the copper wiring.

A semiconductor device including an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O₂ to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.

In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.

The invention discloses a high-conductivity graphene fiber and a preparation method thereof. By the adoption of the wet spinning technology, oxidized graphene spinning liquid with the mass percentage being 1-10% is extruded from a spinning head into a coagulating bath to obtain an oxidized graphene gel fiber, the oxidized graphene gel fiber is collected on a graphite rolling shaft after being fully solidified, the oxidized graphene fiber is obtained, and the oxidized graphene fiber is sequentially subjected to chemical reduction, high-temperature thermal treatment and chemical doping. The prepared graphene fiber has high conductivity, and the conductivity of the prepared graphene fiber is one magnitude order higher than that of a common graphene fiber. The whole process is simple and controllable in technology, and conductivity of the graphene fiber is improved. The obtained graphene fiber has excellent mechanical property and excellent electrical conductivity and thermal conductivity. The high-conductivity graphene fiber can be used for preparing soft solar batteries, supercapacitors and wearable devices and can serve as a light wire to be used in ultra-light wires and cables, and it is hopeful to replace a metal copper wire with the graphene fiber for new-generation power transmission.

Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure.

To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

The purpose of the present invention is to provide: a magnetic element for wireless power transmission, which is capable of feeding power with high power transmission efficiency, while increasing the heat dissipation performance; and a method for manufacturing the magnetic element for wireless power transmission magnetic element for wireless power transmission have configurations that respectively comprise planar coils through which an alternating current passes and magnetic parts which are arranged in parallel in the intervals between the copper wires of the planar coils when viewed in cross section. The magnetic parts comprise an epoxy resin in which iron-based amorphous particles FINEMET® serving as magnetic particles are dispersed, and the magnetic parts are integrated with the planar coils by being bonded to the planar coils in an electrically insulated state by means of the epoxy resin.

An underlayer film-forming material for copper, a method for forming the underlayer, an underlayer film for copper, and a semiconductor device including a substrate, the underlayer and copper wiring film, which prevents copper diffusion as well as provides superior adhesion to a copper wiring film, even if the film is thinner than conventional barrier metals. The underlayer film-forming material for copper is formed from a compound represented by a (R₁R₂)P—(R)_n—Si(X₁X₂X₃), wherein at least one of X₁, X₂, and X₃ represents a hydrolysable group; each of R₁ and R₂ represents an alkyl group; R represents a divalent linear organic group which is selected from an alkylene group, an aromatic ring, and an alkylene group including an aromatic ring; and n is an integer from 1 to 6.

A polishing liquid is provided with which a polishing rate relative to a conductive metal wiring typically represented by a copper wiring on a substrate having a barrier layer containing manganese and/or a manganese alloy and an insulating layer on the surface (particularly, copper oxide formed at the boundary) is decreased and with which less step height between the conductive metal wiring and the insulating layer is formed, and a polishing method using the polishing liquid is also provided. The polishing liquid includes: colloidal silica particles exhibiting a positive ζ potential at the surface thereof, a corrosion inhibiting agent; and an oxidizing agent, in which the polishing liquid is used in a chemical mechanical polishing process for a semiconductor device having, on a surface thereof, a barrier layer containing manganese and/or a manganese alloy, a conductive metal wiring, and an insulating layer.