10 results about "Solder interconnection" patented technology

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die surrounded by an insulating material, the die having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface, a first redistribution layer (RDL), on the first surface of the die, including a first conductive pathway through a first dielectric material electrically coupled to the first conductive contact of the die by a first solderless metal-metal interconnect; and a second RDL, on second surface of the die, including a second conductive pathway through a second dielectric material electrically coupled to the second conductive contact of the die by a second solderless metal-metal interconnect, wherein a thickness of the die is between 20 microns and 45 microns. In some embodiments, a thickness of the die is between 60 microns and 75 microns.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a first encapsulation layer at least partially encapsulating the first integrated device; a plurality of through molding encapsulation layer via interconnects located in the first encapsulation layer; wherein the plurality of through molding encapsulation layer via interconnects are configured to provide an electrical path for ground; a seed layer coupled to and touching the first encapsulation layer, the plurality of through molding encapsulation layer via interconnects and a back side of the first integrated device; and a first heat sink coupled to the seed layer.

This disclosure provides a power module and a power conversion device, belonging to the field of power conversion technology. The power module includes at least one power chip, a substrate, a heat sink, and a solder layer. The at least one power chip is located on the surface of the substrate, and the substrate has a first metal layer on its surface opposite to the power chip. The area of ​​the metal layer is greater than or equal to the area occupied by the at least one power chip. The surface of the heat sink is provided with a blocking structure, the area enclosed by the blocking structure being greater than or equal to the area occupied by the at least one power chip and less than or equal to the area of ​​the first metal layer. The solder layer is disposed within the area enclosed by the blocking structure, and the heat sink is fixedly connected to the first metal layer through the solder layer. Adopting this disclosure can improve the reliability and stability of the soldered interconnection between the power module and the heat sink.

A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The integrated device comprises a die substrate; a die interconnection portion coupled to the die substrate; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of pillar interconnects coupled to the plurality of pad interconnects; and a plurality of interconnects coupled to the plurality of pillar interconnects, wherein at least one pad interconnect from the plurality of pad interconnects, at least one pillar interconnects from the plurality of pillar interconnects and at least one interconnect from the plurality of interconnects are configured as an inductor.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer includes a cavity; a metallization portion coupled to the first integrated device; and a first passive device coupled to the metallization portion through at least a second plurality of solder interconnects, wherein the first passive device is located at least partially in the cavity of the encapsulation layer.

Microelectronic assemblies, related apparatus, and methods are disclosed. In some embodiments, a microelectronic assembly can include a wafer surrounded by an insulating material, the wafer having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface; a first redistribution layer (RDL) on the first surface of the wafer including a first conductive path electrically coupled to the first conductive contact of the wafer by a first dielectric material through a first solderless metal-metal interconnect; and a second RDL on the second surface of the wafer including a second conductive path electrically coupled to the second conductive contact of the wafer by a second dielectric material through a second solderless metal-metal interconnect, wherein a thickness of the wafer is between 20 microns and 45 microns. In some embodiments, the thickness of the wafer is between 60 microns and 75 microns.

A package comprising an integrated device and a substrate coupled to the integrated device through a plurality of solder interconnects. The integrated device comprises a die substrate; a die interconnection portion coupled to the die substrate; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of pillar interconnects coupled to the plurality of pad interconnects; and a plurality of interconnects coupled to the plurality of pillar interconnects, wherein at least one pad interconnect from the plurality of pad interconnects, at least one pillar interconnects from the plurality of pillar interconnects and at least one interconnect from the plurality of interconnects are configured as an inductor.