38 results about "Solder interconnection" patented technology

A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.

A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip burn-in, replacement or field repairs.

A method and electrical structure for separating electronic components from one another joined by solder interconnections. An electronic module is joined to a substrate via a solder interconnection, whereby the electronic module has an electrical heating component residing within a bottom layer thereof adjacent a solder interconnection. Preferably, a chip carrier is joined to a board whereby the chip carrier has an electrical mesh plane for heating adjacent the solder interconnection. Resistive heat is generated within this electrical heating component either by applying an electrical current to the electrical heating component, or by non-contact inductively heating the layer in which such electrical heating component resides to generate resistive heat within the electrical heating component. The resistive heat is transferred to the solder interconnection to allow for localized melting of the solder interconnection and removal of the electronic components from one another.

The invention is directed to improved conductive adhesives for solder-free interconnections in microelectronic assembly processes such as for chip carrier-to-substrate attachment. These adhesives are characterized by low tensile modulus, low resistivity, high adhesion strength, and durability of these properties during reliability stress conditions of thermal shock, thermal aging, and temperature / humidity (85.degree. C. / 85%) exposure of the assembled devices. The adhesives contain a homogeneous solution of a siloxane containing epoxide, a curing agent, a curing catalyst and an organic polymeric or oligomeric additive. A conductive filler is added to the solution forming the filler. Preferred fillers are Ag coated with Pd and Ag coated with Au.

An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join / assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn / Ag and Sn / Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join / assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.

A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.

A packaging fabrication for an organic electroluminescence panel is disclosed. The panel comprises a printed circuit board, one or a plurality of OEL panels and a plurality of bumps, wherein the OEL is provided with poly solder interconnections in area array. The printed circuit board is provided with a plurality of solder pads arranged with bumps. One or a plurality of OEL is arranged on the printed circuit board and the poly solder interconnections and bumps are used to electrically connect the OEL with the printed circuit board. Further, the excellent heat dissipation property of the low re-flow temperature of the poly solder interconnections and the ceramic printed circuit board provides packaging fabrication for low temperature low stress OEL.

A method of attaching an integrated circuit chip to a module and a resultant structure. The method includes placing a solder bump tape between the chip and the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet; aligning and contacting top surfaces of solder columns with respective chip pads of an array of chip pads of the chip and aligning and contacting bottom surfaces of the solder columns with respective module pads of an array of module pads; and reflowing the solder columns to form solder interconnections between chip pads and respective module pads.

A solder interconnection between a module and printed circuit board or card is provided by a plurality of solder connections arranged in a micro grid array joining solder wettable pads on a major surface of the module to a corresponding set of solder wettable pads of the printed circuit board or card. The solder connections are column shaped with the height of each connection being at least about 1.4 times the diameter of the connection.

A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.

A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.

A solder pre-form for soldering a coaxial cable to a connector body is provided with a plurality of flux grooves on a cable side and a connector side. The solder pre-form may also have a plurality of holes between the cable and connector sides. In a method of use, flux is applied to the flux grooves and the solder pre-form applied to encircle the outer conductor which is then inserted into the connector body and the solder pre-form melted to complete the solder interconnection. Where holes are present, flux may be applied to the connector side, passing through the holes also to the cable side.

The invention discloses a flip chip semiconductor encapsulation structure which comprises a semiconductor chip, multiple copper posts, a lead frame, an insulating layer on the surface of the lead frame, multiple solder interconnection structures and moulding complexing agents. The surface of the semiconductor chip is provided with a pad pattern, and the copper posts are formed on the pad pattern. The insulating layer is provided with an opening, the area of the opening is larger than the cross area of each copper post, and leads on the upper portion of the lead frame are exposed at the opening. The solder interconnection structures are located between the copper posts and the leads exposed at the opening, and the moulding complexing agents are used for encapsulating the assembly. The flip chip semiconductor encapsulation structure enables the semiconductor chip to be firmly coupled on the lead frame, and meanwhile bad contact between the semiconductor chip and the lead frame is prevented.

A package structure of an OEL panel includes a printed circuit board, at least one OEL panel, and several bumps. Wherein, the OEL panel has several poly solder interconnections arranged in an array structure. The printed circuit board has several solder pads, which are also implemented with bumps. The at least one OEL panel is disposed on the printed circuit board to have the electric connection with the printed circuit board through the poly solder interconnections and the bumps.

The invention discloses a method of forming a flip-chip semiconductor encapsulation device. The method includes the following steps that: copper columns are formed on a pad pattern of a semiconductor chip, and one end of each copper column, which is far away from the pad pattern, is plated with a barrier layer, and a predetermined amount of solder is distributed on the barrier layers, and the solder is coated with soldering flux; lead frames are provided, and the surfaces of the lead frames are plated with insulating layers, and openings corresponding to the positions of the copper columns, are formed in the insulating layers and expose a part of leads of the lead frames respectively; the semiconductor chip is mounted on the lead frames in a flip manner, and the solder contacts with the exposed leads; when refluxing is performed, the solder is melt, and solder interconnection structures are formed between the copper columns and the exposed leads by means of the soldering flux; and after the refluxing, a film is attached to a non-active surface of the chip, and then, encapsulation is performed, and the film is removed, and therefore, the flip-chip semiconductor encapsulation device can be formed. According to the method, the non-active surface of the chip is not covered with the encapsulation material, so that the formed flip-chip semiconductor device can have an excellent heat dissipation effect.

A solder pre-form for soldering a coaxial cable to a connector body is provided with a plurality of flux grooves on a cable side and a connector side. The solder pre-form may also have a plurality of holes between the cable and connector sides. In a method of use, flux is applied to the flux grooves and the solder pre-form applied to encircle the outer conductor which is then inserted into the connector body and the solder pre-form melted to complete the solder interconnection. Where holes are present, flux may be applied to the connector side, passing through the holes also to the cable side.

A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.

An apparatus and method for soldering an electrical component to a circuit board includes a stage positioning the circuit board and electrical component in alignment with a solder tip along an axis. A first spring-loaded compression mechanism maintains contact between the circuit board and the electrical component, and a second spring-loaded compression mechanism brings the soldering tip into thermal contact with the circuit board and the electrical component such that solder disposed adjacent to the circuit board and the electrical component melts. When the second spring-loaded compression mechanism removes its applied force such that the soldering tip comes out of contact with the circuit board, the first spring-loaded compression mechanism maintains the contact between the circuit board and the electrical component while the solder cools and solidifies.