80 results about "Solder interconnection" patented technology

A method for normalizing the solder interconnects (e.g., normalizing the height of the solder ball interconnects) in a circuit package module (e.g., dual-sided mold grid array package module) after removal from a test board includes receiving in a fixture the circuit package module upside down and removably coupling a stencil to the fixture and over the circuit package module. The stencil has a pattern of apertures that coincides with the pattern of solder interconnects of the circuit package module. The method also includes applying solder paste over the stencil to pass through the apertures to add solder paste to the solder interconnects. The method also includes removing the stencil from over the fixture, and removing the circuit package module from the fixture. The circuit package module can be heated to reflow the solder interconnects with the added solder paste.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects, wherein the first integrated device comprises a plurality of through substrate vias; an interconnection device coupled to a back side of the first integrated device through a second plurality of solder interconnects; a second substrate coupled to the first substrate through at least a third plurality of solder interconnects; and a second integrated device coupled to the second substrate and the interconnection device.

A device comprising a board; a first package coupled to the board through a plurality of solder interconnects, wherein the first package comprises: a first substrate; a first integrated device coupled to the first substrate; a heat pipe coupled to the first integrated device through a thermal interface material; a second package coupled to the first substrate through a through a plurality of inter substrate interconnects; and an encapsulation layer located between the first substrate and the second package.

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A package, the package comprising: an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate includes: at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects at least partially located in the at least one dielectric layer. The frame may be an embedded frame.

The application relates to a method for improving the thermal fatigue resistance of a lead-free solder interconnection BGA package joint, and relates to the field of electronic packaging welding. The surface of a PCB substrate is processed by superfast laser to have a well-shaped micro-nano structure, the well-shaped micro-nano structure is a grid-shaped straight-line groove microstructure formed by a plurality of transverse parallel lines and a plurality of longitudinal parallel lines, the adjacent interval between the plurality of transverse parallel lines and the plurality of longitudinal parallel lines is 80-120 mu m, the groove width is 10-20 mu m, the groove depth is about 30-50 um, the groove parameters are adjusted by adjusting the superfast laser processing parameters, and a large number of micro-particles are covered on the inside and around the groove; the solder ball is planted on a bare chip through a heating plate, and the chip and the processed PCB substrate are welded and packaged through a hot air welding machine. The specific surface area and structural richness of the surface are improved, and the problems of poor thermal fatigue resistance and poor durability of the existing BGA package joint can be solved.

A package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

A package comprising a first substrate; an integrated device coupled to the first substrate through at least a first plurality of solder interconnects; an inter substrate interconnect structure coupled to the first substrate through at least a second plurality of solder interconnects. The inter substrate interconnect structure comprises an inner interconnect; a dielectric layer coupled to the inner interconnect; and an interconnect coupled to the dielectric layer, wherein the interconnect surrounds the dielectric layer and the inner interconnect; a second substrate coupled to the inter substrate interconnect structure through at least a third plurality of solder interconnects; and an encapsulation layer coupled to the first substrate and the second substrate.

A package comprising a substrate; and a passive device coupled to the substrate through at least a first plurality of solder interconnects. The passive device comprises a trench capacitor device; an encapsulation layer; and a metallization portion coupled to the trench capacitor device and the encapsulation layer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package comprising a substrate comprising a first surface and a second surface, wherein the substrate further comprises: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the first surface of the substrate through at least a first plurality of solder interconnects; and a passive device coupled to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via.

A package includes a package substrate and a first integrated device coupled to the package substrate by a first plurality of solder interconnects. The package substrate includes a bridge and / or interposer, an encapsulation portion, a first metallization portion coupled to a first surface of the encapsulation portion, and a second metallization portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block.

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; and a bridge coupled to the substrate, wherein the bridge comprises a plurality of spring pads.

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (GTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

An integrated device (e.g., flip chip) (100) includes a die portion (102) including a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) including a first pillar interconnect (104a) including a first cavity (209) and a second pillar interconnect (104b) including a second cavity (209). The cavity (209) can extend partially through a height of the pillar interconnect (104a, 104b). A planar cross-section of the cavity (209) extending through the pillar interconnect (104a, 104b) can include an O-shape. A plurality of solder interconnects (106a, 106b) can be coupled to the plurality of pillar interconnects (104a, 104b) and can include a solder interconnect (106a, 106b) located in the cavity (209) of the pillar interconnect (104a, 104b). The pillar interconnect (104a, 104b) can include a first pillar interconnect portion (204) including a first width and a second pillar interconnect portion (206) including a second width different from (e.g., smaller than) the first width, where the cavity (209) of the pillar interconnect (104a, 104b) can be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) can include a shape of a top hat. A method (700) for manufacturing an integrated device (100) can include providing a die portion (102) and forming a plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) can include forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) (e.g., having a circular pattern with a diameter between an inner diameter and an outer diameter of the ring-shaped first interconnect portion (602)) over the die portion (102); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that a first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) can also include forming a solder interconnect (106) over the cavity (209) of the pillar interconnect (104). The second photoresist layer (610) can be removed after forming the first solder interconnect (106). Portions of the under bump metallization layer (109) can then be removed, and the plurality of solder interconnects (106) can be reflowed. A package (400) includes a substrate (402) and an integrated device (100) coupled to the substrate (402) by a plurality of pillar interconnects (104a, 104b) and a plurality of solder interconnects (106a, 106b).The solder interconnects (106a, 106b) can include intermetallic compounds (IMCs) (406a, 406b) that can be formed when metals from the substrate interconnects (422a, 422b) and / or the post interconnects (104a, 104b) diffuse in the solder interconnects (106a, 106b) upon a solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area of the solder interconnects (106a, 106b) to couple, providing a more robust and reliable bond between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnects (106a, 106b) to be located between the post interconnects (104a, 104b) and the substrate (402) without causing shorts between adjacent interconnects (104a, 104b) of the substrate (402).

A package comprising a substrate comprising a first surface and a second surface, wherein the substrate further comprises: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the first surface of the substrate through at least a first plurality of solder interconnects; and a passive device coupled to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via.

Modularized construction of a structure is used for a multi-die integration package. Segregation of complex devices into substructures (sub-modules) are tested and verified as functional before final reconstitution into the multi-die integration package. The thermal coefficient of sub-modules can be fine-tuned for low chip module warpage. The sub-modules can be made with a glass interposer tuned with a certain coefficient of thermal expansion (CTE) and modulus to provide favorable warpage performance. Solder interconnects at high stress locations may be used to further reduce via and polyimide (PI) stresses. A minimal redistributed layer (RDL) comprising conductive metal patterns with a plurality of metal contacts thereon is formed on a polyimide (PI) or glass carrier and electrically interconnects the sub-modules together.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A package comprising a first substrate; an integrated device coupled to the substrate; a second substrate coupled to the first substrate through at least a plurality of solder interconnects, wherein the second substrate is located over a portion of the integrated device; and a heat sink coupled to a back side of the integrated device through a thermal interface material, wherein the heat sink is located over another portion of the integrated device, wherein the heat sink is located laterally to the second substrate.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a plurality of interconnects. The plurality of interconnects comprises a first via interconnect comprising a partial concentric planar cross section; and a second via interconnect comprising a partial ring planar cross section, wherein the second via interconnect laterally surrounds at least part of the first via interconnect.