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1149 results about "Burn-in" patented technology

Burn-in is the process by which components of a system are exercised prior to being placed in service (and often, prior to the system being completely assembled from those components). This testing process will force certain failures to occur under supervised conditions so an understanding of load capacity of the product can be established.

Resilient contact structures formed and then attached to a substrate

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.
Owner:FORMFACTOR INC

Optimized control of power plants having air cooled condensers

An optimization and control system for a utility plant that uses fan based air cooled condensers controls the operation of the power generation system at the plant in conjunction with the operation of the air cooled condensers so as to run the power plant at an optimum operating point associated with minimizing or reducing the cost of each kilowatt-hour of energy or other useful energy produced by the plant. The optimization and control system includes an optimizer having a numerical solver that determines values for a set of control variables associated with an optimal operating point of the plant and an expert system that oversees and modifies the control variable settings prior to providing these settings to a plant controller. The numerical solver uses an objective function and one or more models of plant equipment to determine the operating point of the plant that minimizes the cost per unit of useful energy generated by the plant. As part of determining the optimal plant operating point, the numerical solver may determine the number of fans to run within the air cooled condensers of the plant and/or the speed of the fans to use in the air cooled condensers in conjunction with the amount of fuel to burn in the boiler, the desired temperature of the steam at the input of the steam turbine, etc., all required to produce a given amount of power (load demand) at the particular environmental conditions currently experienced at the plant. The expert system may modify these outputs by determining which fans to actually use at any particular time based on, for example, the availability of or the operational status of the fans, the wear of the fans and fan motors, etc.
Owner:EMERSON PROCESS MANAGEMENT POWER & WATER SOLUTIONS

Test and burn-in apparatus, in-line system using the test and burn-in apparatus, and test method using the in-line system

A test and burn-in apparatus for semiconductor chip package devices, an in-line system which includes the test and burn-in apparatus, and a test method which employs the in-line system are provided. A test and burn-in apparatus for testing semiconductor devices allows various testing processes, including a burn-in process, to be performed at the same testing stage. The apparatus employs test trays which contain the semiconductor devices. These test trays are used throughout the in-line system so that an entire back-end process can be performed without the need for loading / unloading the semiconductor devices into and from device trays between the various tests. The test and burn-in apparatus according to this invention can therefore occupy less space than the prior art testing apparatuses. The in-line system includes multiple test and burn-in apparatuses as well as a single sorting unit which performs a composite sorting operation after all the testing processes have been performed. Furthermore, the method for testing the semiconductor devices in the in-line system includes testing the semiconductor devices in the test trays using the test and burn-in apparatus, generating a test tray map corresponding to results of the test, transferring the test trays to a different testing apparatus for a second testing and test tray map generation process, and finally sorting the semiconductor devices in the sorting unit after all testing processes have been performed based on a final sorting map created by combining the test tray maps of each of the tests. The benefits of this invention are reduced time and space requirements because neither transferring the devices to device trays between tests nor performing multiple sorting steps are required.
Owner:SAMSUNG ELECTRONICS CO LTD

Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application

A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.
Owner:IBM CORP

Massively parallel interface for electronic circuit

Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and / or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.
Owner:ADVANTEST SINGAPORE PTE LTD
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