The invention provides an in-
speed test design method beneficial to
time sequence optimization. The in-
speed test design method comprises the following steps: S1, a
chip design stage, a comprehensive stage and a
test vector generation stage: a buffer is arranged in a
netlist; s2, a back-end
design stage: no buffer exists in a
netlist output by a back end; s3, manually modifying the
netlist, and adding a buffer; s4, a form
verification stage: comparing that the functions of the netlist are the same before and after the addition of the buffer; s5, a
test vector generation stage: inputting a netlist containing a buffer; and S6, a
simulation verification stage, wherein no buffer exists in the verified netlist. By using the method, the
chip can reach faster frequency; the balance of the
clock network can be ensured, the structure of the
clock network can be simplified, the possibility of errors is reduced, and the process is simpler; the
clock path is inserted into an
inverter to optimize the
time sequence, and the
power consumption is lower than that of an inserted buffer; the size of the
chip can be reduced by deleting unnecessary buffers, and the production cost is saved; and the
correctness is ensured.