74 results about "Microvia" patented technology

A circuit board including a board substrate having opposite first and second sides. The board substrate has a thickness measured along a z-axis that is perpendicular to the first and second sides. The circuit board also includes plated thru-hole (PTH) vias extending along the z-axis from the first side into the board substrate. The PTH vias are arranged to form multiple signal pairs. The circuit board also includes signal traces that are directly coupled to the PTH vias and extend perpendicular to the z-axis in the board substrate. The signal traces and the PTH vias are configured to transmit differential signals. The circuit board also includes ground columns that extend along the z-axis in the board substrate. The ground columns are distributed relative to the signal pairs to form shield arrays. Each of the shield arrays surrounds one of the signal pairs, wherein the ground columns comprise microvias.

A flip chip package may include stacked vias in which the diameter D1 of the outermost via is less than the diameter D2 of the innermost via. The ratio D2/D1, for example, may be 1.5 to 2.

A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N ≧2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N-1 and metal plane N-1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

A laser drilling system for drilling blind vias in printed circuit board panels, multichip modules and chipscale packages with top and bottom surfaces and which include multiple dielectric polymer and metal layers. The system includes a first laser module comprising a laser able to form at least one via per pulse through one or more polymer layers. The vias are circular or non-circular in shape. An articulated arm is adapted to move at a speed of about 200 inches per second and at an acceleration of about 5 g's or more. A beam delivery unit is attached to the articulated arm and a conveyor adapted to move panels at a constant speed. The first laser module positioned on a separate track from the conveyor moves at a faster rate than the conveyor to drill the top surface. A second laser module is positioned to move on another separate track from the conveyor movable at a faster rate so as to drill the bottom surface.

The present invention provides inter alia copper electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention contain an increased brightener concentration that can provide effective copper plate on difficult-to-plate aperture walls, including high aspect ratio, small diameter microvias.

The invention relates to an electrocoppering solution for filling blind microvia. Materials of block polyether, poloxamers, amine block polyether or polyvinylpyrrolidone and the like are added into the electrocoppering solution to be used as an inhibitor so as to realize a synergistic effect with an accelerator of sodium 3, 3'-dithiodipropane sulfonate or 3-sulfhydryl group-1-propanesulfonate, a leveling agent of janus green and the like and chloride ions, so that the non-voidance, seamless and perfect electrocoppering filling of the blind microvia with different ratios of pit-depth to pit-diameter for an electroplating technology is realized. The electrocoppering solution has the advantages of stable quality, long service life, large concentration operation windows for various additives, small copper surface area thickness and the like.

The electronic module comprises a dielectric 1031 substrate having a first surface and a second surface and an installation cavity extending through the dielectric substrate and having a perimetrical side wall. The electronic module further comprises a first wiring layer 1032 on the first surface, a second wiring layer 1033 on the second surface, and a feed through conductor 1034 on the perimetrical side wall and electrically connecting at least one conductor in the first wiring layer to at least one conductor in the second wiring layer. There is also at least one IC inside the installation cavity. The electronic module further comprises a first insulating layer 1035 on the second wiring layer, a second insulating layer 1036 on the first wiring layer, and a third wiring layer 1037 on the first insulating layer. First microvias 1038 inside the first insulating layer make electrical connections between the second wiring layer and the third wiring layer. Second microvias 1039 electrically connect the IC to at least one of the second wiring layer and the third wiring layer. The electronic module comprises also a fourth wiring layer 1040 on the second insulating layer and third microvias 1041 inside the second insulating layer and making electrical connections between the first wiring layer and the fourth wiring layer.

A method for microvia filling by copper electroplating with a TSV technology for a 3D copper interconnection at a high aspect ratio, which includes: Step 1: formulating an electroplating solution of a copper methyl sulfonate system, Step 2: wetting the microvias of the TSV technology by means of an electroplating pre-treatment, Step 3: charging into the grooves, completing the ultra-low current diffusion, so that the copper ions and the additives are rationally distributed at the surface and the interior of the microvias of the TSV technology, Step 4: connecting the wafer for the TSV technology to the cathode of a power source, fully immersing the electroplating surface of the wafer in the electroplating solution, and electroplating with a step-by-step current method of rotating or stirring the cathode, the current density of the plating conditions is 0.01-10A/dm2 and the temperature is 15-30° C., Step 5: after the electroplating, washing the wafer completely clean with deionized water, and drying it by spinning or blowing. The method for microvia filling by copper electroplating with a TSV technology for a 3D copper interconnection at a high aspect ratio has a high via-filling speed, a thin copper layer on the surface, no risk of creating voids and cracks, and can achieve the complete filling of microvias having an aspect ratio of more than 10:1 which are extremely difficult to fill.

The invention discloses a microvia-superfilling copper plating technology. The microvia-superfilling copper plating technology comprises the following steps of a, carrying out activation treatment on a blind hole plate to be plated in a dilute sulphuric acid solution for 1-10min, carrying out water washing and drying, vertically fixing the blind hole plate to be plated to the middle of a Hull cell having the volume of 1500mL, and putting phosphor-containing copper plates as anodes having phosphor content of 0.04-0.065% at two ends of the cell, b, preparing a plating solution, c, switching on a power supply, carrying out electroplating at current density of 0.5-2ASD for 5-30min, increasing current density to 0.5-4ASD, carrying out electroplating for 10-20min, wherein the whole electroplating process is finished in a static state, then switching off the power supply, taking out the blind hole plate as a cathode, flushing the blind hole plate by distilled water, and blow-drying the blind hole plate by cold air to obtain a sample. Under the condition of absolutely no forced convection of the plating solution, the microvia-superfilling copper plating technology does not increase surface copper thickness and guarantees a high microvia-filling rate of the blind hole device.

An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

A system (1) has a projection lens (12) directing on-axis light and low level LEDs (18) directing light to blind microvias (5). A high resolution camera (14) captures blind microvia images and an image processor recognizes defects according to classifications (54-59) according to reflected light area and centroid position. The lens (12) is telecentric for particularly effective image capture in blind microvias (5). The system also has an array of 6000 back lighting LEDs (10) providing illumination for capture of images by a camera (15). These images are analyzed by the image processor to detect defects such as blocked through microvias.

Inspection of partially drilled microvias by fluorescence based optical imaging techniques, selective coaxial illumination and multivariable off-axis illumination and the use of comparative image analysis and the transformation of back reflected radiation by means of an integrated fluorescing plate mounted to the surface of a CCD or EMCCD array.

A method for manufacturing electrical connecting elements or semifinished products. Microvias are formed in a dielectric substrate layer by piercing a substrate layer (1) through a first conducting layer (3), which essentially covers an entire side of the substrate. The perforation depth (d) is at least equal to the total thickness of the substrate and the first conducting layer. The conductor material of the first conducting layer (3), during the piercing step, is deformed so that it partially covers the wall of the hole fabricated by the piercing process. Plating the first conducting layer with additional conductor material bridges the little remaining distance between the conductor material and the opposite side of the substrate layer.