19 results about "Microvia" patented technology

The invention provides a three-dimensional stacked packaging substrate device and a manufacturing method, and relates to the technical field of semiconductor packaging, and the three-dimensional stacked packaging substrate device comprises a substrate which is a multi-layer stacked substrate; a drop point area corresponding to the vertical interconnection terminal is provided with a backflow channel, and the backflow channel comprises a grounding via hole array or a grounding metal ring surrounding the drop point area and is used for providing a continuous reference loop for a high-speed signal transmitted through the vertical interconnection terminal. Providing a core plate, carrying out multi-layer lamination, and manufacturing a backflow channel in a corresponding vertical interconnection terminal drop point area; manufacturing blind holes or micro holes in the substrate to realize interlayer interconnection; the substrate is divided into a high-speed digital area, an analog / radio frequency area and a power supply area according to functions for partition wiring, and the ground plane of each partition is kept continuous; a decoupling device is arranged at the near end of the vertical interconnection drop point or the chip power supply inlet. The system has the beneficial effects that low reflection, low jitter and low bit error rate of high-speed signal transmission are realized, and the electromagnetic compatibility and the working reliability of the system are improved.

Provided is a process of securing a board component in an in-mold electronics assembly, the process comprising: inserting the board component into a mold; injecting a thermally conductive thermoplastic polymer composition into the mold and into a flow-through collar to flow over the board component which lies within an insert pocket in the in-mold electronics assembly; cooling the thermally conductive thermoplastic polymer composition securing the board component and forming the in-mold electronics assembly; and removing the in-mold electronics assembly from the mold, wherein the board component optionally includes one or more attachment openings, through holes, through-hole vias, blind vias, buried vias, microvias, stacked microvias, and any combination thereof allowing the thermally conductive thermoplastic polymer composition to flow therethrough.

This invention belongs to the field of semiconductor manufacturing and circuit board electroplating technology, and particularly relates to an acidic copper sulfate electroplating solution containing a tetrazine structure, its preparation method, and its application. The electroplating solution is prepared by the following method: first, anhydrous copper sulfate is dissolved in ultrapure water, and then sulfuric acid, chloride ions, inhibitors, accelerators, and synergist 3,6-bis(pyridin-3-yl)-1,2,4,5-tetrazine are added sequentially under stirring conditions, and the mixture is stirred until homogeneous. This invention also provides a method for using the above electroplating solution in TSV blind via electroplating, including pretreatment of a TSV silicon blind via substrate with a diameter of 10 µm and a depth of 30 µm, using it as a cathode, clamping it with a platinum electrode, and placing it in the copper sulfate electroplating solution for electroplating. The electroplating solution formulation of this invention has a synergistic effect, exhibits excellent filling performance in TSV blind via electroplating, and is suitable for electroplating processes of high aspect ratio microvias.

According to various embodiments, a printed circuit board includes: a buried via formed through one or more layers of the printed circuit board; a first conductive pad that is formed on a first end of the buried via; a first conductive via that is formed through a first layer of the printed circuit board and is connected to the first conductive pad; and a second conductive via that is formed through the first layer of the printed circuit board and is connected to the first conductive pad.

The invention discloses an intermediary layer in a chip packaging structure and a preparation method thereof, and the method comprises the following steps: providing the intermediary layer, and etching and preparing a plurality of micro through holes in the intermediary layer; prefabricating a high copper column, providing a carrier wafer, and bonding an intermediate layer on the first surface of the carrier wafer; accurately matching the high-copper columns into the micro-through holes to metalize the micro-through holes, filling gaps between the high-copper columns and the micro-through holes with insulating materials, and solidifying the insulating materials; and de-bonding, removing the carrier wafer, and removing redundant materials on the surface of the intermediate layer by adopting a CMP copper exposing process, so that the end surfaces of the high-copper columns are exposed on the two surfaces of the intermediate layer. According to the manufacturing method, the mode of prefabricating the high copper column is adopted, the technical limitation of the height of the electroplated metal high copper column is avoided, the high copper column with the higher height can be manufactured, the height of the high copper column is larger than 150 micrometers, and the requirements for the high copper column in the fields of the microelectronic manufacturing technology, semiconductor device manufacturing, the electronic packaging technology and the like are met.

Disclosed is an electronic assembly (EA) comprising: - a circuit carrier (ST), - a semiconductor device (HB) embedded in the circuit carrier (ST) and having an electrical contact surface (KF1), - wherein the contact surface (KF1) of the semiconductor device (HB) is physically and electrically contacted by means of a microvia (MV), wherein the microvia (MV) is sintered onto the contact surface (KF1) of the semiconductor device (HB) in a sintering process using a metallic, in particular copper-containing, sintering paste (SP). Furthermore, an inverter with a specified electronic assembly (EA) and a method for manufacturing the specified electronic assembly (EA) are described.

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

The application provides a micro via array metal filter manufacturing method and a metal filter thereof. The micro via array metal filter manufacturing method comprises the following steps: manufacturing a photoetching mask; forming a titanium nitride film on one side of a silicon wafer; bonding to form a glass-titanium nitride film-silicon wafer three-layer sandwich structure; spin coating photoresist on the outer side of the silicon wafer, placing the photoetching mask to expose the photoresist, post-baking, developing, then etching the non-resin area on the silicon wafer, and removing the photoresist to obtain a micro column array silicon wafer structure; pulse electroforming, stripping the electroformed metal micro hole structure from the silicon wafer to obtain a metal filter; and removing silicon from the obtained metal filter to obtain a micro via array metal filter with a preset thickness. The application can prepare a micro via array metal filter with a depth-width ratio greater than 50:1, greatly improves the processing efficiency of the metal filter, and most importantly, ensures the uniformity and consistency of the micro vias in the metal filter, with a CV value less than 5%.

The present invention provides a method for fabricating laser-conductive microvias on a PCB board and the PCB board. The method comprises: performing a copper coating operation on the PCB board to obtain a processed board, wherein the processed board includes a first processed surface and a second processed surface; positioning the PCB board on the first processed surface to obtain a first positioning hole; drilling a hole on the first processed surface to two-thirds of the thickness of the processed board according to the first positioning hole to obtain a first laser hole; positioning the PCB board on the second processed surface according to the first laser hole to determine a second positioning hole, wherein the second positioning hole and the first positioning hole are arranged symmetrically about the horizontal axis of the processed board; drilling a hole on the second processed surface to two-thirds of the thickness of the processed board according to the second positioning hole to obtain a second laser hole; and machining the target microvia based on the first laser hole and the second laser hole. In an embodiment of the present invention, the problem that mechanical drilling cannot produce microvias that meet the requirements can be solved, thereby saving costs while producing microvias.

This application relates to the field of micro-hole processing technology, and in particular to a micro-hole processing method, apparatus, and workpiece. The micro-hole processing method includes: providing a worktable and a workpiece to be processed; fixing the workpiece to be processed on the worktable; heating a first processing area on the upper surface of the workpiece to a temperature higher than the workpiece's ambient temperature; and applying an ultrasonic processing component to the heated first processing area to perform micro-hole processing on the workpiece. By heating the first processing area on the upper surface of the workpiece, the technical effect of improving the quality of micro-hole processing is achieved.

A self-filling method for high-aspect-ratio microvias of a substrate is provided, in which the substrate is activated with a coupling agent; a pasty nano-filler is applied onto a surface of the substrate, where the microvias in the substrate are self-filled with the pasty nano-filler through capillary action, the pasty nano-filler has a wetting angle of α≤30°, and each of the microvias has an aspect ratio of 5-500:1 and a diameter of 1-100 μm; and the coated substrate is subjected to sintering treatment.

A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

The application relates to the technical field of C23C18 / 38, in particular to a plating copper bath for filling blind micro-via holes and a use method thereof, which at least comprises a leveling agent solution of 12-16 mL / L, a brightener solution of 10-15 mL / L, sulfuric acid of 60-80 g / L, copper sulfate of 160-180 g / L, hydrochloric acid of 40-55 mg / L, an oxidizing agent of 1.0-8.0 g / L, and ultrapure water supplementing to 1L. The plating copper bath has excellent hole filling performance, good filling and left-right effects for blind micro-via holes, and a bright and smooth appearance of the plating layer.

The present invention relates to a method for removing an organic resin from a copper surface on a dielectric substrate containing conductive through-holes (TH) and / or conductive blind microvias (BMV), comprising the following steps: (i) applying an organic paste to the dielectric substrate to fill the through-holes (TH) and / or blind microvias (BMV) with the organic paste, wherein, after step (i), at least a portion of the surface of the dielectric substrate is covered with the organic paste; and (ii) curing the organic paste to convert it into a solidified organic resin, wherein, after step (ii), the dielectric (iii) a step of coating at least a portion of the surface of the substrate with an organic resin; and a step of chemically treating the dielectric substrate with a non-aqueous composition to remove the organic resin from the surface of the substrate in order to obtain a chemically treated surface of the substrate, wherein the non-aqueous composition comprises: a) at least one high-boiling point solvent having a boiling point of at least 100°C in a concentration of 80% to 95% by mass; b) at least one carboxylic acid in a concentration of 5% or more and less than 20% by mass; c) at least one anionic aromatic surfactant in a concentration of 0.25% or more and less than 1.5% by mass; and d) 0.25% or more and 1.A step comprising: (iv-1) a step of mechanically treating the chemically treated surface of the substrate obtained after step (iii) with an abrasive to remove residual organic resin from the chemically treated surface of the substrate in order to obtain a mechanically treated surface of the substrate; and / or (iv-2) a step of wet chemically treating the chemically treated surface of the substrate obtained after step (iii) with an oxidizing solution containing an oxidizing agent to remove residual organic resin from the chemically treated surface of the substrate in order to obtain a wet chemically treated surface of the substrate; (v The present invention relates to a method comprising: (i) in some cases, a step of depositing a conductive material, preferably electrolytically removing a coating metal, on a mechanically treated surface obtained after step (iv-1) or on a wet-chemically treated surface of the substrate obtained after step (iv-2) to obtain a conductive surface of the substrate; and (vi) in some cases, a step of further electrolytically removing a coating metal on the conductive surface of the substrate obtained after an optionally selected step (v) or on a mechanically treated surface of the substrate obtained after step (iv-1) or on a wet-chemically treated surface of the substrate after step (iv-2) in order to obtain an electrolytic metal coating surface.

The present invention relates to an optical inspection system and method for semiconductor substrates. [Solution] The optical inspection system and method for semiconductor substrates involves placing a sample at the inspection position and introducing an excitation light source into the sample for measurement. The excitation signal generated after the light source enters the sample in the forward direction is called the forward excitation signal, and the excitation signal generated after the light source enters the sample and is reflected by another interface of the sample is called the reverse excitation signal. The system collects the forward and reverse excitation signals and, through a signal processing and image generation module, generates high-resolution images of the via wall shape and defects of microvias, enabling accurate inspection of the internal structure of microvias.

The utility model provides a heat-conducting silica gel patch with high tensile property, which comprises a heat-conducting silica gel patch body and a copper column, the heat-conducting silica gel patch body comprises a tensile layer I, a tensile layer II, a heat-conducting layer I, a heat-conducting layer II, a heat-conducting layer III, a base material layer and a patch body, and a plurality of micro through holes uniformly penetrate through the surface of the heat-conducting silica gel patch body. Compared with the prior art, the utility model has the following beneficial effects: the tensile layer I and the tensile layer II are added into the heat-conducting silica gel patch body, so that the overall tensile strength and durability of the whole patch can be obviously enhanced, and the patch can be prevented from cracking or falling off under the action of stretching or external force; through the arrangement of the copper column, the first heat conduction layer, the second heat conduction layer and the third heat conduction layer, heat is transmitted to the copper column from the electronic component and then is transmitted to the external environment through the first heat conduction layer, the second heat conduction layer and the third heat conduction layer in the heat conduction silica gel patch, the heat resistance is reduced to the maximum extent, and the heat dissipation capacity is improved.

The application discloses a kind of microvia processing methods based on picosecond-microsecond composite laser, steps include: S1: processing substrate is washed and dried;S2: setting laser processing path;S3: first pulsed laser is generated and shaped;S4: after interval predetermined time, second pulsed laser is generated and primarily shaped;S5: first pulsed laser and second pulsed laser are integrated by beam combiner, and cooperate in predetermined position, form microvia;Again, microvia is sequentially processed along laser processing path in processing substrate, microvia array processed in processing substrate can be formed.The microvia processing method is through the synergistic mechanism of " picosecond pulse induced channel " and " microsecond pulse selective removal ", using its no diffraction, long focal depth characteristics, can be processed in hard and brittle transparent material once microvia with depth-diameter ratio more than 300:1, and single-hole processing time can be shortened to 20 μs, suitable for high depth-diameter ratio microvia high-density, mass production.

The application discloses a structure for improving temperature measuring performance of a temperature measuring chip by adopting graphene material and a manufacturing method thereof, and relates to the technical field of temperature sensing, which comprises a temperature measuring chip packaged on a circuit substrate, a micro hole is formed on the circuit substrate at a position opposite to a temperature sensing area of the temperature measuring chip, a heat conduction column is arranged in the micro hole, an upper end surface of the heat conduction column is in contact with a temperature sensing surface of the temperature measuring chip, and a graphene sheet capable of being in contact with a surface of a measured object is connected to a lower end surface of the heat conduction column, and a heat insulation pad is arranged between the graphene sheet and the circuit substrate, so that the temperature sensing surface of the chip and the surface of the measured object are connected almost directly, heat conduction time is greatly shortened, and heat conduction efficiency is improved.