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A tester with mixed protocol engine in a FPGA block

A tester, communication protocol technology, used in electronic circuit testing, automated test systems, detection of faulty computer hardware, etc.

Active Publication Date: 2015-12-09
ADVANTEST CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, on the test bench, when a DUT running a protocol different from that supported by the existing adapter card needs to be tested, critical time is consumed in replacing the hardware bus adapter card

Method used

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  • A tester with mixed protocol engine in a FPGA block
  • A tester with mixed protocol engine in a FPGA block
  • A tester with mixed protocol engine in a FPGA block

Examples

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Embodiment Construction

[0033] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. While the embodiments have been described in conjunction with the drawings, it should be understood that they are not intended to limit the embodiments. On the contrary, these embodiments are intended to cover alternatives, modifications, and equivalents. Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding. However, one of ordinary skill in the art will recognize that these embodiments can be practiced without these specific embodiments. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0034] Symbols and Terminology Section

[0035] Portions of the detailed description that follow are presented in terms of procedures, logic blocks, processe...

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PUM

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Abstract

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.

Description

technical field [0001] The present disclosure relates generally to the field of electronics test systems, and more particularly to the field of electronics test equipment for testing devices under test (DUTs). Background technique [0002] Automatic test equipment (ATE) may be any test assembly that performs tests on semiconductor devices or electronic assemblies. ATE assemblies can be used to implement automated tests that quickly perform measurements and generate test results that can then be analyzed. An ATE assembly can be anything from a computer system coupled to a meter to a complex automated test assembly that may include a custom purpose-built computer control system and a number of components capable of automatically testing electronic components and / or semiconductors Different test instruments for wafers (for example, system-on-chip (SOC) testing or integrated circuit testing). ATE systems both reduce the amount of time spent testing a device to ensure that the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G01R31/3177
CPCG01R31/2834G01R31/318307
Inventor 约翰·费迪尼安德鲁·尼米克
Owner ADVANTEST CORP
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