432results about "Automated test systems" patented technology

A test and / or measurement instrument includes at least three ports and at least three measurement circuits connected to the at least three ports, respectively. The test and / or measurement instrument further includes at least one signal generator circuit and a control circuit. The control circuit is configured to set a first calibration mode and carry out a first test of the instrument by measuring the calibration signal travelling from the signal generator circuit to the respective port as well as a signal traveling from the respective port to the signal generator circuit. The control circuit is configured to set a second calibration mode and carry out a second test of the instrument by measuring the calibration signal forwarded only to the main port in the first sub-mode and the calibration signal received by the respective port from the signal generator circuit via the main port in the first sub-mode.

The invention relates to a PCBA automatic testing system and method, and relates to the technical field of PCBA automatic testing, and the system comprises a multi-source data collection module which is used for collecting chip dynamic power consumption waveform, PCB interlayer temperature gradient, and multi-source data of signal loop impedance change, and eliminating the sampling delay error of a sensor through a synchronous collection time sequence alignment algorithm; transmitting the acquired multi-source data to a dynamic modeling engine; according to the invention, by dynamically fusing the multi-physical-quantity data and adaptively generating the test path, the system can detect the fault of the PCBA more comprehensively and accurately, the detection efficiency is improved, and the false detection rate is reduced; the thermal aging and faults of the PCB are predicted by using a dynamic modeling engine, so that potential failure risks can be found in advance, and a powerful guarantee is provided for quality control of the PCB; and the test path is automatically generated according to the dynamic modeling result and the data of the fault knowledge graph, so that the workload and error of manually planning the test path are reduced.

The invention discloses a method, a system and equipment for predicting the stability of integrated circuit test equipment and a medium, and belongs to the technical field of integrated circuit test. The method comprises the following steps: firstly, carrying out preprocessing and feature selection on historical data in an FT test stage, and adopting a Gaussian mixture model (GMM) to cluster and identify different operation condition clusters of a test machine; then, establishing a health state GMM reference for each working condition cluster, calculating a KL divergence value of a normal sample and the reference, and setting a dynamic anomaly detection threshold by 99.73% quantile of the KL divergence value; and finally, in real-time monitoring, calculating a KL divergence value of real-time data and a corresponding working condition cluster benchmark, and comparing the KL divergence value with a dynamic threshold value to realize accurate anomaly marking. The method effectively solves the problem of abnormal detection of the test data of the integrated circuit under complex and changeable working conditions, and improves the monitoring accuracy and working condition adaptability.

The present disclosure relates to a tester, a test system, and a test method. The tester comprises a plurality of function boards, a main control module, and a co-processing module. The function boards implement different functions. The main control module is connected to the function boards and the host respectively and is configured to receive test item(s) sent by the host and send test sequences in the test item(s) to the function boards. The plurality of function boards is connected to at least one device under test, and is configured to send excitation signals to the at least one device under test according to the received test sequences, and receive response signals fed back by the at least one device under test based on the excitation signals, obtain test data, and send the test data to the co-processing module. The co-processing module is connected to the plurality of function boards respectively, and is configured to process the test data obtained by the function boards to obtain test result(s), and send them to the host. The present disclosure can improve the testing efficiency.

The invention belongs to the technical field of board card testing, and particularly relates to a board card voltage and current measurement and insulation voltage resistance testing method and system, and the method comprises the steps: starting a testing cabinet of a board card testing system, carrying out the self-inspection, and setting system parameters; a power supply is loaded according to set system parameters, and a load mode is selected according to different product requirements to provide working voltage and current for the board card; after the load mode is confirmed, voltage and current measurement and insulation voltage resistance test are carried out on the board card in a probe contact mode, and test data are transmitted to the data processing and analyzing module in real time; and the data processing module judges according to preset upper and lower limit standards after receiving the measurement and test data, and stores the data and an evaluation result to the storage unit at the same time. Through unified control and data processing, voltage and current measurement and insulation voltage resistance testing of the board card are integrated in one system, automatic board card comprehensive testing is achieved, and the accuracy and efficiency of board card comprehensive testing are improved.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention provides a microwave superheterodyne frequency sweep measurement system based on Rydberg atoms, and belongs to the technical field of microwave frequency measurement. The laser module excites detection light of 780 nm and coupling light of 480 nm, and the two beams of light are reversely input into the atomic gas chamber through the dichroscope; signal microwaves are generated by a radio frequency signal source and are radiated to the position of the atomic gas chamber through the horn antenna; local oscillation microwaves are generated by the microwave module and are also radiated to the position of the atomic gas chamber through the horn antenna; the atomic gas chamber serves as a mixer to form a difference frequency signal; the spectrum analyzer is used for monitoring low-frequency difference frequency signals generated in the frequency mixing process in real time and recording signal intensity in real time. According to the invention, high-precision and wide-band microwave frequency measurement is realized, continuous and smooth frequency sweeping response can be provided in a frequency range, and absolute frequency detection of microwave signals is realized under the condition that a complex frequency comb technology is not introduced. The hardware architecture is simplified, the automation degree is improved, and integration, popularization and application are facilitated.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

The invention relates to the technical field of PCBA testing devices, in particular to a production line PCBA full-automatic testing device which comprises a supporting box, a supporting frame, a pressing assembly, a detection assembly, a bearing plate and a display screen. The pressing assembly is arranged on one side of the top of the supporting frame, the detection assembly is installed on the lower side of the supporting frame, and the bearing plate is fixed to the other side of the bottom of the supporting frame. A U-shaped containing groove is formed in the bearing plate, pressing frames are arranged on the two opposite sides of the groove in a lifting mode, and pressing blocks are arranged at the four corners of the groove in an inward rotating mode. And the bottoms of the pressing frame and the pressing block are connected with a driving assembly for controlling the lifting of the pressing frame and the rotation of the pressing block. Through cooperative work of the linkage clamping mechanism and the U-shaped placement groove, rigid fixation and quick release of the PCBA board are synchronously realized in single operation, so that the offset risk caused by human force difference in the testing process is eliminated, the contact precision of a probe is ensured, an open type part taking channel is optimized, and the detection reliability and the operation practicability are improved.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention discloses a chip testing method, device and system based on a visual waveform platform and a medium, and relates to the field of chip testing, and the method comprises the steps: obtaining an initial simulation waveform selected by a user based on a chip type; target parameters of the initial simulation waveform are extracted, an editing result input by the user is obtained, and the editing result is obtained by editing the target parameters through a visual waveform platform by the user; adjusting the initial simulation waveform based on the editing result to obtain a target simulation waveform; converting the target analog waveform into binary waveform data, and sending the binary waveform data to a hardware execution mechanism, so that the hardware execution mechanism generates an excitation signal based on the binary waveform data, and controls a digital-to-analog converter driving chip to output a response waveform through the excitation signal; and determining whether the chip passes the test according to the target simulation waveform and the response waveform. And the professional skill requirements on operators are reduced, the operation difficulty is reduced, and the test efficiency is improved.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention relates to an antenna device comprising a quad-ridged waveguide, an open end of which is configured to act as a radiating aperture, and an orthomode transducer, OMT, configured to couple the quad-ridged waveguide to two feed structures.

A method is performed by a session management module and includes the steps described below. An update instruction sent by a target test module is received; a session table is queried according to identifier information corresponding to the target test module so that a listening module identifier set corresponding to the target test module is obtained; a demand instruction is sent to a listening module corresponding to each listening module identifier in the listening module identifier set; an acquisition instruction sent by the listening module is received and the acquisition instruction is sent to the target test module so that the target test module sends shared information to the session management module; the shared information corresponding to the shared information identifier sent by the target test module is received, and the shared information corresponding to the shared information identifier is sent to the listening module.

The embodiment of the invention discloses a pre-charging loop fault diagnosis method and device and a storage medium. The method is applied to a pre-charging loop and comprises the following steps: calculating a theoretical range of an electrical parameter change ratio of the pre-charging loop according to a resistance value range of a pre-charging resistor, a capacitance value range of a capacitor and a preset sampling period; acquiring a voltage information change ratio or a current information change ratio of the pre-charging resistor at each sampling moment in the preset sampling period in an actual pre-charging process, and obtaining an actual electrical parameter change ratio of the pre-charging loop; when the actual electrical parameter change ratio is not within the theoretical range, it is judged that a fault exists in the pre-charging loop; wherein the voltage information change ratio or the current information change ratio is the ratio of the difference value between the previous sampling value and the current sampling value relative to the current sampling value in the preset sampling period. According to the embodiment of the invention, the technical problem of how to quickly carry out fault diagnosis in the pre-charging process is solved.

The invention relates to the technical field of chip detection, and discloses a power supply adjusting and testing system, method and device for chip post-silicon verification, a medium and a product, the system comprises a voltage regulating module, a control module and at least one detection module; each detection module is arranged on a power supply path between each power domain of the chip to be detected and the corresponding power module; the control module is in communication connection with the voltage regulating module and the detection module. The control module is used for generating a target voltage regulation signal according to the debugging and testing instruction so as to control the voltage regulation module to perform voltage bias corresponding to the target power supply domain; and when the target power data on the power supply path of the target power supply domain meets a termination condition, controlling the voltage regulating module to terminate voltage bias. By integrating the functions of voltage regulation, detection and control, a traditional external instrument is replaced, the problems that a test environment is complex to build, the power supply quality is damaged and multi-channel parallel test is limited are solved, and the test efficiency and the chip verification reliability are remarkably improved.

One example includes a circuit. The circuit includes a circuit core configured to perform an operational function and scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit generated from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data. The circuit further includes a plurality of bidirectional input / output (I / O) circuits each comprising a bidirectional I / O control and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of an I / O pad of the respective bidirectional I / O control at each shift of the set of SoC scan data via a pin parametric measurement unit (PPMU).

The invention provides a full-automatic parameter measurement system and method for a micro-cavity optical chip, and the system achieves the automatic measurement of the characteristic parameters of the micro-cavity optical chip through integrating a DFB tunable laser light source, an isolator, an EDFA amplifier, an ASE filter, a fundamental frequency light band elimination filter, a selectable beam splitter, a VOA, a PD, a main control module and other components. The system is connected with a to-be-tested chip through a specific interface, and can automatically obtain a central wavelength change curve, a transmission spectrum characteristic afterglow map and an expected soliton state intensity range of the micro-cavity optical chip at each temperature. The invention aims to automatically test the characteristic parameters of the micro-cavity optical chip so as to assist in reducing the time generated by tuning the optical frequency comb by adopting the chip, and meanwhile, an expected soliton state intensity range is given to reduce the problem of excessive tuning, so that a pre-test process required in chip application is simplified, and great convenience is brought to debugging generation of the integrated optical frequency comb.

The invention discloses a method and a system for displaying a test waveform of ATE (automatic test equipment), and belongs to the technical field of automatic test, and the method comprises the following steps: receiving a waveform display request sent by an upper computer, the waveform display request comprising a trigger condition for triggering a logic controller to store waveform digital information; triggering conditions in the waveform conversion request are set to a register address corresponding to the logic controller, a pattern program is executed, test data are sent to a tested device, and return data of the tested device are received; after the pattern program is executed, the waveform digital information is obtained from a register address corresponding to the logic controller, and the waveform digital information is all test data and return data which are started to be stored by the logic controller after a trigger condition is met; and analyzing and converting the waveform digital information, and forwarding the waveform digital information to an upper computer for waveform analog signal display. According to the application, a section of waveform at any time node is captured in real time, the time sequence problem of a pattern program is quickly positioned by comparing the captured waveform signal with the pattern time sequence, the debugging period is shortened, and the development difficulty is reduced.

Various embodiments provide a testing system for evaluating electrical wiring systems. The system can include an analyzer unit, a first adapter cable, and a second adapter cable. The analyzer unit can include an identification chip reader. The identification chip reader can be configured to read and determine the identity of an identification chip that is part of an adapter cable that is connected to the analyzer unit. Various other embodiments are also provided.

The embodiment of the invention provides a test method and device, a storage medium and electronic equipment, and relates to the technical field of computers.The method comprises the steps that a test parameter set is obtained, and the test parameter set comprises test parameters of at least one temperature condition; loss test is carried out by using the test parameter set and a first test board to obtain a limit value of link loss, and the limit value of link loss is at least used for reflecting the driving capability of a sending end chip; carrying out loss test by using the test parameter set and a first test board, comprising the following steps: adjusting the temperature of the first PCB, and determining the target temperature of the adjusted first PCB; and determining test parameters matched with the target temperature, and performing loss test by using the matched test parameters. Therefore, the link loss characteristic is changed by adopting the test parameters matched with each temperature and controlling the measurement temperature, and then the limit value of the link loss is obtained to reflect the driving capability of the sending end chip.

The invention belongs to the field of visual inspection, and particularly relates to a chip packaging multi-dimensional defect intelligent detection system which comprises a plurality of modules and a subsystem. Wherein the electric-thermal linkage detection module consists of ATE (automatic test equipment) and a thermal infrared imager, and is used for acquiring an electric parameter matrix and a thermal imaging matrix of a chip; the multi-dimensional vision detection module comprises an X-ray tomography unit, a 3D structured light imaging unit and a plane vision unit; the reconstruction module is used for reconstructing an internal structure of the chip, acquiring 3D surface topography and extracting plane defect features; the multi-modal feature fusion module is based on a cross-modal attention mechanism and a multi-task joint learning model to fuse electric-thermal data, X-ray voxel features and 3D morphology features; the hierarchical defect decision-making subsystem locates a defect area through FastR-CNN, classifies defect types through a graph convolutional network, and outputs a final defect judgment result based on Bayesian reasoning network by integrating multi-modal evidence; through multi-modal data linkage, joint detection of cavities, heat dissipation and appearance defects can be realized.

A test and measurement instrument includes an input configured to receive at least a waveform of a test signal, which includes a plurality of samples. The test and measurement instrument includes a processing circuit connected with the input. The processing circuit is configured to analyze the waveform and to select at least a subset of samples out of the plurality of samples. The subset of samples matches predefined criteria concerning at least one of bandwidth, amplitude distribution, and amplitude percentiles. The test and measurement instrument is configured to generate a modified waveform based on the selected subset of samples and / or to measure only a part of a received measurement signal from a device under test, which corresponds to the selected subset of samples. Further, a test and measurement setup and a method of measuring a device under test are described.

The invention belongs to the technical field of electronic component testing, and discloses an automatic testing system and method for a voltage reference chip. The system can be detachably connected with a voltage reference chip, can detect the voltage reference chip, and comprises a data acquisition system, an upper computer, a verification board, a programmable power supply and a coaxial anti-interference cable. The test system is provided with a data acquisition system, an upper computer, a verification board, a programmable power supply and a coaxial anti-interference cable, and can acquire reference voltages output by a voltage reference chip under different thermal environments, power supply voltages and loads, analyze and calculate whether various indexes of the voltage reference chip meet specifications or not, and determine whether the indexes of the voltage reference chip meet the specifications or not. And an automatic testing effect is achieved.

Radio frequency devices are presented that include input termination paths for use during calibration of these devices using test equipment. In one embodiment, an integrated circuit is disclosed. The integrated circuit may include an input terminal; an amplifier circuit; an input path connecting the input terminal to the amplifier circuit; and a calibration switch connected in series to a resistor to form a calibration path. In some embodiments, the calibration path is connected to the input path, and wherein the calibration switch is configured to be in a closed state during calibration of the amplifier circuit and in an open state after completion of the calibration of the amplifier circuit.

The invention discloses a high and low temperature automatic test method and system for a transmit-receive vector control module, and a medium, and belongs to the technical field of chip test. The method comprises the steps that an upper computer selects a test channel and test items and configures test parameters; the upper computer is connected with the instrument according to the test items and performs different presetting according to the test types; starting an automatic test, sending a matrix switch control instruction by the upper computer, performing switch matrix channel switching and COM port switching, and then executing SIP power-up and pole writing; executing a corresponding test process according to the test type; and after the test is completed, the SIP is powered off, poles are written, test data are stored, then whether all channels of the SIP are tested or not is judged, if not, the next channel is tested, and if all the channels are tested, all the test data are exported. Through the full-automatic testing process, manual intervention is reduced, and the testing efficiency of a production line can be greatly improved. In a high and low temperature test environment, the equipment can carry out continuous multi-channel test.

Embodiments of the present invention provide a gimbaling socket structure that uses tension to bring a device under test (DUT) disposed in the socket into secure contact with a liquid cooled thermal array or the like to cool the DUT during testing. The gimbaling socket structure is secured to a tension spring and can move freely in 3 dimensions to bring the surfaces of the DUT and the thermal array (or components thereof, such as TEC / ATI layers) into even, level, and secure contact with each other, thereby preventing air gaps between surfaces and improving thermal performance. The even, secure contact between surfaces improves thermal cooling and reduces variation in cooling efficiency. In this way, more DUTs can be tested in parallel within a small test space, overall costs of the test system are reduced, and greater cooling capacity can be provided for testing high-powered devices.

The invention relates to the technical field of chip detection, and particularly discloses an automatic test method, system and equipment for chip particles and a computer readable storage medium, the method comprises the following steps: firstly, obtaining installation cooperation parameters (including associated data and contact characteristic parameters) of a chip and test equipment, obtaining an installation cooperation index according to the installation cooperation parameters, and judging whether the installation cooperation index exceeds a threshold value or not; if not, physical distribution parameters and electrical characteristic parameters of the chip are obtained, electrical response characteristics such as time sequence delay, current ripple and power consumption fluctuation are obtained through the electrical characteristic parameters, and an electrical performance index is calculated; surface temperature and humidity distribution fields are obtained according to the physical distribution parameters, then physical energy indexes are obtained, the two indexes are fused to obtain a comprehensive performance index, whether the comprehensive performance index exceeds a preset value or not is judged, and if yes, it is judged that the chip has defects, in the process, through parameter quantification and multi-dimensional fusion, automatic comprehensive detection of the chip defects is achieved, and one-sidedness of single index judgment is avoided; the result reliability is ensured.

The invention discloses an automatic chip testing device, which belongs to the field of chip testing and comprises a working plate and supporting legs fixedly connected to the lower surface of the working plate, a mounting mechanism is mounted on the upper surface of the working plate, and a testing mechanism is mounted on one side of the upper surface of the working plate. The mounting mechanism comprises a mounting plate slidably connected to the upper surface of the working plate, and mounting grooves are formed in the upper surface of the mounting plate in a rectangular array mode. Through cooperative use of the devices, a driving motor is started according to the position of a chip body, so that a threaded rod drives an abutting spring and a bearing plate to move, the position of the chip body is finely adjusted, positioning of the chip body is more accurate, and through arrangement of a pressure sensor, the connection pressure of a pin and an elastic probe is monitored in real time, so that the accuracy of chip positioning is improved. According to the pressure setting threshold value and the electric push rod, the chip body is driven to move up and down, and the connection between the pin and the elastic probe is adjusted, so that the connection between the chip body and the elastic probe is more accurate.