565results about "Automated test systems" patented technology

The invention provides a chip performance test method and system based on automation equipment, and the method comprises the steps: connecting a to-be-tested chip to a test channel through a probe card, sampling a plurality of voltage sensor nodes in a power distribution layer of the probe card, and obtaining the voltage distribution data of a power rail; calculating power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; performing compensation control on the multi-stage parallel capacitor array on the test board according to the prediction data, and executing chip test under the control to obtain a test result and compensation control data; and correcting the test result by using the compensation control data and the voltage distribution data to obtain corrected chip performance parameters. According to the invention, accurate monitoring, prediction, active compensation and correction of the transient voltage drop of the power supply rail are realized, and the accuracy and consistency of chip performance testing are obviously improved.

The invention relates to an efficient test optimization method, system and device for chip test equipment, and the method comprises the steps: obtaining the equipment state data and test management information of the chip test equipment, carrying out the test unit division of the equipment state data based on the test management information, and obtaining the regional test information; acquiring real-time operation data of the chip test equipment, and performing matching analysis on the real-time operation data and the regional test information to obtain a real-time test task group; acquiring chip performance data acquired by the chip test equipment, performing load prediction on the regional test information to obtain a test load trend, and performing resource planning analysis with a real-time test task group to obtain an initial test scheme; performing exception identification on the chip performance data to obtain chip exception information; and performing global optimization on the initial test scheme according to the priority test sequence to obtain a global test strategy. According to the invention, fine management of different test tasks can be realized.

A test and / or measurement instrument includes at least three ports and at least three measurement circuits connected to the at least three ports, respectively. The test and / or measurement instrument further includes at least one signal generator circuit and a control circuit. The control circuit is configured to set a first calibration mode and carry out a first test of the instrument by measuring the calibration signal travelling from the signal generator circuit to the respective port as well as a signal traveling from the respective port to the signal generator circuit. The control circuit is configured to set a second calibration mode and carry out a second test of the instrument by measuring the calibration signal forwarded only to the main port in the first sub-mode and the calibration signal received by the respective port from the signal generator circuit via the main port in the first sub-mode.

The invention relates to a PCBA automatic testing system and method, and relates to the technical field of PCBA automatic testing, and the system comprises a multi-source data collection module which is used for collecting chip dynamic power consumption waveform, PCB interlayer temperature gradient, and multi-source data of signal loop impedance change, and eliminating the sampling delay error of a sensor through a synchronous collection time sequence alignment algorithm; transmitting the acquired multi-source data to a dynamic modeling engine; according to the invention, by dynamically fusing the multi-physical-quantity data and adaptively generating the test path, the system can detect the fault of the PCBA more comprehensively and accurately, the detection efficiency is improved, and the false detection rate is reduced; the thermal aging and faults of the PCB are predicted by using a dynamic modeling engine, so that potential failure risks can be found in advance, and a powerful guarantee is provided for quality control of the PCB; and the test path is automatically generated according to the dynamic modeling result and the data of the fault knowledge graph, so that the workload and error of manually planning the test path are reduced.

The embodiment of the invention discloses a test system model generation method and device, a medium and equipment, and relates to the technical field of automated tests.Third-party equipment is regarded as a special tested product for common modeling, the third-party equipment is integrated into whole test system modeling, the modeling range is expanded, the universality is enhanced, and the test system model generation efficiency is improved. After the electrical connection mode of the target third-party equipment is obtained, the number of channels of different signal types can be sorted out, the total number of signal type channels required by the test of the tested product is obtained after merging statistics, finally, a test station model is obtained after model constraint is loaded, and a test result is obtained by combining the initial modeling conditions of the tested product and the third-party equipment. According to the invention, the adapter model and the test cable model are quickly generated, the modeling of the test system is completed, and the effect of modeling the test system by the third-party equipment is improved.

The present disclosure discloses a testing system, a battery production line, and a testing method. The testing system includes a control device and a test device. The test device includes at least two probe card adjustment assemblies. The control device is connected to the test device and configured to adjust the probe card adjustment assemblies according to an adjustment strategy, and drive the adjusted probe card adjustment assemblies to test the battery module currently to be tested. The adjustment strategy is determined based on current module information corresponding to the battery module and historical module information. The historical module information is the module information of a battery module tested last time. The technical solution provided by the embodiments of the present disclosure can quickly adjust the probe card adjustment assemblies to adapt to different battery modules.

The invention discloses a method, a system and equipment for predicting the stability of integrated circuit test equipment and a medium, and belongs to the technical field of integrated circuit test. The method comprises the following steps: firstly, carrying out preprocessing and feature selection on historical data in an FT test stage, and adopting a Gaussian mixture model (GMM) to cluster and identify different operation condition clusters of a test machine; then, establishing a health state GMM reference for each working condition cluster, calculating a KL divergence value of a normal sample and the reference, and setting a dynamic anomaly detection threshold by 99.73% quantile of the KL divergence value; and finally, in real-time monitoring, calculating a KL divergence value of real-time data and a corresponding working condition cluster benchmark, and comparing the KL divergence value with a dynamic threshold value to realize accurate anomaly marking. The method effectively solves the problem of abnormal detection of the test data of the integrated circuit under complex and changeable working conditions, and improves the monitoring accuracy and working condition adaptability.

A system (100) comprising a wireless transceiver (121); an electrical wiring harness (110); and a wireless test module (120), WTM, operable to physically couple to the electrical wiring harness (110), the WTM (120) comprising a chassis (122) and a variable front end (126) connected to the chassis (122) using hot-swap connectors. The WTM (120) is operable to: wirelessly receive, using the wireless transceiver (121), a plurality of test instructions according to an automated test plan from a computer system (130); perform, using the variable front end (126), one or more tests on the electrical wiring harness (110) according to the plurality of test instructions; and wirelessly communicate, using the wireless transceiver (121), test results to the computer system (130).

The present disclosure relates to a tester, a test system, and a test method. The tester comprises a plurality of function boards, a main control module, and a co-processing module. The function boards implement different functions. The main control module is connected to the function boards and the host respectively and is configured to receive test item(s) sent by the host and send test sequences in the test item(s) to the function boards. The plurality of function boards is connected to at least one device under test, and is configured to send excitation signals to the at least one device under test according to the received test sequences, and receive response signals fed back by the at least one device under test based on the excitation signals, obtain test data, and send the test data to the co-processing module. The co-processing module is connected to the plurality of function boards respectively, and is configured to process the test data obtained by the function boards to obtain test result(s), and send them to the host. The present disclosure can improve the testing efficiency.

The invention belongs to the technical field of board card testing, and particularly relates to a board card voltage and current measurement and insulation voltage resistance testing method and system, and the method comprises the steps: starting a testing cabinet of a board card testing system, carrying out the self-inspection, and setting system parameters; a power supply is loaded according to set system parameters, and a load mode is selected according to different product requirements to provide working voltage and current for the board card; after the load mode is confirmed, voltage and current measurement and insulation voltage resistance test are carried out on the board card in a probe contact mode, and test data are transmitted to the data processing and analyzing module in real time; and the data processing module judges according to preset upper and lower limit standards after receiving the measurement and test data, and stores the data and an evaluation result to the storage unit at the same time. Through unified control and data processing, voltage and current measurement and insulation voltage resistance testing of the board card are integrated in one system, automatic board card comprehensive testing is achieved, and the accuracy and efficiency of board card comprehensive testing are improved.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention provides a microwave superheterodyne frequency sweep measurement system based on Rydberg atoms, and belongs to the technical field of microwave frequency measurement. The laser module excites detection light of 780 nm and coupling light of 480 nm, and the two beams of light are reversely input into the atomic gas chamber through the dichroscope; signal microwaves are generated by a radio frequency signal source and are radiated to the position of the atomic gas chamber through the horn antenna; local oscillation microwaves are generated by the microwave module and are also radiated to the position of the atomic gas chamber through the horn antenna; the atomic gas chamber serves as a mixer to form a difference frequency signal; the spectrum analyzer is used for monitoring low-frequency difference frequency signals generated in the frequency mixing process in real time and recording signal intensity in real time. According to the invention, high-precision and wide-band microwave frequency measurement is realized, continuous and smooth frequency sweeping response can be provided in a frequency range, and absolute frequency detection of microwave signals is realized under the condition that a complex frequency comb technology is not introduced. The hardware architecture is simplified, the automation degree is improved, and integration, popularization and application are facilitated.

Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across a range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

The invention relates to the technical field of PCBA testing devices, in particular to a production line PCBA full-automatic testing device which comprises a supporting box, a supporting frame, a pressing assembly, a detection assembly, a bearing plate and a display screen. The pressing assembly is arranged on one side of the top of the supporting frame, the detection assembly is installed on the lower side of the supporting frame, and the bearing plate is fixed to the other side of the bottom of the supporting frame. A U-shaped containing groove is formed in the bearing plate, pressing frames are arranged on the two opposite sides of the groove in a lifting mode, and pressing blocks are arranged at the four corners of the groove in an inward rotating mode. And the bottoms of the pressing frame and the pressing block are connected with a driving assembly for controlling the lifting of the pressing frame and the rotation of the pressing block. Through cooperative work of the linkage clamping mechanism and the U-shaped placement groove, rigid fixation and quick release of the PCBA board are synchronously realized in single operation, so that the offset risk caused by human force difference in the testing process is eliminated, the contact precision of a probe is ensured, an open type part taking channel is optimized, and the detection reliability and the operation practicability are improved.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention relates to the field of integrated circuit automatic test equipment, in particular to an AC calibration method and system of an ATE equipment client, and solves the problems that in the prior art, an external TDC calibration board is needed, parallel calibration cannot be achieved, and the calibration time is long in the semiconductor automatic test equipment. The AC calibration method of the ATE equipment client comprises two parts of intra-group calibration and inter-group calibration, channels are grouped through loopback board cards, intra-group AC signal sending alignment calibration and intra-group AC signal receiving alignment calibration are carried out, inter-group calibration is carried out by changing a channel connection relation, finally, multi-board card parallel calibration is achieved, and the overall calibration time is shortened.

The invention discloses a universal verification system, device and method suitable for the functional performance of an FPGA device, and relates to the technical field of FPGA device testing, the universal verification system comprises verification hardware, verification software, a verification auxiliary instrument and environment equipment, and the specific verification steps are as follows: step 1, on-chip logic function verification; step 2, common interface function verification; 3, software and hardware adaptability function verification; 4, comprehensive performance function verification; 5, dynamic power consumption testing; step 6, common IP function verification; 7, testing associated parameters; step 8, system adaptability; and step 9, environment adaptability. The universal verification system is suitable for verification of a serial interface function, a multi-path IO compatibility test function, development software platform adaptability, simulator adaptability, a configuration mode, configuration starting time, a signal processing function, official IP supportability and the like, and has functions of a high-speed interface protocol, an Aurora protocol, a DDR protocol, an IIC protocol, an SPI protocol and the like.

The invention discloses a chip testing method, device and system based on a visual waveform platform and a medium, and relates to the field of chip testing, and the method comprises the steps: obtaining an initial simulation waveform selected by a user based on a chip type; target parameters of the initial simulation waveform are extracted, an editing result input by the user is obtained, and the editing result is obtained by editing the target parameters through a visual waveform platform by the user; adjusting the initial simulation waveform based on the editing result to obtain a target simulation waveform; converting the target analog waveform into binary waveform data, and sending the binary waveform data to a hardware execution mechanism, so that the hardware execution mechanism generates an excitation signal based on the binary waveform data, and controls a digital-to-analog converter driving chip to output a response waveform through the excitation signal; and determining whether the chip passes the test according to the target simulation waveform and the response waveform. And the professional skill requirements on operators are reduced, the operation difficulty is reduced, and the test efficiency is improved.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention relates to the technical field of manufacturing process optimization, and discloses a circuit board impedance calibration method and system, and the method comprises the steps: obtaining circuit board design parameters; establishing an initial impedance model according to the circuit board design parameters; performing parameter adjustment on the initial impedance model to obtain a corrected impedance model; performing error analysis on the corrected impedance model to obtain an initial impedance predicted value; performing iterative compensation on the initial impedance predicted value to obtain an optimized impedance predicted value; judging the optimized impedance predicted value and a preset value to obtain a final impedance predicted value; testing the final impedance predicted value, calculating a test variance, and judging the variance and a preset threshold value to obtain a test result; judging according to a test result and a preset condition, and generating an impedance calibration report; according to the impedance calibration report, the circuit board production process parameters are updated, and a new circuit board production guidance file is generated. According to the method, the impedance calibration of the circuit board can be efficiently realized.

The embodiment of the invention provides a chip testing system and method.The chip testing system comprises a main control device and a measuring circuit board, the measuring circuit board comprises a chip to be tested, and a power input access of the chip to be tested is electrically connected with a measuring resistor; the main control equipment is used for sending a performance test instruction to the measurement circuit board, and the performance test instruction is used for running the chip to execute a plurality of test tasks according to a specific time sequence; the measurement circuit board is used for responding to the performance test instruction, running the to-be-tested chip to execute a plurality of test tasks, collecting working parameters of the to-be-tested chip under the plurality of test tasks, and measuring power consumption parameters of two ends of the resistor under the plurality of test tasks; and the main control equipment is also used for acquiring the working parameters and the power consumption parameters under the plurality of test tasks acquired by the measurement circuit board, and determining the performance test result of the to-be-tested chip based on the working parameters and the power consumption parameters under the plurality of test tasks, so that the accuracy and the test efficiency are improved, and the test cost is reduced.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention relates to an antenna device comprising a quad-ridged waveguide, an open end of which is configured to act as a radiating aperture, and an orthomode transducer, OMT, configured to couple the quad-ridged waveguide to two feed structures.

A method is performed by a session management module and includes the steps described below. An update instruction sent by a target test module is received; a session table is queried according to identifier information corresponding to the target test module so that a listening module identifier set corresponding to the target test module is obtained; a demand instruction is sent to a listening module corresponding to each listening module identifier in the listening module identifier set; an acquisition instruction sent by the listening module is received and the acquisition instruction is sent to the target test module so that the target test module sends shared information to the session management module; the shared information corresponding to the shared information identifier sent by the target test module is received, and the shared information corresponding to the shared information identifier is sent to the listening module.

The embodiment of the invention discloses a pre-charging loop fault diagnosis method and device and a storage medium. The method is applied to a pre-charging loop and comprises the following steps: calculating a theoretical range of an electrical parameter change ratio of the pre-charging loop according to a resistance value range of a pre-charging resistor, a capacitance value range of a capacitor and a preset sampling period; acquiring a voltage information change ratio or a current information change ratio of the pre-charging resistor at each sampling moment in the preset sampling period in an actual pre-charging process, and obtaining an actual electrical parameter change ratio of the pre-charging loop; when the actual electrical parameter change ratio is not within the theoretical range, it is judged that a fault exists in the pre-charging loop; wherein the voltage information change ratio or the current information change ratio is the ratio of the difference value between the previous sampling value and the current sampling value relative to the current sampling value in the preset sampling period. According to the embodiment of the invention, the technical problem of how to quickly carry out fault diagnosis in the pre-charging process is solved.

The invention relates to the technical field of chip detection, and discloses a power supply adjusting and testing system, method and device for chip post-silicon verification, a medium and a product, the system comprises a voltage regulating module, a control module and at least one detection module; each detection module is arranged on a power supply path between each power domain of the chip to be detected and the corresponding power module; the control module is in communication connection with the voltage regulating module and the detection module. The control module is used for generating a target voltage regulation signal according to the debugging and testing instruction so as to control the voltage regulation module to perform voltage bias corresponding to the target power supply domain; and when the target power data on the power supply path of the target power supply domain meets a termination condition, controlling the voltage regulating module to terminate voltage bias. By integrating the functions of voltage regulation, detection and control, a traditional external instrument is replaced, the problems that a test environment is complex to build, the power supply quality is damaged and multi-channel parallel test is limited are solved, and the test efficiency and the chip verification reliability are remarkably improved.

An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks using a fitting approach. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks.

The invention provides a substrate withstand voltage test device and test system, and belongs to the technical field of intelligent measurement and control, the device comprises a simulation module, a quantum control module, an energy system execution module and an emergency linkage module, the simulation device collects substrate electric field data in real time to generate a dynamic three-dimensional model; the quantum control device calculates high-precision boundary conditions based on the model; the energy system executes rapid charging and discharging or protection action according to conditions; the emergency linkage device positions a breakdown point, predicts a defect type and evaluates reliability through multiple sensors, a simulation-control-protection-diagnosis closed loop is formed, the measurement precision is increased, the efficiency of determining the breakdown point is improved, breakdown diffusion is prevented, and the misjudgment rate is reduced.

One example includes a circuit. The circuit includes a circuit core configured to perform an operational function and scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit generated from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data. The circuit further includes a plurality of bidirectional input / output (I / O) circuits each comprising a bidirectional I / O control and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of an I / O pad of the respective bidirectional I / O control at each shift of the set of SoC scan data via a pin parametric measurement unit (PPMU).