277results about "Automated test systems" patented technology

A test and / or measurement instrument includes at least three ports and at least three measurement circuits connected to the at least three ports, respectively. The test and / or measurement instrument further includes at least one signal generator circuit and a control circuit. The control circuit is configured to set a first calibration mode and carry out a first test of the instrument by measuring the calibration signal travelling from the signal generator circuit to the respective port as well as a signal traveling from the respective port to the signal generator circuit. The control circuit is configured to set a second calibration mode and carry out a second test of the instrument by measuring the calibration signal forwarded only to the main port in the first sub-mode and the calibration signal received by the respective port from the signal generator circuit via the main port in the first sub-mode.

The invention relates to a PCBA automatic testing system and method, and relates to the technical field of PCBA automatic testing, and the system comprises a multi-source data collection module which is used for collecting chip dynamic power consumption waveform, PCB interlayer temperature gradient, and multi-source data of signal loop impedance change, and eliminating the sampling delay error of a sensor through a synchronous collection time sequence alignment algorithm; transmitting the acquired multi-source data to a dynamic modeling engine; according to the invention, by dynamically fusing the multi-physical-quantity data and adaptively generating the test path, the system can detect the fault of the PCBA more comprehensively and accurately, the detection efficiency is improved, and the false detection rate is reduced; the thermal aging and faults of the PCB are predicted by using a dynamic modeling engine, so that potential failure risks can be found in advance, and a powerful guarantee is provided for quality control of the PCB; and the test path is automatically generated according to the dynamic modeling result and the data of the fault knowledge graph, so that the workload and error of manually planning the test path are reduced.

The invention discloses a method, a system and equipment for predicting the stability of integrated circuit test equipment and a medium, and belongs to the technical field of integrated circuit test. The method comprises the following steps: firstly, carrying out preprocessing and feature selection on historical data in an FT test stage, and adopting a Gaussian mixture model (GMM) to cluster and identify different operation condition clusters of a test machine; then, establishing a health state GMM reference for each working condition cluster, calculating a KL divergence value of a normal sample and the reference, and setting a dynamic anomaly detection threshold by 99.73% quantile of the KL divergence value; and finally, in real-time monitoring, calculating a KL divergence value of real-time data and a corresponding working condition cluster benchmark, and comparing the KL divergence value with a dynamic threshold value to realize accurate anomaly marking. The method effectively solves the problem of abnormal detection of the test data of the integrated circuit under complex and changeable working conditions, and improves the monitoring accuracy and working condition adaptability.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

A method is performed by a session management module and includes the steps described below. An update instruction sent by a target test module is received; a session table is queried according to identifier information corresponding to the target test module so that a listening module identifier set corresponding to the target test module is obtained; a demand instruction is sent to a listening module corresponding to each listening module identifier in the listening module identifier set; an acquisition instruction sent by the listening module is received and the acquisition instruction is sent to the target test module so that the target test module sends shared information to the session management module; the shared information corresponding to the shared information identifier sent by the target test module is received, and the shared information corresponding to the shared information identifier is sent to the listening module.

Various embodiments provide a testing system for evaluating electrical wiring systems. The system can include an analyzer unit, a first adapter cable, and a second adapter cable. The analyzer unit can include an identification chip reader. The identification chip reader can be configured to read and determine the identity of an identification chip that is part of an adapter cable that is connected to the analyzer unit. Various other embodiments are also provided.

Radio frequency devices are presented that include input termination paths for use during calibration of these devices using test equipment. In one embodiment, an integrated circuit is disclosed. The integrated circuit may include an input terminal; an amplifier circuit; an input path connecting the input terminal to the amplifier circuit; and a calibration switch connected in series to a resistor to form a calibration path. In some embodiments, the calibration path is connected to the input path, and wherein the calibration switch is configured to be in a closed state during calibration of the amplifier circuit and in an open state after completion of the calibration of the amplifier circuit.

The invention discloses an automatic chip testing device, which belongs to the field of chip testing and comprises a working plate and supporting legs fixedly connected to the lower surface of the working plate, a mounting mechanism is mounted on the upper surface of the working plate, and a testing mechanism is mounted on one side of the upper surface of the working plate. The mounting mechanism comprises a mounting plate slidably connected to the upper surface of the working plate, and mounting grooves are formed in the upper surface of the mounting plate in a rectangular array mode. Through cooperative use of the devices, a driving motor is started according to the position of a chip body, so that a threaded rod drives an abutting spring and a bearing plate to move, the position of the chip body is finely adjusted, positioning of the chip body is more accurate, and through arrangement of a pressure sensor, the connection pressure of a pin and an elastic probe is monitored in real time, so that the accuracy of chip positioning is improved. According to the pressure setting threshold value and the electric push rod, the chip body is driven to move up and down, and the connection between the pin and the elastic probe is adjusted, so that the connection between the chip body and the elastic probe is more accurate.

The invention provides an automatic test system and test method for an input board, and relates to the technical field of railway signal equipment detection application. The method comprises the following steps: the industrial control computer controls the power supply to start and perform self-inspection; the upper computer software carries out initialization setting on communication parameters and working states of the processing board unit, the IO part mainboard, the camera, the controllable power supply and the tested input board and establishes a test log; the upper computer software judges whether each test point of the tested input board is short-circuited or adhered or not, whether an indicator lamp works normally or not and whether each channel runs normally or not by controlling the short-circuit judgment module, the camera and each path of output of the tested input board; and the upper computer software generates all test results into test records and uploads the test records to the control center. According to the invention, by simulating the real working state of the input board, the automatic test of the function and performance of the input board is realized, the test efficiency and the measurement accuracy are improved, the labor intensity is reduced, and the data management is more convenient.

The invention relates to a resource board card and a test machine, and the resource board card comprises a test pattern memory which is used for storing test pattern information with different functions; the test pattern generator generates pattern data according to the test pattern information of the current target function, sends the pattern data to the time sequence module, calls the test pattern information of the read operation in the test pattern memory, generates pattern data based on the test pattern information of the read operation, and sends the pattern data to the time sequence module; receiving comparison result data obtained by processing a feedback signal for executing the read operation on the to-be-tested device by the time sequence module; the test pattern generator also reads test pattern information of a next target function from the test pattern memory after determining that the to-be-tested device completes an operation corresponding to the current target function according to the comparison result data, and the test pattern information serves as new test pattern information of the current target function to generate pattern data to be sent to the time sequence module; the waiting time can be reduced, and the test efficiency is improved.

An automated test equipment (ATE) for testing semiconductor devices, the test equipment comprises a test handler, a spare part, or a contactor socket, and a semiconductor devices tester, The spare part comprises an electronic component for storing and / or processing data regarding the spare part or a portion thereof, The test equipment comprises an operator terminal comprising a display or GUI and a data exchange interface which is connected or connectable to the electronic component within the spare part, for at least displaying data stored therein. The ATE further comprises a data buffer unit for buffering the data, a maintenance planning and control unit for planning and controlling maintenance actions of the test equipment, and a dedicated database residing in a control computer.

A test system includes a test and measurement instrument, ovens to hold devices under test (DUT), each oven having an oven switch selectably connected to the DUTs, channel switches selectably connected to the oven switches and to one channel of the instrument, one or more processors to: select an oven and its oven switch, connect that oven switch to a subset of DUTs in that oven, connect the channel switches to that oven switch to receive signals from the subset of DUTs, send the signals to channels of the instrument to acquire waveforms from the subset of DUTs in parallel, and repeat connecting of the channel switches and that oven switch until the instrument has acquired waveforms from each DUT in that oven, use machine learning to tune each DUT, test whether each DUT in that oven is optimally tuned, and repeat until all DUTs have been tuned and tested.

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

The present invention relates to an antenna device comprising a quad-ridge waveguide configured with its open ends acting as radiating apertures, and an orthogonal mode transducer (OMT) configured to couple the quad-ridge waveguide to two feed structures.

The invention relates to the technical field of chip testing, and discloses a circuit, method, device and system for measuring the voltage of a chip pin, and the circuit comprises a relay circuit which can be in a first state or a second state through a control signal; when the relay circuit is in the first state, the chip pin is directly connected with the ATE test channel through the relay circuit; the voltage division circuit is provided with a test end, a sampling end and a reference end; and when the relay circuit is in the second state, the test end is connected with the chip pin through the relay circuit, the sampling end is connected with the ATE test channel through the relay circuit, and the reference end is connected with the reference voltage. And when the relay circuit is in the second state, the voltage of the sampling end can be adjusted to a measurable range of the ATE test channel through the voltage division circuit and the reference voltage, so that the high voltage and the negative voltage exceeding the measuring range at the chip pin can be obtained through calculation.

The application provides a precise output amplification circuit, a load detection circuit and a device applying the circuit. The output amplification circuit uses an operational amplifier and a rheostat to provide a precise large current for a load to be detected by using only a single precise output unit, saves detection channel resources, reduces test cost, and simultaneously uses two selectable fast voltage detection circuits and precise voltage detection circuits, applies Kelvin four-wire method and a controller to make the detection circuit have fast detection function and high-precision detection function, and realize switching of the detection module, and fully meet the needs of different test scenarios.

The application provides a light source calibration method and device for optical chip testing and an optical chip testing system. The method comprises the following steps: obtaining a linear relationship between a light source voltage parameter and a light source brightness in a preset measurable voltage range; selecting a quasi-voltage parameter based on a preset rule, obtaining a measured value and a theoretical value of the light source brightness under the quasi-voltage parameter to obtain a variation corresponding to each quasi-voltage parameter, and judging whether each variation meets a preset accuracy requirement; taking the quasi-voltage parameter meeting the preset accuracy requirement as a calibrated light source parameter, and constructing a corresponding light source based on the calibrated light source parameter to participate in the testing of the optical chip. The application is based on the idea of the gradient descent algorithm, and stability and high efficiency are taken into account. No matter in any accuracy requirement environment, the light source calibration can be completed in a short time, the calibration frequency is low, the calibration efficiency is high, the light source calibration is accurately and efficiently realized, and the chip testing efficiency is improved.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The application provides a scan test method, comprising: constructing a single stuck-at fault scan forest, the scan forest comprising a plurality of scan inputs and a plurality of scan trees, each scan input being driven by an ATE; each pin of the ATE driving a plurality of demodulators, each demodulator driving a plurality of scan trees, each scan tree corresponding to each demodulator being controlled by different clock signals of a gate logic, each scan tree comprising a plurality of scan chains, and each scan chain comprising a plurality of scan flip-flops; and based on the constructed single stuck-at fault scan forest, placing a test. The method can effectively reduce the calculation time and memory overhead.

The invention provides a test method for testing a semiconductor device, which comprises the following steps of: executing at least one test item in a group of test items on the semiconductor device under a first environment condition; generating, by the machine learning model, an identification result based on the test results of the at least one test item, the identification result predicting at least one test result of performing one or more test items of the set of test items on the semiconductor device under a second environmental condition; and determining whether to perform one or more test items in the set of test items on the semiconductor device under a second environmental condition based on the identification result. According to the invention, based on the test result under the first environment condition, the machine learning model is utilized to predict and obtain the corresponding identification result, so that whether the test needs to be executed again under the second environment or not is determined according to the identification result.

The invention discloses a software ecological management method of automatic test equipment and application thereof, and belongs to the technical field of integrated circuit test. The method comprises the following steps: automatically writing a version identifier containing firmware information of an upper computer and a lower computer when a test program is compiled; when the program is loaded, the system obtains the actual version of the current operating environment and compares the actual version with the version identifier; if the versions are not matched, the system interrupts program execution through consistency verification and an interlocking controller, and a version switching manager is started; and the version switching manager automatically closes the current environment according to the version identifier, searches a version information base, switches the software of the upper computer, synchronously updates the firmware of the lower computer to a target version, and restores the test after the environment verification is passed. Through binding during compiling and forced verification during loading, automatic and accurate switching of the test environment is achieved, the problems that manual switching is prone to errors and software and hardware collaboration is poor are solved, and the test risk and the maintenance cost are remarkably reduced.

An electronics part verification system may comprise a test-site board loaded onto or otherwise secured to a PnP machine and computer instructions for using the PnP machine's capabilities to (i) retrieve a component-to-be-verified from a feeder; (2) move the component to a test site on the test-site board; (3) use an LCR meter to obtain an inductance, capacitance, or resistance value for the component; and (4) determine, based on the value from the LCR meter, whether the component is correct or incorrect.

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

Various embodiments provide a testing system for evaluating electrical wiring systems. The system can include an analyzer unit, a first adapter cable, and a second adapter cable. The analyzer unit can include an identification chip reader. The identification chip reader can be configured to read and determine the identity of an identification chip that is part of an adapter cable that is connected to the analyzer unit. Various other embodiments are also provided.

A chip testing system comprises a multipath selection unit comprising a plurality of input nodes and at least one output node, the plurality of input nodes are respectively coupled with a first type to-be-tested pin of a to-be-tested chip, and the output node is coupled with a testing unit, the first type to-be-tested pin is suitable for selectively coupling one of the input nodes with one of the output nodes according to a selection control signal, so that the corresponding first type to-be-tested pin is coupled with one of the output nodes; and the test unit is coupled with the multi-path selection unit and is suitable for testing the first type to-be-tested pin coupled with one of the output nodes of the multi-path selection unit. According to the technical scheme, test resources and test cost can be saved.

The present application relates to the field of integrated circuit automatic test equipment, and discloses an asynchronous execution method and system for ATE test machines.The asynchronous execution method comprises the following steps: an SDK module forms a plurality of executable tasks from test item interface instructions issued by an upper computer and stores the executable tasks in a task stack; the SDK module polls tasks in the task stack, judges the executability of the tasks and processing modules; if the tasks are executable, the SDK module further judges whether lower modules participate; according to the judgment result, the SDK module processes the tasks by itself or distributes the tasks to an ATOS module for processing or distributes the tasks to an FPGA module through the ATOS module for processing; the SDK module, the ATOS module and the FPGA module asynchronously process the assigned tasks at the same time; and after the tasks are completed, the processing results are returned to the task stack; after all subtasks of the current test item are completed, the SDK module loads tasks of the next test item until all test items are completed.