21results about "Automated test systems" patented technology

An electronics part verification system may comprise a test-site board loaded onto or otherwise secured to a PnP machine and computer instructions for using the PnP machine's capabilities to (i) retrieve a component-to-be-verified from a feeder; (2) move the component to a test site on the test-site board; (3) use an LCR meter to obtain an inductance, capacitance, or resistance value for the component; and (4) determine, based on the value from the LCR meter, whether the component is correct or incorrect.

To improve measurement speed.SOLUTION: A test and measurement device 20 receives a signal from a device 10 under test through a probe 32. One or more processors 38 generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform from a user interface device 44, select the number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system 46 to the short pattern waveforms to obtain a value for the one or more measurements, and supply the values of the one or more measurements for the waveform.SELECTED DRAWING: Figure 8

The application discloses a testing device and testing equipment, the testing device is used in combination with an oscilloscope, comprising a base, a first test module and a second test module, the first test module comprises a signal pin and a first driving assembly, the first driving assembly drives the signal pin to move, the second test module comprises a grounding pin and a second driving assembly, the second driving assembly drives the grounding pin to move; the testing equipment comprises the above testing device. In the application, the first driving assembly drives the signal pin to pierce a point at a testing position, at the same time, the grounding pin pierces a point at a suitable position of a to-be-tested member at the side of the signal pin. Since the signal pin and the grounding pin are connected with two pole bases of the oscilloscope respectively, various electrical signals at the testing point, such as voltage, current and phase difference, are shown in the form of waveforms on the oscilloscope, so that the signal waveforms of different testing points are convenient to observe, and the analysis and research of detection data are facilitated.

The present application relates to electronic mainboard detection technical field, especially electronic mainboard automatic detection equipment, including bottom plate, the upside of bottom plate is provided with lower detection mechanism, upper detection mechanism and cooperation detection mechanism, the present application sets up upper detection mechanism and cooperation detection mechanism, namely can realize the high degree of automation and flexibility of electronic mainboard detection, greatly improve the detection efficiency, reduce the dependence on manpower and operation difficulty, the cooperation frame with multifunctional positioning groove is arranged in upper detection mechanism, and important detection modules such as network card detection plugboard and display card detection plugboard are fixed on it by magnetic attraction and limiting block, so that the whole detection tooling forms a module that can be quickly replaced as a whole; when changing product model, the operator only needs to turn the locking group, the whole cooperation frame together with all detection modules on it can be taken out, and another set of modules that are pre-assembled and adjusted are replaced, without tedious screw disassembly and position calibration of individual components.

The present application relates to the technical field of chip simulation test, and discloses a lithium battery charging chip simulation test method and system, the method comprises the following steps: collecting a first signal set of a lithium battery charging chip in a first simulation test process, obtaining a first test data set through the first signal set; collecting original signal data of different models of lithium battery charging chips in a historical period, and obtaining an interference signal set in the original signal data. The present application can improve the authenticity of lithium battery charging chip simulation test, thereby improving test efficiency and accuracy. Through a multi-objective particle swarm optimization algorithm and setting a constraint condition, an optimal balance point can be found among multiple optimization targets, thereby determining an optimal optimization direction, which can ensure that the optimization direction not only brings performance improvement, but also controls cost and energy consumption within an acceptable range.

A test and / or measurement instrument includes at least three ports and at least three measurement circuits connected to the at least three ports, respectively. The test and / or measurement instrument further includes at least one signal generator circuit and a control circuit. The control circuit is configured to set a first calibration mode and carry out a first test of the instrument by measuring the calibration signal travelling from the signal generator circuit to the respective port as well as a signal traveling from the respective port to the signal generator circuit. The control circuit is configured to set a second calibration mode and carry out a second test of the instrument by measuring the calibration signal forwarded only to the main port in the first sub-mode and the calibration signal received by the respective port from the signal generator circuit via the main port in the first sub-mode.

An interface device is provided between a test head and a device under test (DUT). A front-end module includes a pin electronics circuit and a flexible printed circuit (FPC) cable. An interposer is placed on the FPC cable and forms a contact surface with the socket board. A frame is assembled to the front-end module. The frame has a reference surface and the reference surface being brought into contact with the contact surface when the frame is assembled to the front-end module. The socket board is assembled to the frame.

In some examples, a method of performing measurement of a device under test (DUT) coupled to a connector includes determining a first voltage signal representative of a current of the DUT, the current flowing through the connector. The method also includes determining a second voltage signal representative of a voltage of the DUT, as provided at the connector. The method also includes determining a calibration current according to the first voltage signal. The method also includes modifying measurement of the DUT according to the calibration current.

Embodiments according to the application comprise an automatic test equipment for testing a device under test, comprising a real-time handler interface, wherein the real-time handler interface is configured to provide a trigger signaling to a handler for triggering a temperature control function, and wherein the real-time handler interface is configured to provide a synchronization signaling to the handler for synchronizing a function of the handler other than the triggered temperature control function. Correspondingly, embodiments comprise a corresponding handler and methods for such automatic test equipment and handler.

The disclosure relates to a tester, a test control device and a test control method. The device comprises a parallel control unit and a plurality of station control units, wherein each of the station control units corresponds to at least one device under test. The parallel control unit is connected with the station control units and a host respectively and is configured to receive test items sent by the host and send each of test sequences in the test items to a station control unit corresponding to a device under test corresponding to the test sequence. Each of the station control units is connected with a plurality of function boards respectively, wherein functions realized by the function boards are different. Any station control unit of the station control units is configured to send received test sequence(s) to corresponding function boards according to functions required to realize for the received test sequence(s) so as to test device(s) under test corresponding to the received test sequence(s), and control the plurality of function boards to stop testing a target device under test when the testing of the target device under test fails, wherein the target device under test is a device under test corresponding to the any station control unit. The solutions of the disclosure can stop testing of a certain device under test.

Supply chain security for chiplets is described. In accordance with the described techniques, a chiplet manufacturing interface obtains first test results, and stores an encrypted version of the first test results in a database accessible by the chiplet manufacturing interface and a chiplet integration interface. The chiplet integration interface obtains second test results from at least one chiplet, retrieves, from the database, the encrypted version of the first test results, decrypts the encrypted version of the first test results to obtain a first hash of the first test results, and selectively integrates the at least one chiplet into an integrated circuit based on a comparison of the first test results and the second test results and a comparison of the first hash and a second hash of the second test results generated by the chiplet integration interface.

An automated test equipment comprises a tester control configured to broadcast and / or specifically upload input data and / or device specific data, including keys and / or certificates and / or IDs and / or configuration information, to a matching module. The automated test equipment further comprises a channel processing unit configured to transform the input data using the device specific data to obtain device under test adapted data for testing a device under test. The channel processing unit is further configured to process the DUT data using the device specific data to evaluate the DUT data. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

A method for performing an asynchronous automatic test-pattern generation (ATPG) by an ATPG machine includes, in part, generating a set of test patterns; detecting one or more faults associated with the set of test patterns; and receiving, from an ATPG manager, information relating to undetected faults. The method further includes, in part, updating the fault state of the ATPG machine in response to a degree of staleness of a fault state of the ATPG machine determined based at least on the information relating to the undetected faults from the ATPG manager.

The application discloses a chip testing method, device and system. The chip testing method performs protocolization on a test program through a bus protocol library. The protocolized test program meets transmission requirements of a bus protocol of a chip to be tested, so that the test program can be transmitted to the chip to be tested through a bus interface, without occupying other IO ports of the chip to be tested as test mode pins, thereby saving precious pin resources of the chip. Further, channel resources required by an ATE platform for testing a single chip are reduced, so that the ATE platform can test more chips at the same time, maximum site parallel testing is realized, and test cost is greatly reduced.

An exemplary polarity inverter includes a plurality of contactors, each of which includes a controllable switch for configuring a current path. Each of the plurality of contactors includes interleaved contacts such that a first contact receiving a voltage having a first polarity alternates with a second contact receiving a voltage having a second polarity, the first polarity being different from the second polarity. The polarity inverter also includes a first conductive plate electrically connected to each of the first contacts and a second conductive plate electrically connected to each of the second contacts. The first conductive plate and the second conductive plate are parallel. A dielectric material is interposed between the first conductive plate and the second conductive plate.

An electronics part verification system may comprise a test-site board loaded onto or otherwise secured to a PnP machine and computer instructions for using the PnP machine's capabilities to (i) retrieve a component-to-be-verified from a feeder; (2) move the component to a test site on the test-site board; (3) use an LCR meter to obtain an inductance, capacitance, or resistance value for the component; and (4) determine, based on the value from the LCR meter, whether the component is correct or incorrect.

An electronics part verification system may comprise a test-site board loaded onto or otherwise secured to a PnP machine and computer instructions for using the PnP machine's capabilities to (i) retrieve a component-to-be-verified from a feeder; (2) move the component to a test site on the test-site board; (3) use an LCR meter to obtain an inductance, capacitance, or resistance value for the component; and (4) determine, based on the value from the LCR meter, whether the component is correct or incorrect.

In various examples, Automatic Test Equipment (ATE) tests may be applied to electronic components, or devices under test (DUTs), using high-speed functional interfaces. For instance, a DUT and an ATE host device may be configured to perform one or more handshake mechanisms to optimize ATE test flows. The handshakes may be used to pause and / or resume a test interface executing on the DUT. In some examples, the ATE host device and the DUT may use one or more common data storage locations for performing the handshakes, such as system memory of the ATE host device, addressable register space of the DUT, a combination thereof, or any other shareable memory space. Additionally, the test interface of the DUT may be configured to convert packetized test data received using the high-speed functional interface to a raw data format consistent with traditional ATE test inputs received using I / O pins of the DUT.

A scan test fault analysis system is provided that selects a plurality of features from scan diagnosis report for a faulty die and processes the plurality of features through a trained artificial neural network to provide a predicted location of a fault in the faulty die.

Disclosed is a test device including a mother board and a plurality of daughter boards. The plurality of daughter boards are selectively coupled to the mother board and configured to provide a plurality of test signals from a device under test to the mother board. Each of the plurality of daughter boards includes a substrate, a socket, and a connector. The socket is mounted on the substrate and configured to output a corresponding test signal among the plurality of test signals through a first socket pin. The connector is mounted on the substrate and configured to output the corresponding test signal from the socket to the mother board through a first connector pin. Relative positions between the first connector pins and the first socket pins on the plurality of daughter boards are the same.

Embodiments according to the present application include an automatic test equipment for testing a device under test, comprising a bidirectional dedicated real-time handler interface, wherein the real-time handler interface is configured to provide a trigger signaling to a handler to trigger a temperature control function, and wherein the real-time handler interface is configured to receive a signaling from the handler, and wherein the automatic test equipment is configured to consider the signaling received from the handler. Accordingly, embodiments include a corresponding handler and method for such an automatic test equipment and handler.