Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block

Abstract

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data to be written to the one of the plurality of DUTs and a comparator circuit configured to compare data read from the one of the plurality of DUTs with test pattern data written to the one of the plurality of DUTs

Description

CROSS-REFERENCE TO RELATED APPLICATIONSRelated Applications[0001]The present application is related to U.S. patent application Ser. No. ______, filed ______, entitled “TESTER WITH MIXED PROTOCOL ENGINE IN FPGA BLOCK,” naming John Frediani and Andrew Niemic as inventors, and having attorney docket number ATST-JP0089. That application is incorporated herein by reference in its entirety and for all purposes.[0002]The present application is related to U.S. patent application Ser. No. ______, filed ______, entitled “A TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY,” naming Gerald Chan, Andrew Niemic, Eric Kushnick, and Mei-Mei Sui as inventors, and having attorney docket number ATST-JP0090. That application is incorporated herein by reference in its entirety and for all purposes.[0003]The present application is related to U.S. patent application Ser. No. ______, filed ______, entitled “GUI IMPLEMENTATIONS ON CENTRAL CONTRO...

AI Technical Summary

Benefits of technology

[0014]Accordingly, a need exists for a tester architecture that can address the problems with the systems described above. What is needed is a test architecture whereby the command and test pattern generation functionality can be transferred onto the FPGA, so that the processing load on the tester processor and

Problems solved by technology

Because the tester processor is responsible for generating the commands and test patterns, the number of DUTs that can be tested with a given ATE body is limited by the processing capabilities of the tester processor.

Unless the PCIe hardware bus adapter cards are physically substituted with car

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