770 results about "Tested time" patented technology

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention relates to the technical field of optical communication, and discloses an optical module adaptive test and rapid convergence method based on reinforcement learning, which can dynamically generate and execute an optimal test sequence for optical modules of different types or states through an off-line trained RL intelligent agent module, avoids redundant steps in a fixed process, and improves the test efficiency. On the premise of ensuring the test coverage, the test time is obviously shortened, and meanwhile, the detection probability of potential defects is improved; through the closed-loop test of the integrated RL intelligent agent module, the test action can be adjusted in real time according to the state of a single optical module, so that the test process can quickly adapt to the individual difference and process fluctuation of the device, the online quick convergence of the test strategy is realized, and the accuracy and stability of the test are guaranteed; and through online iterative optimization of the RL agent module, new data and new changes in the production process can be continuously learned, so that a test strategy is continuously evolved, and the optimal performance is kept for a long time.

The invention provides a battery process simulation test method, which comprises the following steps of: S1, inputting battery model parameters required by a second-order equivalent circuit and an initial state of a battery for pre-processing to obtain a basic second-order equivalent circuit simulation model, and introducing a series of calibration parameters on the basis of the basic second-order equivalent circuit model to obtain a simulation result of the battery model; errors are dynamically corrected in the simulation calculation process, the problem that an original model is insufficient in precision in the aspects of SOC change rate, voltage response and the like is effectively solved, and the accuracy and reliability of simulation results are remarkably improved. Aiming at complex and diversified process requirements in a battery test scene, a process simulation function supporting multiple process steps and multi-condition logic is constructed, an actual test process can be truly restored, and powerful data support is provided for process debugging, test time prediction and electric energy consumption evaluation.

A method for controlling an artificial intelligence (AI) device can include obtaining a pre-trained AI model configured to generate embeddings from input data, receiving unlabeled target data from a target domain different than a source domain used to train the pre-trained AI model, determining first parameter updates for the pre-trained AI model by performing a self-supervised adaptation process based on a correlation between a first input sample and an augmented version of the first input sample, and generating an updated AI model based on the first parameter updates. Also, the method can further include determining second parameter updates by performing a pair-wise adaptation process based on adjusting embedding representations of a pair of input samples based on a threshold to correspond to a same identity, and generating a final adapted AI model based on the second parameter updates, the final adapted AI model being adapted to the target domain.

The invention belongs to the technical field of hydraulic test and intelligent control, and particularly discloses a hydraulic component test system integrating data acquisition and automatic data analysis functions, which comprises a physical hardware test platform, a test control software platform and a digital twinborn model of a tested component, and realizes real-time interaction through an OPC UA protocol. Model parameters are corrected on line by means of measured data, and steady state, transient state and disturbance working condition tests are automatically executed based on a working condition library; and dynamically optimizing a test sequence in a test process, skipping a redundant working condition or encrypting a critical region, and synchronously generating a structured performance report. The accuracy and consistency of test results are improved, working condition simulation signals are automatically generated, performance data are collected in real time, a comprehensive performance report is generated, manual operation is reduced, the test process optimization unit can skip redundant working conditions and refine failure boundary positioning, and the test time and cost are effectively saved.

The invention relates to the technical field of electronic measurement, in particular to a multifunctional comprehensive test method and system for a direct-current power supply, and the method comprises the steps: initializing a test; a static performance test step; a dynamic performance test step: driving a direct-current electronic load module to execute a time sequence instruction sequence in the dynamic load test file, and acquiring an output voltage and an output current waveform through a high-speed data acquisition module in the execution process; a ripple noise test step: switching the high-speed data acquisition module to an alternating current coupling mode and acquiring a high-frequency noise waveform in a constant load current section in the time sequence instruction sequence; a correlation analysis step; and a test termination step: controlling the load to return to zero and closing the tested DC power supply. Through automatic configuration and test execution of the system, the complexity of manual operation is reduced, and the test efficiency is improved. And especially in a high-frequency test scene, the test time is remarkably saved through automatic execution.

The invention discloses a fault detection method and system for an SVF multi-stage full-bridge sub-module in an SLCC, and the method comprises the steps: constructing a converter valve test model which comprises a converter valve, a valve control unit and a low-pressure pressurization unit; wherein the converter valve comprises a full-bridge sub-module; based on a valve tower structure, wiring complexity and test voltage safety, performing number optimization on series connection and parallel connection of full-bridge sub-modules, and setting test power supply voltage; and based on the topological structure of the full-bridge sub-modules, performing low-voltage pressurization test on the full-bridge sub-modules by using a low-voltage pressurization unit to obtain the working states of the full-bridge sub-modules, judging faults of the full-bridge sub-modules connected in series, and positioning fault positions. According to the method, the detection efficiency of the multi-stage full-bridge sub-module is improved, all the full-bridge sub-modules of the valve tower can be rapidly and accurately detected and diagnosed only through one-time wiring, the field handover test time is shortened, and SLCC direct-current power transmission project construction is supported.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention discloses a minimum working voltage value testing method and device, a medium and equipment. The method comprises the following steps: acquiring an initial working voltage value and a preset step value of a circuit to be supplied with power; and based on the initial working voltage value and a preset step value, performing iterative calculation by using a dichotomy, and determining the minimum working voltage value of the circuit to be supplied with power. By adopting the scheme, the test time of the minimum voltage value of the normal work of the circuit can be shortened, so that the test efficiency is improved.

The invention provides a double-station radio frequency chip high-low temperature high-speed test sorting machine which comprises a test assembly, and the test assembly comprises a shell, a workbench, a preprocessor, a first air inlet pipe, a first exhaust pipe, a placing device and a detection table; the inner side wall of the shell is fixedly connected with a workbench, two preprocessors are symmetrically installed on the top of the workbench, the outer side walls of the preprocessors communicate with an air inlet pipe and an exhaust pipe, and the top of the workbench is symmetrically and fixedly connected with two detection tables. The chip is preprocessed through the preprocessor, it is ensured that the chip reaches the required test temperature before entering the detection table, and therefore the overall test time is shortened. The test cover slidably connected to the test bench facilitates rapid replacement of the test chip, and further improves the test speed. By adding the double testing stations, testing can be carried out alternately, two groups of chips can be tested at the same time, the waiting time is shortened, and the testing efficiency is improved.

The invention discloses an automobile part accelerated life test method and system, and the method comprises the steps: setting an extreme temperature cycle: setting a cycle of keeping a low temperature of-40 DEG C for 30 minutes and keeping a high temperature of 180 DEG C for 30 minutes, and setting a temperature change rate of 15 DEG C / min; a multi-physics field coupling test: in an extreme temperature cycle process, synchronously carrying out a resistance test, a withstand voltage test, a turn-to-turn insulation test, a vibration test, a humidity test and a salt spray test, and comprehensively evaluating the electrical, mechanical and environmental adaptability of the parts; multi-scale numerical simulation: establishing material-level, part-level and system-level coupling models, and predicting life distribution of parts; and data-driven optimization: based on historical test data and a numerical simulation result, establishing an acceleration model, dynamically adjusting a temperature cycle parameter and a stress level, and realizing maximization of test efficiency. Based on extreme temperature circulation (-40 DEG C / 30 minutes to 180 DEG C / 30 minutes) and multi-physical field coupling strengthening stress testing, the test time is shortened by 70% or above, and the evaluation error is smaller than or equal to + / -5%.

The invention relates to a TSN network minimization intrusive test scheduling method for guaranteeing production safety priority, which comprises the following steps: step 1, reservation of time-space isolated test resources: distributing a special test time slot with the lowest priority for test flow in a scheduling period of a centralized network controller; and step 2, a dynamic detection strategy of service awareness: monitoring key performance indexes of the key production service queue in real time, and when all the key performance indexes are lower than a preset threshold value, injecting test flow in a test time slot. And step 3, adaptive network optimization of closed loop feedback. According to the invention, on the premise of not influencing the normal operation of the key production service under the coal mine, the accurate and real-time monitoring of the TSN network state can be realized, the non-inductive test effect of the service is finally achieved, and the self-adaptive optimization capability is realized.

The invention, which relates to the technical field of phased-array antenna testing, discloses an automatic phased-array testing system comprising a vector network analysis module, an antenna horn and servo control module, a phased-array antenna module, a testing tool module and an upper computer control module. The invention also discloses a phased array automatic test method. The method comprises the following steps: preparing before testing; configuring test parameters; executing an automatic test; processing and storing test data; and finishing the test and resetting the equipment. Full-process automatic testing is achieved through the upper computer automation unit, traditional testing time is shortened, large-scale phased array batch testing is adapted, personal errors are eliminated through the testing tool, the vector network module and the servo module, data credibility is improved, operation is simplified, data are automatically stored, a report is generated, modular design is adapted to multiple types of phased arrays, and testing efficiency is improved. And the cost is reduced, the application is wide, and better use prospects are brought.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention relates to the technical field of coal mine underground geological survey, and provides a coal mine drill hole rock mechanical parameter testing system and method.The coal mine drill hole rock mechanical parameter testing system comprises a main machine; the rock parameter testing probe is electrically connected with the host machine, and the rock parameter testing probe is provided with an orientation measuring device; the end part of the push rod is connected with the rock parameter test probe, and the push rod is used for driving the rock parameter test probe to enter a test drill hole in the roadway surrounding rock; various rock mechanical parameters can be measured at the same time through one-time testing, comprehensive surrounding rock mechanical property data are provided, the testing time and cost are reduced, and the testing efficiency is improved; measurement in multiple different directions is accurately achieved in the testing process, all directions of the circumference of the drill hole can be covered, mechanical parameters of the roadway surrounding rock in different directions can be comprehensively obtained, and the overall mechanical characteristics of the surrounding rock can be reflected more truly.

The invention discloses a filling adhesive and flexible plate matching evaluation method, a sample and a manufacturing method thereof. The evaluation method comprises the following steps: manufacturing a standard sample; obtaining test conditions of the standard sample in advance; wherein the test conditions comprise test temperature, test humidity and test time; according to the test conditions, carrying out reliability test on the standard sample; and according to the standard sample subjected to the reliability test, obtaining an evaluation result of the matching of the bottom filling glue and the flexible plate. According to the method, the standard sample for evaluating the matching property of the underfill adhesive and the flexible plate is manufactured by a simple technological process, so that the evaluation of the matching reliability between the underfill adhesive and the flexible plate under the environmental influence of humidity and temperature at the same time can be conveniently realized by using the standard sample in a material selection stage, and the risk of product failure is reduced; and thus, the product yield in the production stage is improved.

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor machine control method and device, a medium and a product, and the method comprises the steps: training an initial weight prediction model according to training time sequence data until a weight prediction error is not greater than a preset target value, and obtaining a target weight prediction model; inputting the test time sequence data into the target weight prediction model, and predicting a target weight; the test time sequence data comprises process parameter time sequence data, machine state parameter time sequence data and process measurement result time sequence data; according to the predicted target weight and the actual feedback data and historical feedback data of the current batch of wafers, obtaining process parameter prediction data of the current batch of wafers; and controlling the semiconductor machine to execute the target technological process on the current batch of wafers according to the technological parameter prediction data. And at least according to the dynamic change of the actual working condition of the machine, the process parameters of the machine can be dynamically tracked and predicted in real time.

The invention relates to the technical field of automobile testing equipment, and discloses a new energy automobile chassis load testing device which comprises a testing table, a ramp is connected to one side of the surface of the testing table, electric sliding rails are symmetrically installed on the two sides of the testing table, and walking frames are slidably arranged in the electric sliding rails. Telescopic rods are arranged on the two sides, close to each other, of the walking frame, pressure detection mechanisms are arranged at the tops of the two sides of each telescopic rod correspondingly, each pressure detection mechanism comprises a mounting plate, the mounting plates are fixedly connected with the two sides of the corresponding telescopic rod correspondingly, and hanging rods are fixedly mounted on the two sides of the center of the bottom of each mounting plate; the bottom of the hanging rod is hinged to a swing arm, an extension arm is movably installed in the swing arm, and the sides, close to each other, of the extension arm are rotationally connected with a gravity roller, the driving test of various different items can be simulated, continuous running is achieved, the integration degree is high, and the test time is highly saved.

The invention discloses a large language model confidence coefficient calibration method and a confidence coefficient-based adaptive test extension method, which are used for optimizing a large language model based on a composite reward function, and the composite reward function comprises a correctness reward, a calibration reward and a reference accuracy reward. The correctness reward is determined based on the consistency of the model output answer and the real answer, the calibration reward is determined based on the matching degree of the confidence of the model output answer and the answer correctness, and the reference accuracy reward is determined based on the consistency of the answer correctness and the accuracy label of the corresponding question. Through the composite reward function, the reliability of model confidence expression can be improved while the output accuracy is ensured.

Disclosed herein are systems, devices, and methods for efficiently checking the integrity of a robot system. The integrity-checking system may generate a predefined motion instruction for a robot, where the predefined motion instruction instructs the robot to perform a random movement at a test time. The random movement may be associated with an expected observation at the test time. The integrity-checking system may also determine a systematic failure based on a difference between the expected observation and a current observation of the robot at the test time. The current observation may be determined from received sensor data, and if the integrity-checking system detects a failure, it may stop the robot's motion or other mitigating instructions.

The invention discloses an insulation resistance test method for an IGBT (Insulated Gate Bipolar Translator) module, and relates to the field of power electronic systems. The insulation resistance test method for the IGBT module comprises the following steps: determining environment variable parameters, configuring a test voltage variable, applying a test voltage to the IGBT module, recording a test time variable, and testing the voltage variable and the test time variable based on different environment variable parameters. According to the insulation resistance test method for the IGBT module, multiple voltage test variables are set, the initial voltage can be self-adapted, the strictly controlled voltage output error is matched, the absolute value of the output error does not exceed 0.5%, the leakage current is measured by adopting a four-wire method, and the current measurement error is controlled in a minimum range; the error absolute value of the current measuring instrument does not exceed 1%, and the accuracy of insulation resistance calculation is greatly improved.

The invention relates to the technical field of electrical equipment insulation tests, and discloses a medium-voltage cable variable-frequency resonance voltage-withstanding test system and a medium-voltage cable variable-frequency resonance voltage-withstanding test method. The method comprises the steps of configuring a test loop and setting related parameters, and presetting a target test voltage, test time, a system quality factor range, a local discharge capacity threshold and a current change rate threshold based on a cable model, a cable length, a laying environment temperature and an equivalent capacitance. And executing frequency scanning in a preset frequency range through an adaptive step length strategy, adjusting the step length according to the current response, identifying the resonant frequency and verifying the quality factor of the system. In the test process, the loop current change rate, the partial discharge capacity and the equipment temperature are monitored in real time, a protection mechanism is triggered according to abnormal characteristics, and insulation state diagnosis is completed. When the test is ended, voltage is reduced at a controllable rate, residual charges are dissipated, and a test report is automatically generated. The method improves the accuracy and safety of the test, and is suitable for various field conditions.

The invention provides an enhancement method for a question answering system during testing based on reinforcement learning, and belongs to the technical field of natural language processing. The method aims at solving the technical problems that an existing large language model (LLM) faces knowledge blind areas, reasoning chain breakage and context length limitation in a question and answer (QA) task, an existing fine adjustment method is high in calculation cost and damaged in generalization ability, and a prompt strategy seriously depends on a limited context window and lacks long-term memory. The method comprises the following steps: firstly, collecting reflection experience through multiple attempts and a failure reflection mechanism, and constructing an experience library; thirdly, performing text embedding, clustering and semantic abstracting on experiences in the experience library, and constructing an external memory library; secondly, a memory selection process is formalized into a Markov decision process (MDP), reinforcement learning (such as a PPO algorithm) is used for training a strategy agent, and the agent is optimized with a current task as a state, with memory item selection as an action and with LLM answer correctness as a reward; finally, in a test time (inference) phase, the agent dynamically selects the most helpful memory entry according to the new task and integrates it into the hint of the LLM to generate a final answer. According to the method, under the condition that LLM internal parameters do not need to be updated, the question and answer accuracy is dynamically improved, the calculation overhead is reduced, and the limitation of a context window is effectively overcome.

This invention discloses a shoe wear simulation test circuit and method. The shoe wear simulation test circuit includes at least an EBS controller, and the shoe wear simulation test method includes: acquiring the current test voltage, providing the current test voltage to the EBS controller, and receiving the current feedback signal output by the EBS controller; determining the current theoretical remaining wear of the shoe based on the current test voltage; determining the current tested remaining wear of the shoe based on the current feedback signal; and determining the current test result based on the current theoretical remaining wear and the current tested remaining wear. The technical solution of this invention can realize the simulation test of shoe wear detection function in a laboratory environment, with short test time and high accuracy, thus improving the reliability and safety of the braking system.

The utility model discloses an instrument quick release frame for a motorcycle simulation test stand, which comprises an instrument stand, an instrument panel and a movable support are arranged on the instrument stand, the movable support is assembled on the instrument stand in a pluggable manner, and a control module is movably arranged on the movable support. The utility model provides an instrument quick-release frame for a motorcycle simulation test bed, which can realize that a control module for adjusting the test bed is quickly assembled on an instrument frame and is quickly taken away after adjustment is completed, so that the accuracy of the test bed during test is ensured, the test can quickly enter a test stage, and the whole test time is shortened.

The invention is suitable for the technical field of semiconductor chip testing, and provides a digital signal data acquisition method and system based on chip testing, and the method comprises the steps: a semiconductor testing machine generates and issues a global trigger instruction at a time, and achieves the unified driving of multiple pins based on a digital signal sequence through a first trigger instruction facing a tested chip, starting sampling and digitization of corresponding electric signals by a second trigger instruction oriented to the data sending equipment, aggregating the electric signals according to a test session, and sending the aggregated electric signals to the data processing equipment; the data processing equipment carries out parallel calculation on the received digital signal sampling data and caches a result; and the semiconductor test machine obtains the instruction through the test result and carries out asynchronous backward reading. Therefore, control, acquisition and calculation are decoupled and can be propelled in an overlapped manner, serial waiting and instruction round-trip are reduced, the test time can be shortened, and throughput and resource utilization rate are improved.

The application provides a press-pack IGBT sub-module test adapter and a test device. The press-pack IGBT sub-module test adapter comprises a lower clamp. The lower clamp comprises: a conductive base plate, the conductive base plate having an array of positioning holes, the array of positioning holes comprising a plurality of separate positioning holes; a positioning assembly, the positioning assembly comprising a conductive adapter, the conductive adapter being adapted to be placed on the array of positioning holes, the conductive adapter being provided with a first recess, the first recess being adapted to place a to-be-tested sub-module; and a first fastener, the first fastener being adapted to penetrate the conductive adapter on the side of the first recess and extend in at least part of the positioning holes. When the structure of the to-be-tested sub-module changes, the structure of the whole adapter does not need to be redesigned, the universality of the adapter is improved, and thus the test cost is reduced and the test time is shortened.

The invention relates to the technical field of membrane scale inhibitor performance testing, in particular to a membrane scale inhibitor performance dynamic testing method and system. The operation condition of the same section of membrane element is simulated in the mode that multiple circulation periods are carried out, membrane inlet water is concentrated step by step, the frequency of a high-pressure plunger pump is reduced step by step along with the increase of the number of circulation periods so as to reduce the water inlet flow of a membrane assembly, and the recovery rate of the membrane assembly is synchronously adjusted to a proper set value in each circulation period; by monitoring turbidity data of an online turbidity meter on the membrane concentrated water side, when the turbidity of the concentrated water suddenly and abnormally rises, the scaling phenomenon can be judged to occur, a test end point is reached, and the periodic concentration cycle operation is ended. The technical problems that in the prior art, the actual membrane system operation condition cannot be simulated, the operation condition is greatly different from the actual scaling process, the experiment end point and the evaluation result are easily influenced by ion measurement errors, the operation is complex, the operation intensity is large, the reagent consumption and cost are high, and the test time is long are solved.

The invention provides a performance test method and device, a storage medium, electronic equipment and a chip, and relates to the technical field of signal processing, and the method comprises the steps: firstly generating a multi-tone signal; carrying out the performance test of the radio frequency transmitting equipment based on the generated multi-tone signal; and then determining a performance test result of the radio frequency emission equipment. According to the technical scheme, the performance of the radio frequency transmitting equipment can be accurately tested, for example, the performance of a power amplifier can be accurately tested. Compared with the test scheme of the related technology, the performance information of the radio frequency emission equipment can be obtained by inputting the multi-tone signal at one time, scanning is not needed, and the test time can be greatly shortened. Moreover, heating is low, power consumption is low, thermal damage of the device caused by overheating is avoided, and the memory effect can be obtained.

The invention discloses a solid state disk test method and device, and relates to the technical field of computers, and the method comprises the steps: generating test environment configuration information based on a test environment adaptation benchmark of a plurality of versions of solid state disks, decomposing the NVMe protocol test of the plurality of versions of solid state disks into a plurality of atomic test items, clustering the plurality of function test items to generate a test case set of the solid state disk, and identifying an actual version of the target solid state disk; and calling the corresponding test environment configuration information from the test environment configuration information to execute the corresponding multiple function test items called from the test case set, and generating a structured test result of the multiple function test items. According to the method and the device, the problems that testing mostly focuses on basic function verification, coverage on new protocol characteristics and abnormal scenes is seriously insufficient, the testing time is very long and systematic analysis cannot be performed in related technologies are solved, and the technical effects of unified testing environment, full protocol characteristic coverage, one-button automatic execution and complete engineering of structured result output are achieved.