1599 results about "Tested time" patented technology

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention relates to the technical field of automation equipment, and discloses a three-temperature test sorting machine, which is characterized in that a heat preservation cover is arranged on a workbench, and a test space is formed by the heat preservation cover and the workbench, so that the consistency of temperature in the test space can be ensured, a chip is uniformly heated in the test space, and automation of three-temperature test of the chip is realized. The temperature of the chip is adjusted in advance by additionally arranging the pre-heating device, so that the whole chip is heated more uniformly, and meanwhile, the waiting time is fully utilized to adjust the temperature in advance, so that the test time is saved, the accuracy of a chip test result and the stability of a test yield can be ensured, and the test efficiency is improved. Moreover, the test efficiency is improved, and large-scale popularization and application are facilitated.

Annotations associated with test cases written to test a software application can allow related test cases to be dynamically distributed among different sets of test cases that can be executed simultaneously in different parallel threads, thereby speeding up testing relative to executing the test cases sequentially in a single thread. The annotations can also allow test cases to be identified that are relevant to code changes, such that testing times can be further reduced by executing a subset of test cases relevant to code changes instead of a full set of test cases.

The invention relates to the technical field of information, in particular to a forming process and system of a high-precision injection hook in the technical field of injection hook forming. The forming process includes the steps that computer aided design and finite element analysis are applied, the forming process of the injection hook in a mold is simulated, the mold structure is optimized, and the mold testing frequency is reduced; a high-precision mold is integrated with a cooling channel of a preset ejection hook arrow-shaped structure, a temperature sensor is arranged in the cooling channel, the cooling state is monitored in real time, cooling parameters are adjusted based on monitoring data, and precise structure forming is achieved. And the machine vision system detects the integrity and direction consistency of the arrow-shaped structure of the molded ejection hook on line, identifies unqualified products, automatically removes the unqualified products, records defect types, and sends defect type data and corresponding product batch information to the production data acquisition module.

The invention discloses a semiconductor probe card electrical parameter extraction method and system based on an MEMS technology, and relates to the technical field of semiconductor testing, the method comprises the following components: initialization setting: aligning an MEMS probe card to a target test area on a wafer to be tested, firmly fixing the probe card and the wafer together by using a mechanical clamping device, and setting the MEMS probe card and the wafer to be tested; by integrating the decision tree model and the genetic algorithm, accurate mapping and optimization of semiconductor wafer surface features and optimal probe contact parameters are achieved, the intelligent level of testing is improved, the test time is shortened, the test efficiency is improved, and the test cost is reduced. The self-adaptability and stability of the testing process are remarkably enhanced, real-time adjustment of probe contact parameters is ensured through a dynamic monitoring and closed-loop control mechanism, the testing error is effectively reduced, the testing precision is improved, the optimal contact parameter combination is found through an optimization algorithm, the testing period is further shortened, and the testing efficiency is improved.

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention relates to the technical field of circuit assembly type selection, and particularly discloses an optimized matching circuit assembly rapid type selection method and system, which are applied to a circuit assembly characteristic database, and comprises the following steps: obtaining electrical parameter information corresponding to a plurality of candidate circuit assemblies; a virtual test model is constructed based on the electrical parameter information, virtual circuit operation is carried out based on the virtual test model, virtual operation information is generated, and the virtual operation information comprises a plurality of virtual dynamic operation parameters corresponding to a plurality of preset test time points; and obtaining operation performance information of virtual circuit operation according to the virtual operation information. According to the method, in the evaluation link, the voltage, temperature, power and other parameters are subjected to normalization processing, the multi-dimensional correlation change parameters are generated, the problem that traditional model selection neglects the component performance correlation relation is solved, the comprehensive performance of the component in a complex scene can be accurately evaluated, and a comprehensive basis is provided for model selection.

The invention discloses a photovoltaic energy storage system scheduling method, system and equipment, and the method comprises the steps: firstly, setting test time, dividing the test time into a plurality of time periods, calculating the photovoltaic end generation power of each time period, and calculating the photovoltaic end generation power of each time period; the method comprises the steps of obtaining load end electricity consumption power, exchange power between an optical energy storage system and a power grid end and energy storage end charging and discharging power in each time period, establishing an electric power balance relation, then constructing constraint conditions according to the electric power balance relation, and taking maximum photovoltaic electric energy consumption as a target function to obtain optimal energy storage power consumption. And finally, according to the constraint condition and the objective function, carrying out charging and discharging scheduling on the energy storage end of the photovoltaic energy storage system. By adopting the method, the charging and discharging scheduling of the photovoltaic energy storage system can be optimized, the dependence on the power grid is reduced, the power grid can be balanced, the stability of the power grid can be improved, and the photovoltaic consumption rate and the utilization rate of the photovoltaic energy storage system can be improved.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention discloses a DRAM (Dynamic Random Access Memory) repair method, test equipment, a storage medium and a computer program product, relates to the technical field of memory repair, and discloses the DRAM repair method, which can find and locate potential fault points in the DRAM in real time by dynamically acquiring an error unit address of the DRAM to provide an accurate target for subsequent repair work. And judging whether the error unit is really damaged or not by performing a repeated read-write test on the error unit. According to the invention, when the number of errors reported by the error unit reaches the preset number of times, it is judged that the error unit is damaged, misjudgment caused by a single test error is avoided, meanwhile, invalid or excessive tests on the damaged unit are prevented, and the test time and resources are saved. And finally, through a remapping technology, the service life of the chip is prolonged, the system shutdown risk caused by chip faults is reduced, and the stability of the DRAM is improved.

The invention discloses a steering column performance test bench and a test method thereof, and relates to the technical field of steering column performance test. The steering column performance test bench comprises a detection bench, a servo motor and a driving assembly, and is used for driving the upper surface of the detection bench to rotate. A first hydraulic rod is hinged to the mounting frame, a same connecting plate is hinged to the other end of the first hydraulic rod and the lower position of the outward side of the mounting frame, two clamping pieces are arranged on the upper side and the lower side of the outer side of the connecting plate, and the upper clamping piece and the lower clamping piece on the same side are used in cooperation and used for clamping a steering column; and the moving assembly is used for driving the mounting frame, the first hydraulic rod above the mounting frame, the clamping piece and the steering column to do horizontal reciprocating motion. According to the invention, multiple performance tests can be carried out on the same steering column in sequence, the automation degree is high, the overall test time is shortened, and the test efficiency is improved.

The invention provides a vehicle body coating filamentous corrosion testing method which comprises the following steps: destroying a coating on the surface of a test piece, exposing a metal matrix, and cleaning chips on the surface of the test piece; introducing an electrolyte solution on the metal matrix at the damaged part of the coating; placing a cover plate at the damaged part of the coating; transferring the test piece with the cover plate into an environmental test box, and setting temperature, humidity and test time; the test piece is moved out of the environment test box, washed, dried and photographed, the filiform corrosion length is measured, and the filiform corrosion risk of the plated steel is judged according to the filiform corrosion length. The method provided by the embodiment of the invention can shorten the test time.

The invention relates to the technical field of optical communication, and discloses an optical module adaptive test and rapid convergence method based on reinforcement learning, which can dynamically generate and execute an optimal test sequence for optical modules of different types or states through an off-line trained RL intelligent agent module, avoids redundant steps in a fixed process, and improves the test efficiency. On the premise of ensuring the test coverage, the test time is obviously shortened, and meanwhile, the detection probability of potential defects is improved; through the closed-loop test of the integrated RL intelligent agent module, the test action can be adjusted in real time according to the state of a single optical module, so that the test process can quickly adapt to the individual difference and process fluctuation of the device, the online quick convergence of the test strategy is realized, and the accuracy and stability of the test are guaranteed; and through online iterative optimization of the RL agent module, new data and new changes in the production process can be continuously learned, so that a test strategy is continuously evolved, and the optimal performance is kept for a long time.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a circuit board test method and device based on a flying probe tester. According to the method, a test point set is determined by obtaining a design file of a circuit board, establishing an electrical connection model and identifying components and pins on the circuit board. And generating test combination set data by analyzing the conduction relationship between the test points, and further generating test scheme data. And based on the test scheme data, a test path is generated by using a path optimization algorithm, finally, the flying probe tester is used for testing, and a test report is generated according to a test result. The flying probe tester adopts the combination of an annular probe and a sharp needle probe, the annular probe is used for a pin connector to ensure accurate contact, and the sharp needle probe is used for other types of components to improve the test precision and adaptability. Compared with a traditional test method, the test scheme can be generated more efficiently, the test path can be optimized more efficiently, the test time is remarkably shortened, and the reliability and accuracy of circuit board testing are improved.

The invention relates to the technical field of electronic component testing, in particular to an electronic component testing device which comprises a salt mist machine body, a control box installed on the surface of the salt mist machine body, an atomization equipment body and a treatment equipment body, the atomization equipment body and the treatment equipment body are arranged in the salt mist machine body, and a liquid storage tank is formed in the top of the control box; according to the device, the stability of the electronic component mounted on the surface of the PCB can be preliminarily tested while the electronic component can be ensured to be more fully contacted with salt mist, the diversity of test results can be increased within a certain test time, and the problem that when part of electronic components are subjected to corrosion resistance test in a salt mist machine at present, the test time is shortened is solved. The invention solves the problems that the batch test of the electronic component is time-consuming, the test efficiency is easily influenced, the position of the atomization equipment is stable, and the position of the electronic component is easily influenced on the test result, and solves the problem that the brine is easy to precipitate when being in the liquid storage tank for a long time.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention relates to the field of image processing, and provides a test method and device, a chip and a storage medium, and the method comprises the steps: obtaining first image data with at least one column of sub-pixels as a test column; wherein the brightness of the sub-pixels in the test column is different from the brightness of the sub-pixels in the non-test column; obtaining a target vertical resolution; generating second image data with the same target vertical resolution according to the first image data; wherein the number and the column number of the test columns in the second image data are the same as those of the first image data; and outputting the second image data to a display screen for displaying. According to the method, the first image data can be directly received, the second image data is generated and displayed on the display screen, a test chart and an external test box do not need to be manually generated to test the display screen, and the test time and the test cost are saved.

The invention relates to the technical field of textile, in particular to a textile fabric quality detection device and a method thereof.The textile fabric quality detection device comprises a test board, a top plate is arranged at the top of the test board, a fabric clamping assembly for clamping fabric is arranged above the top plate, the middle of the test board is concaved inwards to form a cavity, and a plurality of heat dissipation grooves are formed in the side face of the test board; a stretching device for driving the cloth clamping assembly to move is arranged between the test board and the top plate, and an abrasion mechanism for rubbing the cloth is further arranged on the top plate. Through cooperation of the stretching device, the transmission plate, the transmission arm, the motor, the main gear, the auxiliary gear, the torsional spring and other structures, cloth on the cloth clamping assembly is rapidly stretched in a reciprocating mode multiple times, the testing time is shortened, the influence of changes of external environment factors on cloth performance is reduced, the accuracy and reliability of testing data are improved, and the testing efficiency is improved. And the cost is greatly reduced.

The invention provides a battery process simulation test method, which comprises the following steps of: S1, inputting battery model parameters required by a second-order equivalent circuit and an initial state of a battery for pre-processing to obtain a basic second-order equivalent circuit simulation model, and introducing a series of calibration parameters on the basis of the basic second-order equivalent circuit model to obtain a simulation result of the battery model; errors are dynamically corrected in the simulation calculation process, the problem that an original model is insufficient in precision in the aspects of SOC change rate, voltage response and the like is effectively solved, and the accuracy and reliability of simulation results are remarkably improved. Aiming at complex and diversified process requirements in a battery test scene, a process simulation function supporting multiple process steps and multi-condition logic is constructed, an actual test process can be truly restored, and powerful data support is provided for process debugging, test time prediction and electric energy consumption evaluation.

The invention provides an equipment reliability test profile generation method based on a quantitative acceleration test, and relates to the technical field of acceleration tests, and the method comprises the steps: obtaining a reliability index for target equipment, and carrying out the statistics of a test scheme; according to the reliability index and the statistical test scheme, determining the total conventional test time and the reference cycle index for the target equipment; determining an acceleration stress value corresponding to the target stress according to the working limit of the target equipment for the target stress; calculating an acceleration factor of the target stress according to a reference stress value and an acceleration stress value of the target equipment for the target stress; and according to the conventional test profile, the reference stress value, the reference cycle index, the acceleration stress value, the acceleration factor and the total conventional test time of the target equipment, a reliability acceleration test profile of the target equipment is generated, and the reliability acceleration test profile is used for performing a reliability acceleration test on the target equipment for the reliability index. Therefore, the universality of the test is improved, and the test time is shortened.

The invention relates to the technical field of optical chip testing, and particularly discloses an optical chip testing system based on an FPGA (Field Programmable Gate Array), which comprises an optical chip basic performance test analysis module, an optical chip performance rating module, an optical chip stability test analysis module, an optical chip signal processing test analysis module and a database. A high-precision laser and an optical power meter are used for calibration, a photoelectric detector is connected to the output end of an optical chip, and data are collected by an FPGA after amplification and analog-to-digital conversion, so that the input and output optical signal intensity of each test time period can be accurately obtained, and an optical gain value is accurately calculated; therefore, the amplification capability of the optical chip to the optical signal intensity in different time periods can be deeply known, the efficiency and accuracy of optical chip test analysis are effectively improved, the system fault risk caused by substandard chip performance is reduced, and valuable data support is provided for further optimization design of the optical chip.

A method for controlling an artificial intelligence (AI) device can include obtaining a pre-trained AI model configured to generate embeddings from input data, receiving unlabeled target data from a target domain different than a source domain used to train the pre-trained AI model, determining first parameter updates for the pre-trained AI model by performing a self-supervised adaptation process based on a correlation between a first input sample and an augmented version of the first input sample, and generating an updated AI model based on the first parameter updates. Also, the method can further include determining second parameter updates by performing a pair-wise adaptation process based on adjusting embedding representations of a pair of input samples based on a threshold to correspond to a same identity, and generating a final adapted AI model based on the second parameter updates, the final adapted AI model being adapted to the target domain.

The invention belongs to the technical field of hydraulic test and intelligent control, and particularly discloses a hydraulic component test system integrating data acquisition and automatic data analysis functions, which comprises a physical hardware test platform, a test control software platform and a digital twinborn model of a tested component, and realizes real-time interaction through an OPC UA protocol. Model parameters are corrected on line by means of measured data, and steady state, transient state and disturbance working condition tests are automatically executed based on a working condition library; and dynamically optimizing a test sequence in a test process, skipping a redundant working condition or encrypting a critical region, and synchronously generating a structured performance report. The accuracy and consistency of test results are improved, working condition simulation signals are automatically generated, performance data are collected in real time, a comprehensive performance report is generated, manual operation is reduced, the test process optimization unit can skip redundant working conditions and refine failure boundary positioning, and the test time and cost are effectively saved.

The invention relates to the technical field of electronic measurement, in particular to a multifunctional comprehensive test method and system for a direct-current power supply, and the method comprises the steps: initializing a test; a static performance test step; a dynamic performance test step: driving a direct-current electronic load module to execute a time sequence instruction sequence in the dynamic load test file, and acquiring an output voltage and an output current waveform through a high-speed data acquisition module in the execution process; a ripple noise test step: switching the high-speed data acquisition module to an alternating current coupling mode and acquiring a high-frequency noise waveform in a constant load current section in the time sequence instruction sequence; a correlation analysis step; and a test termination step: controlling the load to return to zero and closing the tested DC power supply. Through automatic configuration and test execution of the system, the complexity of manual operation is reduced, and the test efficiency is improved. And especially in a high-frequency test scene, the test time is remarkably saved through automatic execution.

The invention discloses a Ga2O3 SBD trap test method based on forward current transient response, and belongs to the field of semiconductor device reliability. Comprising the following steps: giving a filling voltage interval and a filling time interval of a Ga2O3 SBD trap filling stage; giving a bias condition and a test time interval of a trap test stage; giving a normalization processing method and range of the forward current transient response; a characterization range of a Ga2O3 SBD device level trap time constant is given. The transient response curve of the forward current of the Ga2O3SBD under the constant test voltage is collected, and the transient current variation caused by the trap is evaluated through a normalization processing method. And repeatedly testing under the condition of multiple groups of filling voltages, establishing a time constant spectrum of the trap by using a structure function method, and extracting a time constant parameter of the trap in the Ga2O3SBD to realize in-situ and online Ga2O3SBD trap test. The method is suitable for evaluating the trap effect of Ga2O3 SBD devices from different manufacturers, and can realize spectral valuation characterization of Ga2O3 SBD traps and in-situ and nondestructive testing of trap parameters.

The invention discloses an antenna far field test system and method based on weather radar base data, and relates to the technical field of weather radar test. The transmitting antenna is mounted on the first antenna turntable and rotates along azimuth, pitching and polarization axes; an antenna to be tested and a standard horn antenna are installed on a second antenna rotary table through a radar receiver, the aperture faces of the antenna to be tested and the standard horn antenna form an included angle of 180 degrees, mechanical axes are coaxial, and the antenna to be tested and the standard horn antenna rotate along azimuth and pitch axes. The data processing device is connected with the radar receiver. The testing process is simplified, and the equipment cost and the maintenance cost are remarkably reduced. The test time is shortened, and the test precision of gain, beam width, sidelobe level and the like of the to-be-tested antenna is improved. The whole system has wider adaptability in practical application and is not limited by specific climate conditions. The test process is accelerated, and errors caused by human factors are reduced. The method has the advantages of simplicity in operation, high automation degree, high adaptability and the like, and the measurement precision and the test efficiency of antenna performance parameters are remarkably improved.

The invention discloses a test method and device of a spare power automatic switching device and electronic equipment. The method comprises the steps that a target file used for recording control parameters of the spare power automatic switching device is received, and the control parameters are used for controlling the communication function and the logic function of the spare power automatic switching device; the target file is analyzed, control parameters are obtained, a state sequence is generated according to the control parameters, the state sequence corresponds to the logic function of the spare power automatic switching device and is used for recording the states of other devices communicating with the spare power automatic switching device in a target system, and the target system is the system to which the spare power automatic switching device belongs; the spare power automatic switching device is tested according to the state sequence and the remaining control parameters, a test result is output, and the remaining control parameters are the control parameters recorded in the target file and not included in the state sequence. The technical problems of long test time and high error rate in the test process caused by manual test of the spare power automatic switching device are solved.

Disclosed is a memory array testing system based on FPGA, which is used to test a memory that has not been packaged and has not had peripheral circuits added, comprising: an FPGA, which serves as a control module for the entire testing system; an excitation source, which is used to output an operating voltage for a memory cell; a read circuit, which is used to read the resistance value of a selected memory cell; an array gating module, comprising a row gating circuit and a column gating circuit, and used to select a single memory cell in an array; an upper computer, which is used to, according to a user operation, output a pulse width and amplitude of a pulse voltage, a step time, step voltage and number of scanning points of a scanning voltage, and a control signal of a word line and a bit line of a selected memory cell, and present the resistance data received from FPGA in the form of a chart. The present invention constructs a test circuit on a PCB, effectively reducing testing time and improving testing efficiency compared with traditional probe tests, and performs prototype verification before constructing a peripheral integrated circuit for a memory array.

The invention relates to the technical field of vehicle testing, and discloses an intelligent driving vehicle testing method, device, equipment and medium, and the method comprises the steps: simulating a testing weather environment condition, and obtaining the voltage information, current information and testing time information of a power battery of a tested intelligent driving vehicle under the testing weather environment condition; on the basis of the voltage information, the current information and the test time information, determining the actual electricity consumption power and the average electricity consumption power of the tested intelligent driving vehicle, and on the basis of the actual electricity consumption power and the average electricity consumption power, determining the electricity consumption index of the power battery; and obtaining a test result of the power battery based on the power utilization index. According to the invention, the voltage information, the current information and the test time information are analyzed and judged, the performance of the power battery of the tested intelligent driving vehicle under the test weather environment condition is obtained, and the test accuracy of the tested intelligent driving vehicle can be effectively improved.