2315 results about "Tested time" patented technology

The invention discloses an electromagnetic environment simulation method and system of a display module, a medium and a product, and relates to the field of electromagnetic variable measurement, and the method comprises the steps: receiving a test identification code inputted by a user, extracting a plurality of target scenes corresponding to the test identification code from a preset scene library, and generating a scene change sequence; determining a radio frequency interference source combination and a mechanical vibration parameter corresponding to the target scene; setting test parameters of the test time periods corresponding to the multiple target scenes, and generating a dynamic test sequence; receiving a key test scene marked by a user, and adjusting a test time period and test parameters corresponding to the key test scene to obtain a target test sequence; simulating an electromagnetic environment of the target display module, and recording simulation test parameters of the target display module; the simulation test parameters comprise display brightness, contrast and response time; and determining an electromagnetic compatibility evaluation result based on the target test sequence and the simulation test parameters. According to the invention, the accuracy of an electromagnetic compatibility test result can be improved.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention relates to the technical field of automation equipment, and discloses a three-temperature test sorting machine, which is characterized in that a heat preservation cover is arranged on a workbench, and a test space is formed by the heat preservation cover and the workbench, so that the consistency of temperature in the test space can be ensured, a chip is uniformly heated in the test space, and automation of three-temperature test of the chip is realized. The temperature of the chip is adjusted in advance by additionally arranging the pre-heating device, so that the whole chip is heated more uniformly, and meanwhile, the waiting time is fully utilized to adjust the temperature in advance, so that the test time is saved, the accuracy of a chip test result and the stability of a test yield can be ensured, and the test efficiency is improved. Moreover, the test efficiency is improved, and large-scale popularization and application are facilitated.

The invention relates to the technical field of communication, in particular to an interference avoidance test method and device based on wifi equipment, and the method comprises the steps: determining a test case parameter according to a product specification parameter of to-be-tested equipment; establishing communication connection between the to-be-tested device and the networking device according to the test case parameters; obtaining a target interference signal meeting a test requirement; a target interference signal is sent to the to-be-tested device in the service transmission mode, a test response parameter of the to-be-tested device in a preset test time period is acquired, and the test response parameter is a parameter after the to-be-tested device is interfered by the target interference signal when the to-be-tested device and the networking device perform service transmission; and according to the test reaction parameter, obtaining a test result of the to-be-tested device, the test result being whether the response of the to-be-tested device to the target interference signal meets a preset interference avoidance standard. According to the method, whether the to-be-tested equipment meets the preset interference avoidance standard can be accurately evaluated, and the test accuracy and reliability are improved.

Annotations associated with test cases written to test a software application can allow related test cases to be dynamically distributed among different sets of test cases that can be executed simultaneously in different parallel threads, thereby speeding up testing relative to executing the test cases sequentially in a single thread. The annotations can also allow test cases to be identified that are relevant to code changes, such that testing times can be further reduced by executing a subset of test cases relevant to code changes instead of a full set of test cases.

The invention relates to the technical field of information, in particular to a forming process and system of a high-precision injection hook in the technical field of injection hook forming. The forming process includes the steps that computer aided design and finite element analysis are applied, the forming process of the injection hook in a mold is simulated, the mold structure is optimized, and the mold testing frequency is reduced; a high-precision mold is integrated with a cooling channel of a preset ejection hook arrow-shaped structure, a temperature sensor is arranged in the cooling channel, the cooling state is monitored in real time, cooling parameters are adjusted based on monitoring data, and precise structure forming is achieved. And the machine vision system detects the integrity and direction consistency of the arrow-shaped structure of the molded ejection hook on line, identifies unqualified products, automatically removes the unqualified products, records defect types, and sends defect type data and corresponding product batch information to the production data acquisition module.

The invention relates to the technical field of new energy power generation, in particular to a test simulation method and system based on a new energy automatic power generation control master station. AGC parameters of the new energy power plant are obtained and a model is established, wherein the AGC parameters comprise a power plant table, an AGC field group, an AGC system, a control area, a power plant controller, an AGC unit table, power plant measurement and PLC measurement; configuring parameters of an AGC master station test system, wherein the configuration parameters comprise a PLC name, a new energy power station capacity, a current power, a target power, an adjustment upper and lower limit, a test time parameter and the like; performing simulation according to the AGC modeling parameters and the configuration parameters and outputting a simulation result; and generating an AGC control instruction based on a simulation result and evaluating a dynamic performance index. Through a complete parameter modeling system and differentiated performance index evaluation, the accuracy and efficiency of the new energy AGC control test are remarkably improved, the dynamic performance of the new energy power station is accurately evaluated, and reliable technical support is provided for power grid dispatching.

The invention discloses a semiconductor probe card electrical parameter extraction method and system based on an MEMS technology, and relates to the technical field of semiconductor testing, the method comprises the following components: initialization setting: aligning an MEMS probe card to a target test area on a wafer to be tested, firmly fixing the probe card and the wafer together by using a mechanical clamping device, and setting the MEMS probe card and the wafer to be tested; by integrating the decision tree model and the genetic algorithm, accurate mapping and optimization of semiconductor wafer surface features and optimal probe contact parameters are achieved, the intelligent level of testing is improved, the test time is shortened, the test efficiency is improved, and the test cost is reduced. The self-adaptability and stability of the testing process are remarkably enhanced, real-time adjustment of probe contact parameters is ensured through a dynamic monitoring and closed-loop control mechanism, the testing error is effectively reduced, the testing precision is improved, the optimal contact parameter combination is found through an optimization algorithm, the testing period is further shortened, and the testing efficiency is improved.

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention relates to the technical field of circuit assembly type selection, and particularly discloses an optimized matching circuit assembly rapid type selection method and system, which are applied to a circuit assembly characteristic database, and comprises the following steps: obtaining electrical parameter information corresponding to a plurality of candidate circuit assemblies; a virtual test model is constructed based on the electrical parameter information, virtual circuit operation is carried out based on the virtual test model, virtual operation information is generated, and the virtual operation information comprises a plurality of virtual dynamic operation parameters corresponding to a plurality of preset test time points; and obtaining operation performance information of virtual circuit operation according to the virtual operation information. According to the method, in the evaluation link, the voltage, temperature, power and other parameters are subjected to normalization processing, the multi-dimensional correlation change parameters are generated, the problem that traditional model selection neglects the component performance correlation relation is solved, the comprehensive performance of the component in a complex scene can be accurately evaluated, and a comprehensive basis is provided for model selection.

The invention discloses a photovoltaic energy storage system scheduling method, system and equipment, and the method comprises the steps: firstly, setting test time, dividing the test time into a plurality of time periods, calculating the photovoltaic end generation power of each time period, and calculating the photovoltaic end generation power of each time period; the method comprises the steps of obtaining load end electricity consumption power, exchange power between an optical energy storage system and a power grid end and energy storage end charging and discharging power in each time period, establishing an electric power balance relation, then constructing constraint conditions according to the electric power balance relation, and taking maximum photovoltaic electric energy consumption as a target function to obtain optimal energy storage power consumption. And finally, according to the constraint condition and the objective function, carrying out charging and discharging scheduling on the energy storage end of the photovoltaic energy storage system. By adopting the method, the charging and discharging scheduling of the photovoltaic energy storage system can be optimized, the dependence on the power grid is reduced, the power grid can be balanced, the stability of the power grid can be improved, and the photovoltaic consumption rate and the utilization rate of the photovoltaic energy storage system can be improved.

The embodiment of the invention provides a chip and electronic equipment, the chip comprises a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to preset granularity; each group of chip ports is connected to at least one of a plurality of groups of first ports and a plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is used for controlling gating of a path between the chip port and the scanning test logic module by taking a preset granularity as a unit according to the control instruction. According to the embodiment of the invention, the problems of unreasonable I / O allocation and long test time of large-scale complex chips in related technologies can be solved, the degree of freedom of I / O allocation is improved by setting the granularity of I / O allocation, the I / O resources are dynamically adjusted in the test stage, and the chip test time is shortened.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention discloses a DRAM (Dynamic Random Access Memory) repair method, test equipment, a storage medium and a computer program product, relates to the technical field of memory repair, and discloses the DRAM repair method, which can find and locate potential fault points in the DRAM in real time by dynamically acquiring an error unit address of the DRAM to provide an accurate target for subsequent repair work. And judging whether the error unit is really damaged or not by performing a repeated read-write test on the error unit. According to the invention, when the number of errors reported by the error unit reaches the preset number of times, it is judged that the error unit is damaged, misjudgment caused by a single test error is avoided, meanwhile, invalid or excessive tests on the damaged unit are prevented, and the test time and resources are saved. And finally, through a remapping technology, the service life of the chip is prolonged, the system shutdown risk caused by chip faults is reduced, and the stability of the DRAM is improved.

The invention provides a digital whole-satellite-level spaceborne computer software testing system which comprises a virtual testing platform and a ground testing subsystem, the virtual testing platform is used for simulating the running state of a real satellite and space environment dynamic data, and the ground testing subsystem and the virtual testing platform conduct information interaction. And the test module is used for sending a test instruction to the virtual test platform, receiving a telemetry data packet which is fed back by the virtual test platform and contains a simulation result, executing an automatic test based on the telemetry data packet and carrying out test recording and test interpretation. Therefore, a virtuality and reality combined testing environment is established, limitation of a hardware single machine is avoided, software testing efficiency is improved, testing time is shortened, testing quality is improved, human input is reduced, testing risks are avoided, and the problem that software testing is limited by equipment, sites, environments, time and the like in the prior art is solved.

The utility model relates to a chip testing device and a chip. The chip testing device comprises a testing machine, at least two testing plates and a switching circuit board, the test machine is used for testing the to-be-tested chip at a preset temperature; the test board is used for bearing a to-be-tested chip, carrying out functional test and electrical test on the borne to-be-tested chip at different temperatures, and feeding back a test result to the test machine; the switching circuit board is connected with the test machine and the at least two test boards, a plurality of multiplexing pins are arranged on the switching circuit board, and the multiplexing pins are connected with the at least two test boards and used for transmitting test signals provided by the test machine to the at least two connected test boards in parallel. According to the chip testing device, multiple chips to be tested can be tested at the same time, the testing time is shortened, the testing efficiency is improved, the testing time cost and labor cost are reduced, the overall project progress is accelerated, and the machine utilization rate is effectively improved.

The invention discloses a steering column performance test bench and a test method thereof, and relates to the technical field of steering column performance test. The steering column performance test bench comprises a detection bench, a servo motor and a driving assembly, and is used for driving the upper surface of the detection bench to rotate. A first hydraulic rod is hinged to the mounting frame, a same connecting plate is hinged to the other end of the first hydraulic rod and the lower position of the outward side of the mounting frame, two clamping pieces are arranged on the upper side and the lower side of the outer side of the connecting plate, and the upper clamping piece and the lower clamping piece on the same side are used in cooperation and used for clamping a steering column; and the moving assembly is used for driving the mounting frame, the first hydraulic rod above the mounting frame, the clamping piece and the steering column to do horizontal reciprocating motion. According to the invention, multiple performance tests can be carried out on the same steering column in sequence, the automation degree is high, the overall test time is shortened, and the test efficiency is improved.

The invention discloses UFS equipment and a self-testing method thereof, electronic equipment and a storage medium, and relates to the technical field of UFS equipment testing. The method comprises the following steps: when a T-RX module successfully analyzes a first speed switching request frame constructed by a T-TX module based on a first target speed mode, switching a working mode of a physical layer from a current speed mode to the first target speed mode; initial feature data constructed by the T-TX module is transmitted to a data path based on a first target speed mode and then is received by the T-RX module to obtain return feature data; performing verification processing on the initial feature data and the return feature data to obtain a verification result, determining a path test condition in a first target speed mode, and completing one-time data path test; and when the verification result is correct, the next candidate speed mode is switched for testing until all the candidate speed modes are traversed, and the self-testing is ended. Self-testing can be achieved, the testing time is shortened, the testing efficiency is improved, and the testing cost is reduced.

The invention provides a vehicle body coating filamentous corrosion testing method which comprises the following steps: destroying a coating on the surface of a test piece, exposing a metal matrix, and cleaning chips on the surface of the test piece; introducing an electrolyte solution on the metal matrix at the damaged part of the coating; placing a cover plate at the damaged part of the coating; transferring the test piece with the cover plate into an environmental test box, and setting temperature, humidity and test time; the test piece is moved out of the environment test box, washed, dried and photographed, the filiform corrosion length is measured, and the filiform corrosion risk of the plated steel is judged according to the filiform corrosion length. The method provided by the embodiment of the invention can shorten the test time.

The invention relates to the technical field of optical communication, and discloses an optical module adaptive test and rapid convergence method based on reinforcement learning, which can dynamically generate and execute an optimal test sequence for optical modules of different types or states through an off-line trained RL intelligent agent module, avoids redundant steps in a fixed process, and improves the test efficiency. On the premise of ensuring the test coverage, the test time is obviously shortened, and meanwhile, the detection probability of potential defects is improved; through the closed-loop test of the integrated RL intelligent agent module, the test action can be adjusted in real time according to the state of a single optical module, so that the test process can quickly adapt to the individual difference and process fluctuation of the device, the online quick convergence of the test strategy is realized, and the accuracy and stability of the test are guaranteed; and through online iterative optimization of the RL agent module, new data and new changes in the production process can be continuously learned, so that a test strategy is continuously evolved, and the optimal performance is kept for a long time.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a circuit board test method and device based on a flying probe tester. According to the method, a test point set is determined by obtaining a design file of a circuit board, establishing an electrical connection model and identifying components and pins on the circuit board. And generating test combination set data by analyzing the conduction relationship between the test points, and further generating test scheme data. And based on the test scheme data, a test path is generated by using a path optimization algorithm, finally, the flying probe tester is used for testing, and a test report is generated according to a test result. The flying probe tester adopts the combination of an annular probe and a sharp needle probe, the annular probe is used for a pin connector to ensure accurate contact, and the sharp needle probe is used for other types of components to improve the test precision and adaptability. Compared with a traditional test method, the test scheme can be generated more efficiently, the test path can be optimized more efficiently, the test time is remarkably shortened, and the reliability and accuracy of circuit board testing are improved.

The invention relates to the technical field of precision machinery manufacturing technology, and discloses a high-efficiency wafer test probe station, which comprises a base, the upper surface of the base is fixedly connected with a loading base and a motion control system, the output end of the motion control system is fixedly connected with a microscope, the upper surface of the loading base is fixedly connected with an objective table, and the objective table is fixedly connected with the output end of the motion control system. The interior of the base is in threaded connection with a synchronous adjusting mechanism and a support protection mechanism, the top of the synchronous adjusting mechanism is fixedly connected with a probe angle adjusting mechanism, and the upper surface of the probe angle adjusting mechanism is clamped with a probe seat, so that simultaneous adjustment of a plurality of probes can be realized, the test time is shortened, and the test efficiency is improved. Adjustment is carried out according to different wafer sizes to adapt to different test scenes; the angle of the probe is adjusted by adjusting the angle of the probe seat, so that the influence of resistance on a test signal is reduced in a low-resistance test.

The invention provides a fuel cell bipolar plate coating life prediction method, and the method comprises the steps: determining a termination condition of a bipolar plate coating life test; based on the accelerated corrosion test platform and the simulated cathode potential of the fuel cell under the normal operation condition, performing an off-line real life test on the bipolar plate coating to obtain a first corresponding relation between the contact resistance and the real test time; adjusting a test condition, and performing an offline accelerated life test on the fuel cell bipolar plate coating to obtain a second corresponding relation between the contact resistance and the accelerated test time and a corresponding first accelerated test duration when the offline accelerated life test reaches a termination condition; obtaining a mapping relation between the real test time and the accelerated test time based on the first corresponding relation and the second corresponding relation; and obtaining a prediction result of the service life of the fuel cell bipolar plate coating based on the first acceleration test duration and a mapping relation between the real test time and the acceleration test time. The prediction accuracy is improved; and the prediction cost is reduced.

The invention relates to the technical field of electronic component testing, in particular to an electronic component testing device which comprises a salt mist machine body, a control box installed on the surface of the salt mist machine body, an atomization equipment body and a treatment equipment body, the atomization equipment body and the treatment equipment body are arranged in the salt mist machine body, and a liquid storage tank is formed in the top of the control box; according to the device, the stability of the electronic component mounted on the surface of the PCB can be preliminarily tested while the electronic component can be ensured to be more fully contacted with salt mist, the diversity of test results can be increased within a certain test time, and the problem that when part of electronic components are subjected to corrosion resistance test in a salt mist machine at present, the test time is shortened is solved. The invention solves the problems that the batch test of the electronic component is time-consuming, the test efficiency is easily influenced, the position of the atomization equipment is stable, and the position of the electronic component is easily influenced on the test result, and solves the problem that the brine is easy to precipitate when being in the liquid storage tank for a long time.

The invention discloses a network card testing method, device and equipment and a medium, and relates to the technical field of network card testing, the method is applied to a substrate management controller, and the method comprises the following steps: determining a link state of a network card; reading a target state register and a target state error counter in the network card in response to the condition that the link state of the network card is link connection; the target state register is used for recording the link connection state in the operation process of the network card, and the target state error counter is used for recording the number of times of abnormal link connection in the operation process of the network card; and according to the read value of the target state register and the value of the target state error counter, determining the link connection condition in the operation process of the network card. The method can shorten the test time, improve the test efficiency and reduce resource occupation.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention belongs to the technical field of power semiconductors, and relates to a dynamic on-resistance test circuit of a GaN high electron mobility transistor. The circuit comprises a UIS test circuit, a DPT test circuit, a clamping circuit and a driving circuit, and is characterized in that two semiconductor switches can gate the UIS test circuit and the DPT test circuit, UIS test and subsequent DPT test can be carried out under the condition that a device is not moved, and the introduced clamping circuit can indirectly test the conduction voltage drop of the tested device. The test circuit can be used for testing package-level device products, provides a basis for production, research and development, characteristic characterization, mass production test, reliability evaluation and application evaluation of GaN HEMT, integrates UIS and DPT test circuits together compared with a traditional test circuit, improves the test efficiency and reduces the test cost. Meanwhile, errors caused by the influence of the process and the environment on the result when the device is transferred due to the fact that the time from the application of the electric pressure to the DPT test is too long are reduced.

The invention relates to the field of image processing, and provides a test method and device, a chip and a storage medium, and the method comprises the steps: obtaining first image data with at least one column of sub-pixels as a test column; wherein the brightness of the sub-pixels in the test column is different from the brightness of the sub-pixels in the non-test column; obtaining a target vertical resolution; generating second image data with the same target vertical resolution according to the first image data; wherein the number and the column number of the test columns in the second image data are the same as those of the first image data; and outputting the second image data to a display screen for displaying. According to the method, the first image data can be directly received, the second image data is generated and displayed on the display screen, a test chart and an external test box do not need to be manually generated to test the display screen, and the test time and the test cost are saved.

The invention relates to the technical field of valve detection, and discloses a multifunctional valve testing device and a use method.The multifunctional valve testing device comprises a water tank and a base installed in the middle of the water tank through two platforms, the two platforms are located in the middle of the front side and the middle of the rear side of the base respectively, and the base is provided with annular rails; the annular track is provided with a plurality of sets of fixing bases distributed at equal intervals, the annular track drives the multiple fixing bases to conduct fixed-distance conveying, the fixing bases circularly move around the end face of the base, and the positions of the fixing bases are switched in a reciprocating mode. The annular track can drive the fixed base to conduct fixed-distance conveying, so that the position of the workbench and the position of the multifunctional valve on the workbench can be automatically switched according to a set program. In the testing process, the valve can sequentially pass through a plurality of stations such as air inflation, water entry vibration, bubble detection and air pressure re-detection, the valve does not need to be manually and frequently carried, the testing efficiency is greatly improved, meanwhile, the detection time is prolonged, and the detection result is improved.