5199 results about "Tested time" patented technology

A medical characterization system is configured to input medical-related continuous parameters and discrete data so as to calculate a characterization timeline indicative of a physiological condition of a living being. A data source is in sensor communications with a patient so as to generate a continuous parameter. The data source also provides test data responsive to the patient at a test time. The test data is available to a characterization processor at a result time. The characterization processor is also responsive to the continuous parameter so as to generate a medical characterization as a function of time. A characterization analyzer enables the characterization processor to update the medical characterization in view of the test data as of the test time.

The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog / RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.

An in-band OTDR uses a network's communication protocols to perform OTDR testing on a link. Because the OTDR signal (probe pulse) is handled like a data signal, the time required for OTDR testing is typically about the same as the time required for other global network events, and is not considered an interruption of service to users. A network equipment includes an optical time domain reflectometry (OTDR) transmitter and receiver, each operationally connected to a link to transmit and receive, respectively, an OTDR signal. When an OTDR is to be performed, a network device operationally connected to the link actuates the OTDR transmitter to transmit the OTDR signal on the link during a determined test time based on a communications protocol of the link, during which data signals are not transmitted to the network equipment. A processing system processes the OTDR signal to provide OTDR test results.

The invention discloses a prediction method for a life cycle of a battery. The prediction method comprises the following steps: drawing a curve of the number of discharge and capacity fading rate; determining a function model of the capacity fading rate Qloss of the battery and the number of discharge N of the battery; substituting data of a certain impact factor impacting the life of the battery into the function model, wherein Qloss is 50-80 percent of the nominal capacity of the battery; calculating to obtain the expected cycle period N of the battery. According to the prediction method disclosed by the invention, as long as little cyclic test is performed on the battery, the residual life of the battery can be judged, and therefore, the test time is greatly shortened and the test cost is greatly reduced; the objective condition of capacity fading during the actual use process of the battery can be truly and comprehensively described, the life and the residual life of the battery can be obtained, the performance of the battery can be helped to be determined, and the life of the battery is prolonged. As the established model is universal, the prediction method disclosed by the invention is suitable for establishing life fading models of various storage batteries.

A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip. The apparatus, servicing a plurality of internal scan chains wherein the number of said internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, includes: a) logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs, and converting the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values provided by the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit position at a time; wherein a first plurality of the input data words supplied to the primary inputs produce a second plurality of expanded data words that are loaded into the internal scan chains to achieve an improved test coverage.

The invention discloses a automatic chip testing method, which is characterized by comprising the steps that: the system is powered on, and initialization is completed; the configuration is carried out, a test thread needs to be started is determined according to chip types, and an instrument transceiving end is configured; a test command is generated, test items and test parameter setting in a chip integrated test case configuration file are read and analyzed, and a command frame is generated and transmitted to a single-board system through a communication interface; and the command is analyzed, and setting and testing steps are carried out. The automatic chip testing method can achieve the automatical test and data storage of chips, can be used for testing the chips quickly, is high in test efficiency, saves test time to a certain extent, can achieve the purposes of automatic configuration of a tested DUT chip, automatic configuration of instruments, automatic recovery of test results and automatic generation of test reports, automatic generation of test case reports and automatic switching of test cases through the development of an automatic chip testing platform.

The tester comprises: a clamp (22) to fix the upper sample (23) on its arc groove above the lower sample (25) connected to the middle of supporting shaft (37) by a flat key, a oil bath (26) to accommodate part (25), and a pressure bearing (20) with outside circle contacted to the upper arc surface of (22). This invention can protect the failure condition, and cuts wear test time.

The invention relates to a rock sample detection and data acquisition system. The system can realize elastic parameter test of a rock sample in the state of gas adsorption; in the system, a three-shaft pressure cabin is connected with a gas supply and metering control device for absorbing samples in the cabin and accurately metering absorption quantity, moreover, an ultrasonic transducer is installed on a cap of the (high) pressure cabin and integrated with an ultrasonic wave transmitting / receiving device so that the test of elastic parameters of methane absorption on coal can be realized truly. The system can automatically and continuously test in the processes of gas absorption and gas enrichment, thereby ensuring a consistent test environment, acquiring an absorption quantity and elastic parameter relation curve, improving test accuracy and efficiency and saving test time and cost. The rock sample detection and data acquisition system integrates methane enrichment mechanism simulation and rock physical property test, can be applied to seismic prospecting method research on coalbed methane and shale gas, mine advanced detection, coal mine safety research and the like.

A gear transmission monitoring method includes: forming a good operating condition baseline matrix by, for each of a plurality of different gear mesh frequencies, obtaining a good operating condition signal indicative of gear transmission conditions over a segment of time and transforming the obtained good operating condition signal into a good operating condition time-frequency spectrum; and then obtaining a gear mesh frequency and a test signal over a segment of time, transforming the obtained test signal into a test time-frequency spectrum, and using the gear mesh frequency and the good operating condition baseline matrix to examine the test time-frequency spectrum to monitor gear transmission conditions.

An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and / or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.

The invention relates to a method for predicting the life of a solid tantalum electrolytic capacitor, which comprises the following steps of: 1, collecting current degradation data; 2, determining a degradation track model and a degradation accelerating model; 3, extrapolating the degradation track model to obtain the pseudo-failure life of each sample; 4, performing hypothesis test of pseudo-life distribution and the estimation of unknown parameters; 5, determining the relation of population parameters of the pseudo-life distribution and a stress level; 6 estimating the population parameters of the life distribution of a tantalum capacitor under the normal stress by extrapolating; and 7, determining the average life and reliability curve of the tantalum capacitor. The method has novel concept and simple programs and does not need life tests, the test time can be shorted, the test cost can be saved, and the problem of disharmony between the prediction of the conventional life and engineering is solved, so the method has wide application prospect in the technical field of life prediction.

A system and method for continuous online safety and reliability monitoring is disclosed. The method includes the steps of obtaining operating information about at least one of a plurality of instrumented function components, which are part of an instrumented function, and determining a probability of failure on demand for the instrumented function based on the operating information. In variations, operating information includes status information, which may be received from and / or provided to an asset management application. In some variations, instantaneous probability of failure on demand, online mean time to failure (MTTF), and online safety integrity level (SIL) are also calculated for an instrumented function. In yet further variations, the system allows a user to predict probability of failure on demand values into the future based on hypothetical and / or future planned test times.

The system comprises a control execution module used for testing, and also comprises a monitor-controlling module, a control data collection module, a monitor database module, a procedure strategy configuration module, a user-informing module. Wherein, the monitor-controlling module communicates with the execution-controlling module to monitor the test process; the control data collection module is used for collecting the test data, analyzing execution result and controlling the control execution module to adjust the test sequence according to the procedure strategy defined by user.

A new digital architecture for metallic pipe and cable locators, providing accurate estimation of the fundamental locate parameters, electromagnetic signal strength and signal direction, and utilizing a nested Digital Phase-Locked Loop (DPLL) structure is disclosed. The obstacles to signal direction measurement in low SINR environments using the signal select method are overcome and a more precise phase comparison between the carrier and the FM modulation signals is obtained. The architecture further significantly reduces analog front-end hardware requirements, offers wider resistance to component tolerances, lower calibration and test time, and provides flexible frequency selectivity. Locators according to the present invention provide accurate estimation of the fundamental physical parameters of line location (electromagnetic signal strength and signal direction) in extremely noisy environments, using Digital Signal Processing (DSP) methods.

There is provided a dynamic burn-in test equipment being capable of testing a large number of multi-pin LSI chips in a short test time and at a low cost. The dynamic burn-in test equipment includes at least a thermostatic oven for storing DUTs, a driving unit for applying the input signal to the input terminal of each DUT to apply a predetermined expected value to the output terminal of each DUT, a power supply for applying a predetermined power supply voltage to each DUT through a higher level power supply line and a lower level power supply line (ground line), and a current detector arranged on at least one of the higher level power supply line and the lower level power supply line (ground line). The dynamic burn-in test equipment monitors a power supply current to detect a failure.

A handler is configured by, separably and connectably, a plurality of types of handling modules of different throughputs and a plurality of types of test modules of different numbers of simultaneous measurements and / or test temperatures. Based on the maximum number of measurable pins of the tester outputting a test pattern and examining a response pattern, the number of terminals of the DUTs, and the test time, the throughput of the handling module and the number of simultaneous measurements and / or test temperature of the test module are selected and combined.

Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.

The invention discloses a method for constructing driving condition of an electric vehicle, which can solve the problem that the conventional driving conditions cannot accurately evaluate various performance indexes and energy consumption of the electric vehicle, establishes a driver best travel manner model based on urban road network information and daily traffic flow, establishes a calculationmethod and an allocation rule of the sample capacity required for a test, and plans a test route accordingly, and determines the test time. A large amount of experimental data is obtained by using GPS / IMU equipment. According to the working characteristics of an electric motor of the electrical vehicle and its operating characteristics in urban roads, the rules of data preprocessing and data analysis are formulated. Finally, the driving condition of the electric vehicle is constructed based on the Markov-static Monte Carlo simulation method.

The invention discloses an embedded satellite-borne fault-tolerant temperature control system and a verification method thereof. The system comprises a satellite management computer, an on-satellite temperature control system and a ground monitoring and fault injection computer; the on-satellite temperature control system comprises a temperature control calculation host machine, a temperature control calculation standby machine and an environmental simulation computer; and the temperature control calculation host machine and the temperature control calculation standby machine are temperature control computers. The verification method comprises the following steps of: 1, initializing a file allocation; 2, initializing the system; 3, beginning simulation; 4, injecting and executing a fault; 5, processing redundant fault tolerance; 6, monitoring the ground and evaluating the fault; and 7, evaluating a fault model and a redundancy strategy of the temperature control system. The fault injection and the verification process of the whole running stage of the real satellite-borne temperature control system are completely realized; and the method is simple, convenient and reliable, and greatly reduces the test time and expense for the practical system.

A system and method for continuous online safety and reliability monitoring is disclosed. The method includes the steps of obtaining operating information about at least one of a plurality of instrumented function components, which are part of an instrumented function, and determining a probability of failure on demand for the instrumented function based on the operating information. In variations, instantaneous probability of failure on demand, online mean time to failure (MTTF), and online safety integrity level (SIL) are also calculated for an instrumented function. In other variations of the invention, alarms are reported to an operator based on the variance indicating the probability of failure on demand for the instrumented function is too high. In yet further variations, the system allows a user to predict probability of failure on demand values into the future based on hypothetical and / or future planned test times.

The invention relates to a high-speed dynamic simulation test method used for an electric mainshaft bearing. The electric mainshaft bearing comprises a frame, a main body pedestal, an axial loading cylinder, a test head assembly, a main body gland, a radial loading cylinder, a shaft coupling, a protecting hood, an electric mainshaft, a lubricating oil pipe, an axial loading oil pipe, a vibration sensor, a radial loading oil pipe and a temperature sensor and also a final assembly of all the parts. A hydraulic loading system is started to provide pressure oil to the axial loading cylinder and the radial loading cylinder, the electric mainshaft drives a test mainshaft to rotate, the radial loading cylinder exerts radial force on a first test accompanying bearing and a second test accompanying bearing through a radial loading sleeve, and the radial loading cylinder exerts axial force on a first test bearing and a second test bearing through an axial loading sleeve. The entire test is controlled by a computer to display parameters of the rotating speed, the axial load and the radial load, the oil pressure, the cooling water temperature, the bearing temperature, the bearing vibration, the power current of the electric mainshaft and the test time, and the parameters are saved in a computer database and analyzed.

The invention discloses a prediction method for the q-precentile life of an intelligent meter and relates to the technical field of reliability estimation of accelerated degradation data. The method comprises the following steps: performing degradation path modeling according to test data, and obtaining the pseudo life estimation of the intelligent meter under all stress levels according to the failure threshold value of given parameters; building a Weibull distribution-based accelerated degradation model of three parameters, such as temperature, humidity and electrical stress according to the pseudo life estimation results of the intelligent meter under all stress levels of an accelerated degradation test, so as to obtain the point estimation and covariance estimation of the acceleration model; and obtaining the lower estimation of parameter service life of the intelligent meter under a given reliability degree and a given confidence degree in normal use conditions according to the point and covariance matrix of the parameters of the accelerated degradation model. Due to the adoption of the method, the test time is effectively shortened, the test expense is reduced, and the quick and accurate estimation of a stable period of an accelerometer is realized.

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

The invention discloses a high-performance flat-type cellulose acetate / graphene blend forward osmosis membrane. 5 to 25 percent by weight of cellulose acetate, 1 to 15 percent by weight of additives, 0.01 to 2 percent by weight of graphene and mixed solvent of dimethylformamide, dimethylacetamide, or N-methylpyrrolidone and acetone are added into a dissolving tank according to a given sequence and are stirred and dissolved for 2 to 18 hours at the temperature of 5 to 75 DEG C to be uniformly mixed so as to prepare a forward osmosis membrane casting solution; the high-performance flat-type cellulose acetate / graphene blend forward osmosis membrane is prepared on a supporting material by adopting a phase inversion method. According to the forward osmosis membrane, 1M NaCl is used as a driving liquid, the deionized water is used as a raw material solution, the flux of pure water of the forward osmosis membrane is more than 21L / m<2> within the test time of one hour, and the salt flux in the reverse direction is less than 3.5g / m<2>.

A detached island effect test method and a device based on active frequency deviation relate to a test method and a device to test distributive new energy grid integration power supply, in particular to a detached island effect test method and a device based on active frequency deviation. Regarding the utility model, 25 cyclic waves form a major cycle. Chopped wave rate cf of the first 15 cyclic waves is 0, and variance trend of the frequency is tested. Under the circumstance that frequency tends to rise, frequency disturbance with the chopped wave rate of cf is added in the grid frequency in the last ten cyclic waves, and initial value cfmax of the chopped wave rate cf is positive. Under the circumstance that the frequency tends to reduce, frequency disturbance with the chopped wave rate of cf is added in the grid frequency in the last ten cyclic waves, and initial value cfmin of the chopped wave rate cf is negative. By adopting the invention, not only the operation probability of the detached island tested is improved; but also testing time is reduced, and current harmonics injected into the grid is reduced.

Techniques are provided for use by implantable medical devices for controlling ventricular pacing using a multi-pole left ventricular (LV) lead. In one example, a single “V sense” test is performed to determine intrinsic interventricular conduction time delays (Δn) between the RV electrode and each of the LV electrodes of the multi-pole lead. Likewise, a single “RV pace” test is performed to determine paced interventricular conduction time delays (IVCD_RLn) between the RV electrode and each of the LV electrodes. A set of “LV pace” tests is then performed to determine paced interventricular conduction time delays (IVCD_LRn) between individual LV electrodes and the RV electrode. Optimal or preferred interventricular pacing delays are determined using the intrinsic interventricular conduction delay (Δn) values and a set of interventricular correction terms (εn) determined from the results of the RV pace test and the set of LV pace tests. With these techniques, overall test time can be reduced.

A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.

The invention discloses a test device of a model for manufacturing rock masses containing interlayers and a test method thereof. The test device of the model for manufacturing the rock masses containing interlayers comprises a semicircular angle device, an upper baffle, a lower baffle, a left side plate, a right side plate, a circular turntable, a core-drilling machine drill bit, a flat plate, a flat plate angle control rod, a fixed screw rod, a base plate, an interlayer model test piece, a U-shaped plate and a guide slot. The test method comprises the following test steps: arranging the rock masses according to an outline central line and fixing the rock masses; manufacturing interlayer materials and casting the model, fastening the test piece, drilling the core, replacing the core-drilling machine drill bit, changing the position of the test piece to drill repeatedly and cutting to obtain the test pieces with different height-diameter ratios or obtain the test pieces with different interlayer inclination angles; then carrying out mechanical test. The test device is simple in structure and suitable for manufacturing the test pieces with different interlayer thicknesses, inclination angles and height-diameter ratios; according to a core-drilling and cutting machining device, by making full use of the existing device, the influence on the mechanical properties of the test pieces caused by different conditions can be analyzed, coring of irregular rock samples taken in the site can be carried out directly, so that the test efficiency is improved and the test time is shortened.