459 results about "Tested time" patented technology

The invention relates to the technical field of optical communication, and discloses an optical module adaptive test and rapid convergence method based on reinforcement learning, which can dynamically generate and execute an optimal test sequence for optical modules of different types or states through an off-line trained RL intelligent agent module, avoids redundant steps in a fixed process, and improves the test efficiency. On the premise of ensuring the test coverage, the test time is obviously shortened, and meanwhile, the detection probability of potential defects is improved; through the closed-loop test of the integrated RL intelligent agent module, the test action can be adjusted in real time according to the state of a single optical module, so that the test process can quickly adapt to the individual difference and process fluctuation of the device, the online quick convergence of the test strategy is realized, and the accuracy and stability of the test are guaranteed; and through online iterative optimization of the RL agent module, new data and new changes in the production process can be continuously learned, so that a test strategy is continuously evolved, and the optimal performance is kept for a long time.

The invention belongs to the technical field of hydraulic test and intelligent control, and particularly discloses a hydraulic component test system integrating data acquisition and automatic data analysis functions, which comprises a physical hardware test platform, a test control software platform and a digital twinborn model of a tested component, and realizes real-time interaction through an OPC UA protocol. Model parameters are corrected on line by means of measured data, and steady state, transient state and disturbance working condition tests are automatically executed based on a working condition library; and dynamically optimizing a test sequence in a test process, skipping a redundant working condition or encrypting a critical region, and synchronously generating a structured performance report. The accuracy and consistency of test results are improved, working condition simulation signals are automatically generated, performance data are collected in real time, a comprehensive performance report is generated, manual operation is reduced, the test process optimization unit can skip redundant working conditions and refine failure boundary positioning, and the test time and cost are effectively saved.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention, which relates to the technical field of phased-array antenna testing, discloses an automatic phased-array testing system comprising a vector network analysis module, an antenna horn and servo control module, a phased-array antenna module, a testing tool module and an upper computer control module. The invention also discloses a phased array automatic test method. The method comprises the following steps: preparing before testing; configuring test parameters; executing an automatic test; processing and storing test data; and finishing the test and resetting the equipment. Full-process automatic testing is achieved through the upper computer automation unit, traditional testing time is shortened, large-scale phased array batch testing is adapted, personal errors are eliminated through the testing tool, the vector network module and the servo module, data credibility is improved, operation is simplified, data are automatically stored, a report is generated, modular design is adapted to multiple types of phased arrays, and testing efficiency is improved. And the cost is reduced, the application is wide, and better use prospects are brought.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention discloses a filling adhesive and flexible plate matching evaluation method, a sample and a manufacturing method thereof. The evaluation method comprises the following steps: manufacturing a standard sample; obtaining test conditions of the standard sample in advance; wherein the test conditions comprise test temperature, test humidity and test time; according to the test conditions, carrying out reliability test on the standard sample; and according to the standard sample subjected to the reliability test, obtaining an evaluation result of the matching of the bottom filling glue and the flexible plate. According to the method, the standard sample for evaluating the matching property of the underfill adhesive and the flexible plate is manufactured by a simple technological process, so that the evaluation of the matching reliability between the underfill adhesive and the flexible plate under the environmental influence of humidity and temperature at the same time can be conveniently realized by using the standard sample in a material selection stage, and the risk of product failure is reduced; and thus, the product yield in the production stage is improved.

The invention relates to the technical field of automobile testing equipment, and discloses a new energy automobile chassis load testing device which comprises a testing table, a ramp is connected to one side of the surface of the testing table, electric sliding rails are symmetrically installed on the two sides of the testing table, and walking frames are slidably arranged in the electric sliding rails. Telescopic rods are arranged on the two sides, close to each other, of the walking frame, pressure detection mechanisms are arranged at the tops of the two sides of each telescopic rod correspondingly, each pressure detection mechanism comprises a mounting plate, the mounting plates are fixedly connected with the two sides of the corresponding telescopic rod correspondingly, and hanging rods are fixedly mounted on the two sides of the center of the bottom of each mounting plate; the bottom of the hanging rod is hinged to a swing arm, an extension arm is movably installed in the swing arm, and the sides, close to each other, of the extension arm are rotationally connected with a gravity roller, the driving test of various different items can be simulated, continuous running is achieved, the integration degree is high, and the test time is highly saved.

The invention discloses a large language model confidence coefficient calibration method and a confidence coefficient-based adaptive test extension method, which are used for optimizing a large language model based on a composite reward function, and the composite reward function comprises a correctness reward, a calibration reward and a reference accuracy reward. The correctness reward is determined based on the consistency of the model output answer and the real answer, the calibration reward is determined based on the matching degree of the confidence of the model output answer and the answer correctness, and the reference accuracy reward is determined based on the consistency of the answer correctness and the accuracy label of the corresponding question. Through the composite reward function, the reliability of model confidence expression can be improved while the output accuracy is ensured.

The invention relates to the technical field of electrical equipment insulation tests, and discloses a medium-voltage cable variable-frequency resonance voltage-withstanding test system and a medium-voltage cable variable-frequency resonance voltage-withstanding test method. The method comprises the steps of configuring a test loop and setting related parameters, and presetting a target test voltage, test time, a system quality factor range, a local discharge capacity threshold and a current change rate threshold based on a cable model, a cable length, a laying environment temperature and an equivalent capacitance. And executing frequency scanning in a preset frequency range through an adaptive step length strategy, adjusting the step length according to the current response, identifying the resonant frequency and verifying the quality factor of the system. In the test process, the loop current change rate, the partial discharge capacity and the equipment temperature are monitored in real time, a protection mechanism is triggered according to abnormal characteristics, and insulation state diagnosis is completed. When the test is ended, voltage is reduced at a controllable rate, residual charges are dissipated, and a test report is automatically generated. The method improves the accuracy and safety of the test, and is suitable for various field conditions.

The invention provides an enhancement method for a question answering system during testing based on reinforcement learning, and belongs to the technical field of natural language processing. The method aims at solving the technical problems that an existing large language model (LLM) faces knowledge blind areas, reasoning chain breakage and context length limitation in a question and answer (QA) task, an existing fine adjustment method is high in calculation cost and damaged in generalization ability, and a prompt strategy seriously depends on a limited context window and lacks long-term memory. The method comprises the following steps: firstly, collecting reflection experience through multiple attempts and a failure reflection mechanism, and constructing an experience library; thirdly, performing text embedding, clustering and semantic abstracting on experiences in the experience library, and constructing an external memory library; secondly, a memory selection process is formalized into a Markov decision process (MDP), reinforcement learning (such as a PPO algorithm) is used for training a strategy agent, and the agent is optimized with a current task as a state, with memory item selection as an action and with LLM answer correctness as a reward; finally, in a test time (inference) phase, the agent dynamically selects the most helpful memory entry according to the new task and integrates it into the hint of the LLM to generate a final answer. According to the method, under the condition that LLM internal parameters do not need to be updated, the question and answer accuracy is dynamically improved, the calculation overhead is reduced, and the limitation of a context window is effectively overcome.

This invention discloses a shoe wear simulation test circuit and method. The shoe wear simulation test circuit includes at least an EBS controller, and the shoe wear simulation test method includes: acquiring the current test voltage, providing the current test voltage to the EBS controller, and receiving the current feedback signal output by the EBS controller; determining the current theoretical remaining wear of the shoe based on the current test voltage; determining the current tested remaining wear of the shoe based on the current feedback signal; and determining the current test result based on the current theoretical remaining wear and the current tested remaining wear. The technical solution of this invention can realize the simulation test of shoe wear detection function in a laboratory environment, with short test time and high accuracy, thus improving the reliability and safety of the braking system.

The invention is suitable for the technical field of semiconductor chip testing, and provides a digital signal data acquisition method and system based on chip testing, and the method comprises the steps: a semiconductor testing machine generates and issues a global trigger instruction at a time, and achieves the unified driving of multiple pins based on a digital signal sequence through a first trigger instruction facing a tested chip, starting sampling and digitization of corresponding electric signals by a second trigger instruction oriented to the data sending equipment, aggregating the electric signals according to a test session, and sending the aggregated electric signals to the data processing equipment; the data processing equipment carries out parallel calculation on the received digital signal sampling data and caches a result; and the semiconductor test machine obtains the instruction through the test result and carries out asynchronous backward reading. Therefore, control, acquisition and calculation are decoupled and can be propelled in an overlapped manner, serial waiting and instruction round-trip are reduced, the test time can be shortened, and throughput and resource utilization rate are improved.

The application provides a press-pack IGBT sub-module test adapter and a test device. The press-pack IGBT sub-module test adapter comprises a lower clamp. The lower clamp comprises: a conductive base plate, the conductive base plate having an array of positioning holes, the array of positioning holes comprising a plurality of separate positioning holes; a positioning assembly, the positioning assembly comprising a conductive adapter, the conductive adapter being adapted to be placed on the array of positioning holes, the conductive adapter being provided with a first recess, the first recess being adapted to place a to-be-tested sub-module; and a first fastener, the first fastener being adapted to penetrate the conductive adapter on the side of the first recess and extend in at least part of the positioning holes. When the structure of the to-be-tested sub-module changes, the structure of the whole adapter does not need to be redesigned, the universality of the adapter is improved, and thus the test cost is reduced and the test time is shortened.

The invention relates to the technical field of membrane scale inhibitor performance testing, in particular to a membrane scale inhibitor performance dynamic testing method and system. The operation condition of the same section of membrane element is simulated in the mode that multiple circulation periods are carried out, membrane inlet water is concentrated step by step, the frequency of a high-pressure plunger pump is reduced step by step along with the increase of the number of circulation periods so as to reduce the water inlet flow of a membrane assembly, and the recovery rate of the membrane assembly is synchronously adjusted to a proper set value in each circulation period; by monitoring turbidity data of an online turbidity meter on the membrane concentrated water side, when the turbidity of the concentrated water suddenly and abnormally rises, the scaling phenomenon can be judged to occur, a test end point is reached, and the periodic concentration cycle operation is ended. The technical problems that in the prior art, the actual membrane system operation condition cannot be simulated, the operation condition is greatly different from the actual scaling process, the experiment end point and the evaluation result are easily influenced by ion measurement errors, the operation is complex, the operation intensity is large, the reagent consumption and cost are high, and the test time is long are solved.

The invention provides a performance test method and device, a storage medium, electronic equipment and a chip, and relates to the technical field of signal processing, and the method comprises the steps: firstly generating a multi-tone signal; carrying out the performance test of the radio frequency transmitting equipment based on the generated multi-tone signal; and then determining a performance test result of the radio frequency emission equipment. According to the technical scheme, the performance of the radio frequency transmitting equipment can be accurately tested, for example, the performance of a power amplifier can be accurately tested. Compared with the test scheme of the related technology, the performance information of the radio frequency emission equipment can be obtained by inputting the multi-tone signal at one time, scanning is not needed, and the test time can be greatly shortened. Moreover, heating is low, power consumption is low, thermal damage of the device caused by overheating is avoided, and the memory effect can be obtained.

The invention provides a method for extracting NBIT activation energy from a single PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), which comprises the following steps of: respectively applying NBIT stress under constant voltage to the PMOSFET at different temperatures according to a stress time sequence, monitoring a change dynamic state of a transfer characteristic curve-along with the time sequence at different temperatures, respectively threshold voltage from the transfer characteristic curve-, obtaining a delta degradation dynamic state in a temperature rise process, and extracting the NBIT activation energy from the single PMOSFET. The stress time for generating the delta degradation dynamic state at other temperatures except the initial temperature is converted into the equivalent stress time for generating the delta degradation dynamic state at the initial temperature, and the multiple equivalent stress times are added to obtain the relation of delta-accumulated equivalent stress time; the value enabling the delta-accumulated equivalent stress time to fall on the extension line of the equivalent stress time of the delta-initial temperature is calculated, and a single PMOSFET is used for testing, so that the influence of the consistency difference among a plurality of devices on the activation energy can be avoided, and the result is accurate; and meanwhile, all degradation data are obtained on a single PMOSFET sample, so that the test time is short, and the extraction efficiency of NBIT activation energy and the utilization rate of the sample are improved.

The invention discloses a rapid OTA testing method and system for a satellite communication terminal, relates to the technical field of satellite communication testing, and solves the technical problems that the OTA testing time of the satellite terminal is too long, the efficiency is extremely low, and the industrial large-scale testing requirement is difficult to meet. The method comprises the following steps: establishing signaling connection between a satellite simulator and a to-be-tested terminal, and closing ephemeris consistency verification and position verification functions of the to-be-tested terminal; respectively configuring reference positions of the to-be-tested terminal and the target satellite through the satellite simulator to obtain a plurality of optimized test scenes; generating a test signal containing ephemeris information of the target satellite based on the plurality of test scenes; and selecting a target test scene from the optimized test scene and the standard test scene to carry out OTA performance test on the to-be-tested terminal, and closing an uplink filling function of the to-be-tested terminal in the OTA receiving performance test process. According to the method, the OTA test time of the satellite communication terminal is remarkably shortened, the test efficiency is improved, and the large-scale test requirement is met.

The utility model relates to and discloses a compaction die for testing the compaction density of powder. Relates to the technical field of new energy batteries. The device specifically comprises a lower base, an upper pressing seat, an inner sleeve and a top pressing column, a cavity with openings in the top and the bottom is formed in the upper pressing seat, the lower base is connected with the bottom of the upper pressing seat and used for sealing the opening in the bottom of the cavity, the inner sleeve is inserted into the cavity and used for filling powder, and the top pressing column is inserted into the inner sleeve and used for compacting the powder. The inner sleeve is arranged in the cavity of the upper pressing seat, powder is loaded in the inner sleeve, the powder in the inner sleeve is compacted through downward pressing of the top pressing column, the inner sleeve is detachable in the cavity of the upper pressing seat, and by replacing the inner sleeve, the accuracy of powder compaction density testing can be improved, the testing time can be saved, and the testing efficiency is improved. The test efficiency is improved.

The utility model discloses a handrail swing durable tool which comprises a bottom plate and a cross beam, the cross beam is fixed on the bottom plate, a swing mechanism is arranged on the bottom plate, a force sensor is hinged to the swing mechanism, and a connecting mechanism is arranged on the force sensor. A simulated handrail is arranged on the cross beam, and after a detected hanging ring is fixed between the connecting mechanism and the simulated handrail through cooperation of the connecting mechanism and the simulated handrail, the detected hanging ring of the handrail is driven to swing through the swing mechanism; the tool further comprises a control system capable of controlling the tool, and the swing mechanism and the force sensor are in electric signal connection with the control system. According to the utility model, the tested armrest hanging ring can be automatically swung, the test time is greatly shortened, the cost is reduced, the bearing capacity of the tested armrest hanging ring can be monitored and displayed in real time, and the test result is ensured to be accurate and reliable.

The present application belongs to the technical field of lithium ion battery detection, and particularly relates to a winding core short circuit test parameter optimization method, device and computer equipment. The winding core short circuit test parameter optimization method comprises the following steps: constructing a defect winding core sample library; taking voltage, plane pressure and test time as cooperative optimization parameters, performing full-factor experiments on the defect winding core sample library and normal control samples under different parameter combinations, obtaining a defect detection rate data set and a normal winding core damage rate data set; taking a defect detection rate not lower than a first threshold value and a normal winding core damage rate not higher than a second threshold value as an optimization target, determining an optimal parameter combination; and introducing the optimal parameter combination into a production line for trial operation verification, and determining final target test parameters according to a verification result. The present application solves the technical problems in the prior art, such as test parameter setting depending on experience, lacking systematic verification, not considering the key role of pressure parameters and being unable to balance high detection rate and zero damage rate.

The application provides a method for extracting NBTI activation energy from a single PMOSFET, wherein NBTI stress under a constant voltage is applied to the PMOSFET at different temperatures according to a stress time sequence, a transfer characteristic curve is monitored, a dynamic change of the transfer characteristic curve with time at different temperatures is monitored, a threshold voltage is obtained from the transfer characteristic curve, a delta degradation dynamic in a temperature rising process is obtained, stress time for generating the delta degradation dynamic at temperatures other than an initial temperature is converted into equivalent stress time for generating the delta degradation dynamic at the initial temperature, a plurality of equivalent stress times are added to obtain a relationship of delta cumulative equivalent stress time, a value is calculated to make the delta cumulative equivalent stress time fall on an extension line of the equivalent stress time at the initial temperature, the single PMOSFET test can avoid the influence of consistency difference between a plurality of devices on the activation energy, and the result is accurate; meanwhile, all degradation data are obtained on the single PMOSFET sample, the test time is short, and the extraction efficiency of the NBTI activation energy and the utilization rate of the sample are improved.

The invention provides a reliability test structure and a reliability test method. The reliability test structure comprises a semiconductor substrate; the dielectric layer covers the semiconductor substrate; the at least one first test structure and the at least one second test structure are located in the dielectric layer; the first test structure comprises a first metal layer, a second metal layer and a first through hole layer; and the second test structure comprises a third metal layer, a fourth metal layer and a second through hole layer. According to the reliability test structure, electromigration, dielectric breakdown and voltage slope test structures are integrated through 3D design, electromigration and dielectric breakdown / voltage slope test structures can be tested in the same area in sequence, the position of a wafer does not need to be moved, the test process is simplified, and meanwhile the test efficiency is improved. The electromigration test / dielectric breakdown test, the electromigration test / voltage ramp test and the dielectric breakdown test / voltage ramp test are carried out in parallel, so that the overall reliability test time is greatly shortened. In addition, by means of the design, the wafer area occupied by the testing structure is saved, and the wafer utilization rate is increased.

The application discloses a test method for CTOD resistance curve of high-grade pipeline steel, and relates to the technical field of pipeline steel, in particular to a test method for CTOD resistance curve of high-grade pipeline steel. The application discloses a test method for CTOD resistance curve of high-grade pipeline steel, which comprises the following steps: sample processing is performed on the material to be tested; the sample is selected through sample processing; the temperature of the sample is controlled within a set range by a testing machine; a pre-crack is made on the sample according to the length of the sample; a CTOD test is performed through a multi-sample method to obtain data points meeting the requirements; and the experimental data points are fitted to obtain a fitting curve. The test method provided by the application can quickly and accurately determine the displacement values of each point in the CTOD resistance curve, save a large amount of test time, standardize the test method for the CTOD resistance curve, and enable the test results of the CTOD resistance curve obtained by each laboratory to be directly compared.

The invention discloses an integrated circuit testing machine with a material stacking prevention function and a testing system, and the integrated circuit testing machine comprises a testing head and a host. The integrated circuit testing machine is used for cooperating with the classifier. And the test head is used for placing the tested object on the classifier and taking back the tested object by the classifier. The host is used for executing a test program on the tested object through the test head and providing a first instruction to enable the classifier to operate in a replacement stage. In the replacement stage, the classifier firstly executes the retrieval program and then executes the placement program so as to be replaced with another tested object. Wherein the host is used for executing the residual test program through the test head in the replacement stage, and generating a second instruction for stopping the operation of the classifier when the tested object is left on the test head. Therefore, the problem of material stacking caused by the abnormality of the classifier can be solved without increasing the test time.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

This application provides a method, electronic device, and storage medium for online power monitoring of photovoltaic modules. The method includes: constructing verification conditions; determining a valid test time based on pre-established verification conditions (string operating status verification, irradiance integer value verification, and irradiance stability verification); real-time power correction of the module based on the measured irradiance and cell temperature at the valid test time; determining the online power test value based on the corrected power value under the same integer irradiance reference value; when the integer irradiance reference value reaches a preset high irradiance threshold, correcting the online power test value to standard test conditions to obtain a comparable online power test value; determining the current control reference for the current test cycle based on its corresponding factory power correction value; and updating the dynamic iterative control reference based on the current control reference and historical control references to perform power anomaly monitoring. This application achieves accurate online testing and anomaly identification of photovoltaic module power.

The invention discloses an inspection method for rapidly processing a wire rod metallographic specimen, and belongs to the technical field of metallographic detection. The invention provides an inspection method for rapidly processing a wire rod metallographic specimen in order to solve the problems of inconvenience in specimen processing operation marking, long inspection time, material mixing and material loss during hook-by-hook sampling inspection of a wire rod bearing steel rolling body product. The method comprises the steps of incoming material acceptance check, sample sorting, sample processing, metallographic sample preparation and microscopic examination, an auxiliary device is made of 45 # steel and is of a cuboid structure of 390mm * 75mm * 50mm, circular grooves are formed in the upper surface of the auxiliary device and are arranged in the width direction of the auxiliary device, every two circular grooves form one group, and ten groups of circular grooves are arranged; the diameter of each circular groove is 30 mm, the depth of each circular groove is 30 mm, and the gap between every two adjacent circular grooves is 5 mm. By adding an auxiliary device and a new technological process method, one-person operation can be reduced, the processing time is shortened by half, the probability of sample mixing and losing is 0%, and the accuracy and the efficiency of hook-by-hook inspection of the wire rod are greatly improved.

The invention relates to the technical field of semiconductor device testing, in particular to a method and a system for quickly predicting the service life of a GaN device. The method comprises the following steps: acquiring physical structure attributes and use scene information of a GaN device to be tested; determining key working condition parameters and corresponding target stress conditions based on the physical structure attributes and the use scene information; based on the target stress condition, performing an adaptive composite accelerated stress test on the to-be-tested GaN device to obtain a degradation fingerprint vector; constructing joint probability distribution of the key working condition parameters based on use scene information; and constructing a life prediction model, and obtaining life distribution of the to-be-tested GaN device by using the life prediction model based on the degradation fingerprint vector and the joint probability distribution. The problem that in the prior art, rapid prediction of the service life of a GaN device is not accurate enough is solved. Through combination of the device structure and scene information, self-adaptive acceleration testing and modeling, the testing time is reduced, and the accuracy of GaN device life prediction is improved at the same time.

The utility model discloses a server cabinet based on artificial intelligence, and relates to the technical field of server cabinets, the server cabinet comprises a cabinet body, the inner side of the cabinet body is provided with a support assembly, and the support assembly is used for providing support operation for a notebook computer used when an intelligent server is detected and tested; the supporting assembly comprises a concave frame, a sliding groove, a front end check block, a supporting tray and a limiting round block. According to the utility model, through the arrangement of the supporting assembly, when an intelligent server needs to be detected and tested through a notebook computer, the supporting tray is pulled out, and the positioning clamping blocks on the inclined supporting arms are clamped into the positioning clamping grooves, so that stable supporting of the supporting tray is realized, and the moved-out supporting tray can provide a stable placement position for the notebook computer; therefore, the convenience of detection and test operation of the intelligent server is effectively improved.

The utility model discloses an electrophoretic coating bumping test device for a laboratory, which comprises a bumping test device body, and the top and the bottom of the bumping test device body are both provided with round holes capable of being opened; and the handle lever device is inserted from the round hole which can be formed in the bottom of the bump test device body, penetrates out of the round hole which can be formed in the top of the bump test device body, and is fixed. According to the device, the adjustment design of different variables is integrated in one bump test device, so that two different test objects of workpieces and sample plates with different sizes, a certain number of steel balls with needles with different masses and test time can be realized through simple and convenient adjustment; problems existing in a visual method for testing the scratch resistance of the coating at the present stage are solved by screening proper electrophoresis product models, and finally a product evaluation model is optimized to improve a formula.