1219 results about "Tested time" patented technology

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention relates to the technical field of circuit assembly type selection, and particularly discloses an optimized matching circuit assembly rapid type selection method and system, which are applied to a circuit assembly characteristic database, and comprises the following steps: obtaining electrical parameter information corresponding to a plurality of candidate circuit assemblies; a virtual test model is constructed based on the electrical parameter information, virtual circuit operation is carried out based on the virtual test model, virtual operation information is generated, and the virtual operation information comprises a plurality of virtual dynamic operation parameters corresponding to a plurality of preset test time points; and obtaining operation performance information of virtual circuit operation according to the virtual operation information. According to the method, in the evaluation link, the voltage, temperature, power and other parameters are subjected to normalization processing, the multi-dimensional correlation change parameters are generated, the problem that traditional model selection neglects the component performance correlation relation is solved, the comprehensive performance of the component in a complex scene can be accurately evaluated, and a comprehensive basis is provided for model selection.

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

The invention discloses a steering column performance test bench and a test method thereof, and relates to the technical field of steering column performance test. The steering column performance test bench comprises a detection bench, a servo motor and a driving assembly, and is used for driving the upper surface of the detection bench to rotate. A first hydraulic rod is hinged to the mounting frame, a same connecting plate is hinged to the other end of the first hydraulic rod and the lower position of the outward side of the mounting frame, two clamping pieces are arranged on the upper side and the lower side of the outer side of the connecting plate, and the upper clamping piece and the lower clamping piece on the same side are used in cooperation and used for clamping a steering column; and the moving assembly is used for driving the mounting frame, the first hydraulic rod above the mounting frame, the clamping piece and the steering column to do horizontal reciprocating motion. According to the invention, multiple performance tests can be carried out on the same steering column in sequence, the automation degree is high, the overall test time is shortened, and the test efficiency is improved.

The invention relates to the technical field of optical communication, and discloses an optical module adaptive test and rapid convergence method based on reinforcement learning, which can dynamically generate and execute an optimal test sequence for optical modules of different types or states through an off-line trained RL intelligent agent module, avoids redundant steps in a fixed process, and improves the test efficiency. On the premise of ensuring the test coverage, the test time is obviously shortened, and meanwhile, the detection probability of potential defects is improved; through the closed-loop test of the integrated RL intelligent agent module, the test action can be adjusted in real time according to the state of a single optical module, so that the test process can quickly adapt to the individual difference and process fluctuation of the device, the online quick convergence of the test strategy is realized, and the accuracy and stability of the test are guaranteed; and through online iterative optimization of the RL agent module, new data and new changes in the production process can be continuously learned, so that a test strategy is continuously evolved, and the optimal performance is kept for a long time.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention provides a battery process simulation test method, which comprises the following steps of: S1, inputting battery model parameters required by a second-order equivalent circuit and an initial state of a battery for pre-processing to obtain a basic second-order equivalent circuit simulation model, and introducing a series of calibration parameters on the basis of the basic second-order equivalent circuit model to obtain a simulation result of the battery model; errors are dynamically corrected in the simulation calculation process, the problem that an original model is insufficient in precision in the aspects of SOC change rate, voltage response and the like is effectively solved, and the accuracy and reliability of simulation results are remarkably improved. Aiming at complex and diversified process requirements in a battery test scene, a process simulation function supporting multiple process steps and multi-condition logic is constructed, an actual test process can be truly restored, and powerful data support is provided for process debugging, test time prediction and electric energy consumption evaluation.

The invention provides an equipment reliability test profile generation method based on a quantitative acceleration test, and relates to the technical field of acceleration tests, and the method comprises the steps: obtaining a reliability index for target equipment, and carrying out the statistics of a test scheme; according to the reliability index and the statistical test scheme, determining the total conventional test time and the reference cycle index for the target equipment; determining an acceleration stress value corresponding to the target stress according to the working limit of the target equipment for the target stress; calculating an acceleration factor of the target stress according to a reference stress value and an acceleration stress value of the target equipment for the target stress; and according to the conventional test profile, the reference stress value, the reference cycle index, the acceleration stress value, the acceleration factor and the total conventional test time of the target equipment, a reliability acceleration test profile of the target equipment is generated, and the reliability acceleration test profile is used for performing a reliability acceleration test on the target equipment for the reliability index. Therefore, the universality of the test is improved, and the test time is shortened.

A method for controlling an artificial intelligence (AI) device can include obtaining a pre-trained AI model configured to generate embeddings from input data, receiving unlabeled target data from a target domain different than a source domain used to train the pre-trained AI model, determining first parameter updates for the pre-trained AI model by performing a self-supervised adaptation process based on a correlation between a first input sample and an augmented version of the first input sample, and generating an updated AI model based on the first parameter updates. Also, the method can further include determining second parameter updates by performing a pair-wise adaptation process based on adjusting embedding representations of a pair of input samples based on a threshold to correspond to a same identity, and generating a final adapted AI model based on the second parameter updates, the final adapted AI model being adapted to the target domain.

The invention belongs to the technical field of hydraulic test and intelligent control, and particularly discloses a hydraulic component test system integrating data acquisition and automatic data analysis functions, which comprises a physical hardware test platform, a test control software platform and a digital twinborn model of a tested component, and realizes real-time interaction through an OPC UA protocol. Model parameters are corrected on line by means of measured data, and steady state, transient state and disturbance working condition tests are automatically executed based on a working condition library; and dynamically optimizing a test sequence in a test process, skipping a redundant working condition or encrypting a critical region, and synchronously generating a structured performance report. The accuracy and consistency of test results are improved, working condition simulation signals are automatically generated, performance data are collected in real time, a comprehensive performance report is generated, manual operation is reduced, the test process optimization unit can skip redundant working conditions and refine failure boundary positioning, and the test time and cost are effectively saved.

The invention relates to the technical field of electronic measurement, in particular to a multifunctional comprehensive test method and system for a direct-current power supply, and the method comprises the steps: initializing a test; a static performance test step; a dynamic performance test step: driving a direct-current electronic load module to execute a time sequence instruction sequence in the dynamic load test file, and acquiring an output voltage and an output current waveform through a high-speed data acquisition module in the execution process; a ripple noise test step: switching the high-speed data acquisition module to an alternating current coupling mode and acquiring a high-frequency noise waveform in a constant load current section in the time sequence instruction sequence; a correlation analysis step; and a test termination step: controlling the load to return to zero and closing the tested DC power supply. Through automatic configuration and test execution of the system, the complexity of manual operation is reduced, and the test efficiency is improved. And especially in a high-frequency test scene, the test time is remarkably saved through automatic execution.

The invention discloses a Ga2O3 SBD trap test method based on forward current transient response, and belongs to the field of semiconductor device reliability. Comprising the following steps: giving a filling voltage interval and a filling time interval of a Ga2O3 SBD trap filling stage; giving a bias condition and a test time interval of a trap test stage; giving a normalization processing method and range of the forward current transient response; a characterization range of a Ga2O3 SBD device level trap time constant is given. The transient response curve of the forward current of the Ga2O3SBD under the constant test voltage is collected, and the transient current variation caused by the trap is evaluated through a normalization processing method. And repeatedly testing under the condition of multiple groups of filling voltages, establishing a time constant spectrum of the trap by using a structure function method, and extracting a time constant parameter of the trap in the Ga2O3SBD to realize in-situ and online Ga2O3SBD trap test. The method is suitable for evaluating the trap effect of Ga2O3 SBD devices from different manufacturers, and can realize spectral valuation characterization of Ga2O3 SBD traps and in-situ and nondestructive testing of trap parameters.

The invention discloses a fault detection method and system for an SVF multi-stage full-bridge sub-module in an SLCC, and the method comprises the steps: constructing a converter valve test model which comprises a converter valve, a valve control unit and a low-pressure pressurization unit; wherein the converter valve comprises a full-bridge sub-module; based on a valve tower structure, wiring complexity and test voltage safety, performing number optimization on series connection and parallel connection of full-bridge sub-modules, and setting test power supply voltage; and based on the topological structure of the full-bridge sub-modules, performing low-voltage pressurization test on the full-bridge sub-modules by using a low-voltage pressurization unit to obtain the working states of the full-bridge sub-modules, judging faults of the full-bridge sub-modules connected in series, and positioning fault positions. According to the method, the detection efficiency of the multi-stage full-bridge sub-module is improved, all the full-bridge sub-modules of the valve tower can be rapidly and accurately detected and diagnosed only through one-time wiring, the field handover test time is shortened, and SLCC direct-current power transmission project construction is supported.

The invention provides a leakage current testing method and system based on a low-frequency EIS and a transverse current pulse, and relates to the technical field of leakage current testing. The method comprises the following steps: firstly, determining use information and low-frequency EIS test parameters of a target battery to be tested, then testing the battery by using electrochemical working equipment according to the parameters, obtaining impedance data under different frequencies, and further obtaining first dynamic capacitance information. And controlling the power supply equipment to apply a preset transverse pulse current to the battery, determining a voltage variation cut-off condition, continuously monitoring the voltage variation, and recording the test time variation when the cut-off condition is reached. And finally, the leakage current value of the battery is determined by integrating the first dynamic capacitance information, the transverse current pulse current, the test time variation and the voltage variation. Compared with a traditional method, the leakage current value can be obtained only by applying the direct current once after the low-frequency EIS test without changing the magnitude and the duration time of the current for many times, the test process is simplified, the test efficiency is improved, and the leakage current value can be determined more accurately.

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

The invention relates to the technical field of electronic device testing, and discloses a high-stress acceleration type electronic device integrated aging test system. A central control unit of the system controls an environment simulation cabin module to start a test according to a test task instruction, and the environment simulation cabin module simulates a preset high-stress environment. The aging state evaluation module determines the real-time aging grade and the risk grade of the electronic device and sends the real-time aging grade and the risk grade to the central control unit, and the central control unit adjusts stress application parameters of the environment simulation cabin module according to the real-time aging grade and the risk grade. When the fault diagnosis module detects performance abnormity, real-time performance parameters and test timestamps are sent to the self-adaptive adjustment module, and the self-adaptive adjustment module judges whether stress parameters need to be adjusted or not and sends a correction instruction to the central control unit. And the aging state evaluation module analyzes the temperature distribution data, and sends a test timestamp and real-time performance parameters to the user interaction interface for real-time display when an overheating or performance attenuation signal is generated.

The invention discloses an aircraft parallel collaborative test method, device and equipment and a storage medium, and the method comprises the steps: decomposing a total test process of a single aircraft, and obtaining a plurality of test items of the single aircraft; sorting the plurality of test items on the basis of the association and dependency relationship among the test items, and sorting the test items of the plurality of aircrafts in sequence on the basis of a sorting result to obtain a double-code network diagram of the plurality of aircrafts; based on the double-code network diagram, identifying a test item link with longest time consumption when a plurality of aircrafts are tested at the same time, so as to generate a critical path; and based on the established test process optimization model, optimizing all test items on the critical path by taking test time and test resources as optimization targets, and outputting an optimal parallel test scheme of the plurality of aircrafts. The aircraft test launching efficiency and the resource utilization rate can be effectively improved, the preparation time is shortened, and it is ensured that the test process is completed on time with high quality.

The invention belongs to the technical field of testability design of integrated circuits, and discloses a 3D IC MBIST test method based on an intelligent algorithm, and the method comprises the steps: carrying out the isomorphic grouping through analyzing the space coordinates, hierarchical affiliation and multi-dimensional attributes of a memory; establishing a three-dimensional layout relationship based on the improved interlayer distance model; the hierarchical clustering algorithm is adopted to merge memory clusters according to spatial proximity, and a grouping architecture with the minimum controller number is constructed; a dynamic test scheduling model is established in combination with a multi-target simulated annealing algorithm, and test time is optimized under power consumption constraint through a temperature attenuation mechanism. According to the method, three-dimensional collaborative optimization is carried out on spatial layout, time sequence constraint and power consumption budget, the contradiction between area overhead and test efficiency of a traditional memory built-in self-test scheme in a 3D IC is solved, and lamination test challenges under the condition that the test temperature is limited are effectively handled; and the test economy and reliability of the heterogeneous integrated chip are obviously improved.

The invention discloses a software development control system and method, and belongs to the technical field of software development, the software development control system comprises a task management module, a test management module, an evaluation adjustment module and a visual module which contain a block chain technology, the task management module is responsible for creating, distributing, checking, updating and deleting software development tasks for each current developer, and the test management module is responsible for providing a software development task for each current developer; the test management module is responsible for recording and counting test, time quantity, repair and defect conditions, and the evaluation adjustment module is responsible for sequentially calculating the defect rate Q, the development efficiency KX and the research and development quality YZ of tasks allocated by each current developer in the current month. By improving data security and transparency, accurately calculating defect rate and evaluation efficiency, scientifically and reasonably allocating tasks and comprehensively and quantitatively evaluating research and development quality, transparency and credibility of a software development process are improved, an evaluation mechanism for controlling task allocation and research and development quality is optimized, and scientific and reasonable task allocation is realized.

The invention discloses a terminal communication test method and system based on an SQL database. The method comprises the following steps: determining test content; establishing a relation between the terminal and a computer with a preset SQL database through serial port communication, wherein a plurality of simulation meters of the SQL database are respectively used for simulating a plurality of electric energy meters; when multi-protocol analysis reply is carried out, received data frame protocols are distinguished and analyzed firstly and stored in a structural body, then the data frame protocols enter different processing function trees to be processed one by one, reply information frames are established, and finally information is replied through a serial port. Editing the running state of the simulation meter, and simulating the running state of at least one electric energy meter; and enabling the terminal to send a message of the collection task to each simulation table, or / and each simulation table to report timed freezing data or table data to the terminal. According to the invention, the test cost and the site demand are reduced, the test time is shortened, the test can be carried out quickly, conveniently and clearly, and the test efficiency is improved.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The embodiment of the invention discloses a multi-channel test method, electronic equipment and a test system thereof, and the method comprises the steps: receiving first identification information obtained by scanning of scanning equipment, and selecting a corresponding test channel according to the first identification information; the test channel is provided with a to-be-tested circuit board in advance; receiving second identification information obtained by scanning the to-be-tested circuit board by the scanning equipment; sending a test instruction to the test equipment on the corresponding test channel to enable the test equipment to test the to-be-tested circuit board according to a pre-configured test item to generate test data; and obtaining test data, and storing the test data according to the second identification information. By means of the mode, multi-channel parallel test preparation can be achieved, the test efficiency is improved, the overall test time is shortened, and therefore the test cost and human resource investment are reduced; and cloud storage and tracing of test data can be realized.

The utility model discloses a hydraulic drive type automatic dynamic penetration testing machine which comprises a base, a console and a lifting mechanism are arranged on the base, an automatic hammering device is arranged on the lifting mechanism, and the lifting mechanism and the automatic hammering device are both connected with the console through hydraulic pipelines. According to the utility model, the operating platform is adopted to regulate and control the working state of the lifting mechanism through pressure oil, so that the automatic hammering device can automatically lift and drop a hammer, the purpose of automatic hammering is achieved, the tedious process of manual operation is avoided, each hammering penetration depth can be recorded through the operating platform, the test time is effectively saved, the test efficiency is improved, and the test cost is reduced. And moreover, recording errors caused by manual counting of testers are prevented, the authenticity and accuracy of the test are ensured, the test efficiency is improved, and the device has the characteristics of convenience in installation, convenience in operation and the like.

Various examples are directed to systems and methods for utilizing relationship data. A computing system may receive a time-dependent query against a knowledge graph data structure. The computing system may access confirmation data from the knowledge graph data structure, the confirmation data describing a first plurality of confirmation points-in-time at which the first test relationship is true. The computing system may determine that at least one of a beginning or an end of a first time period associated with a test relationship of the time-dependent query is not defined by the knowledge graph data structure. The computing system may determine a response to the first time-dependent query indicating a veracity of the test relationship at a test point-in-time using the first plurality of confirmation points-and-time.

The invention relates to a parallel test task scheduling method for a multi-target equipment distributed test system, and belongs to the technical field of scheduling methods. The invention provides a parallel test task scheduling method for a multi-target equipment distributed test system and aims to solve the problems that current equipment models are continuously increased, the number and complexity of equipment test tasks are obviously increased, a traditional test method is long in test time and low in resource utilization rate, and equipment test requirements at the current stage cannot be met. The method can obviously shorten the test time and improve the resource utilization rate, and comprises the following steps: step 1, describing an equipment parallel test task scheduling model by adopting a mathematical method; step 2, determining a constraint relationship of the test task on test time sequence and resources and a constraint condition satisfied between the test task and the test resources; 3, determining a fitness function corresponding to the test time and the resource utilization balance degree, and designing an overall fitness function; and step 4, solving the fitness function.

The invention provides a composite material connection structure marine environment acceleration test evaluation method and system based on environmental parameter equal ratio conversion. The method comprises the steps of determining marine atmospheric environment factors influencing performance degradation of the composite material connection structure, determining acceleration test modules, constructing a marine atmospheric environment spectrum, performing equivalent conversion on acceleration test parameters of the acceleration test modules, and performing environmental damage grade evaluation on the composite material connection structure. The system executes the above steps by means of a computer program. According to the method, a specific acceleration test parameter equivalent conversion technical scheme in which the test time is proportionally distributed is creatively adopted for the first time, and the damage process of the marine atmospheric environment of the composite material connection structure can be more accurately reproduced and evaluated in cooperation with a specific environment damage grade evaluation mode of the composite material connection structure.

The invention discloses a minimum working voltage value testing method and device, a medium and equipment. The method comprises the following steps: acquiring an initial working voltage value and a preset step value of a circuit to be supplied with power; and based on the initial working voltage value and a preset step value, performing iterative calculation by using a dichotomy, and determining the minimum working voltage value of the circuit to be supplied with power. By adopting the scheme, the test time of the minimum voltage value of the normal work of the circuit can be shortened, so that the test efficiency is improved.

The invention discloses a fatigue damage simulation test device for wheel-rail rolling contact. The fatigue damage simulation test device comprises a rack assembly, a clamp system, a splicing guide rail, an experiment loading system, a transmission system and a guide system, two parallel vertical lead screws are arranged in the rack assembly, and the lead screws are controlled by a transmission system to rotate and drive a cross beam installed on the lead screws to ascend and descend. A splicing guide rail for testing is mounted on the lower end face of the cross beam through a clamp system; the guide system is mounted on the clamping plate, and the splicing guide rail is controlled by the guide system to limit and guide; the experiment loading system is arranged on the outer side of the splicing guide rail above the guiding system and installed on the clamping plate, and the splicing guide rail is controlled by the experiment loading system to conduct loading. The device is compact in structure, the length range of the guide rail capable of being simulated is large, the adaptive guide rail types are multiple, clamping is convenient, loading is uniform, guiding is convenient, stability is good, control precision is high, meanwhile, the test time is greatly shortened, and the test cost is reduced.