213 results about "Wafer testing" patented technology

The utility model discloses a silicon optical wafer test device and an alignment coupling mechanism and a test system thereof. The alignment coupling mechanism comprises an optical fiber coupling module, a piezoelectric displacement table and a tail end connecting structure which are connected in sequence. The optical fiber coupling module comprises three translation assemblies and three rotating assemblies which are sequentially connected in series; the three translation assemblies are used for driving the tail end connecting structure to do translation motion in the first direction, the second direction and the third direction correspondingly. The three rotating assemblies are used for driving the tail end connecting structure to rotate with the first rotating shaft, the second rotating shaft and the third rotating shaft as the center correspondingly. The first direction, the second direction and the third direction are vertical in pairs; the first rotating shaft, the second rotating shaft and the third rotating shaft are perpendicular pairwise. Each assembly only needs to achieve motion adjustment on one degree of freedom, the function is single, precise control over motion adjustment is facilitated, all the assemblies only need to be sequentially connected in series, spliced and connected, implementation is simple and easy, and equipment cost can be reduced.

The utility model discloses silicon optical wafer test equipment. The silicon optical wafer test equipment comprises a camera assembly, a deflection optical path assembly, a probe station and an optical fiber coupling module, the driving assembly is used for driving the probe station and the deflection optical path assembly to move to the lower part of the camera assembly and the optical fiber end part of the optical fiber array in a mutual switching manner; the optical fiber coupling module is used for clamping the optical fiber end part of the optical fiber array; when the probe station moves to the position below the camera assembly, a cross cursor of a camera of the camera assembly is adjusted to be parallel to a cutting channel of the silicon optical wafer; when the deflection light path assembly moves into the imaging view field of the camera assembly, the camera assembly is used for collecting a first lateral image and a second lateral image through the deflection light path assembly and collecting a vertical image; and adjusting the end part of the optical fiber by using an optical fiber coupling module according to the image, so that the end part of the optical fiber and the optical waveguide are aligned and coupled. According to the application, the operation difficulty and the equipment structure for realizing alignment coupling between the optical fiber end part and the silicon optical waveguide are simplified, and the equipment cost is reduced.

The invention relates to the technical field of wafer testing, in particular to a wafer testing result visualization method and system. Through spatial discretization processing, continuous physical coordinates of test points are mapped to a fixed N * N regular grid, and mass and disordered coordinate points are classified into limited and ordered grid units through the conversion, so that the complexity of data positioning is reduced from O (n) to O (1). When rendering is carried out, a system can directly access grid data at any position through simple coordinate transformation without traversing all test points based on a data structure established on the basis of the regular grid. More importantly, the rendering mode is dynamically selected and drawn, so that the rendering calculation amount of the system does not depend on the total amount of test points any more, but depends on the number of grids in the current viewport. And the processing object is fundamentally optimized from a'test point 'to a'viewport inner grid', so that the data processing and rendering efficiency is greatly improved.

The invention provides a wafer test probe pressure control method and system, electronic equipment and a storage medium. The method comprises the following steps: acquiring probe card information and to-be-tested product information configured for a current test task; based on the probe card information and the to-be-tested product information, extracting a corresponding multi-dimensional parameter set from a pre-established probe card comprehensive parameter database; inputting the multi-dimensional parameter set into a preset probe pressure optimization model, and calculating a probe pressure control interval suitable for the current test task; sending the probe pressure control interval to a production execution system in communication connection with the probe station; executing the current test task under the control of the production execution system, and collecting an actual probe pressure value applied by the probe station in real time through the production execution system; in response to the fact that the actual needle pressure value exceeds the needle pressure control interval, the production execution system is triggered to execute needle pressure abnormal control operation, and the problem that the needle mark is large due to the fact that non-optimal fixed needle pressure is used is solved.

The invention relates to a lithium battery charging chip test method and circuit, and the method comprises the steps: distributing corresponding test resources according to the attribute information of each pin in a charging chip, building a connection, carrying out a pin connectivity test, collecting each performance parameter of the charging chip, comparing the performance parameters with a preset target specification value, and obtaining a test result. Generating a corresponding parameter deviation vector; inputting the parameter deviation vector into a trimming model, calculating a corresponding trimming parameter vector, and encoding the trimming parameter vector into corresponding EFUSE target configuration data; according to the method, target EFUSE configuration data is written into a charging chip in a segmented mode, all the written content of the EFUSE in the charging chip is read, integrity comparison is conducted on all the written content and a pre-stored standard signature, the certainty and traceability of the EFUSE burning process in the wafer testing stage are improved, and the reliability of the EFUSE burning process in the wafer testing stage is improved. The chip waste rate caused by mismatching of test resources or unstable write-in control is reduced, parallel testing of multiple chips can be supported, and the mass production test efficiency and the overall production line yield are improved.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The invention provides a temperature control assembly for a probe card and the probe card, and relates to the field of wafer testing. The temperature control assembly for the probe card comprises a cover plate; the heating assembly is arranged on the side, away from the probe card, of the cover plate, and the heating assembly is electrically connected with the testing machine table; the heating buffer assembly is arranged on one side, close to the probe card, of the cover plate; the heat preservation assembly is arranged on the side, close to the probe card, of the cover plate, and the heat preservation assembly is an assembly with a closed pattern and is distributed on the outer side of the probe card; wherein the cover plate, the heat preservation assembly and the probe card form a heat receiving space, and the orthographic projection of the heating assembly on the cover plate is within the orthographic projection of the heating buffer assembly and the heat preservation assembly on the cover plate. According to the embodiment of the invention, the probe mark offset caused by temperature difference generated by heating of the probe card in the test process can be avoided, so that the test efficiency can be improved.

The utility model relates to an anti-ink-splashing wafer dotting device, which belongs to the technical field of semiconductor wafer testing and comprises a basic support, an adjustable support, a fixed support, a coil, a funnel, a connecting rod, a spring, an ink guide wire, a limit screw I and a limit screw II. The spring is axially and fixedly connected below the connecting rod, the coil is axially and fixedly connected below the spring, the funnel is axially arranged below the coil, and the ink guide wire is arranged below the funnel. An ink fixing pipe is arranged in the funnel, the position for fixing the ink fixing pipe is higher than the upper edge of the funnel, the slender ink fixing pipe can ensure that the ink guide wire does not generate large deformation bending and ink splashing when moving up and down in the coil and the connecting rod, and the inner wall of the part, extending into the funnel, of the ink fixing pipe is provided with a round hole, so that the ink in the funnel is not blocked. The ink fixing pipe prevents ink on the ink guide wire from splashing to the surface of the wafer, and the ink on the ink guide wire falls into the ink fixing pipe when splashing, so that the ink cannot be splashed to the surface of the wafer to contaminate the surface of the wafer, and the product quality and the production efficiency are improved.

The application provides a memory operation method and a memory chip. The method comprises the following steps: obtaining an operation depth; wherein the operation depth is determined in wafer testing and stored in a storage unit; the operation depth represents a threshold voltage change level of the storage unit after operation; when the operation is performed, the operation depth is used for depth checking until the operation depth is reached. The application can accurately test the operation depth of the memory chip, and then guide the actual operation by using the operation depth, so as to achieve the purpose of accurately controlling the operation effect, and the problem that the threshold voltage of the storage unit becomes complex and uncontrollable can be avoided.

The invention relates to the technical field of power semiconductor wafer testing, and discloses a power semiconductor wafer electrical parameter testing system and method, and the system comprises a dynamic testing device which is electrically connected with a wafer bearing device, a static testing device which is electrically connected with the wafer bearing device, and a wafer bearing device which is electrically connected with a switching device. The wafer bearing device is electrically connected with the static testing device, the dynamic testing device is electrically connected with the wafer bearing device, the switching device is electrically connected with the static testing device and the dynamic testing device, and the control device is electrically connected with the switching device and used for controlling the switching device to conduct the wafer bearing device and the dynamic testing device or conduct the wafer bearing device and the static testing device. Two types of tests can be completed by only using one test needle seat, and the two types of tests can be completed through one-time needle pressing, so that the damage to the wafer is reduced.

The invention discloses a wafer testing machine and a storage container for the wafer testing machine. The wafer testing machine comprises a chuck, a probe card, a storage container and a carrying device. And the probe card is arranged above the chuck relative to the chuck. The storage container comprises a plurality of drawers which are used for bearing test samples or auxiliary devices. And the carrying device is used for carrying the test sample or the auxiliary device among the chuck, the storage container and the wafer bearing box. According to the wafer testing machine, the overall testing time can be shortened.

The application discloses a chip performance parameter automatic extraction method and system based on chip geometric coordinate mapping, a storage medium and electronic equipment, and belongs to the technical field of semiconductor testing. The application establishes a unified physical coordinate system, and performs coincidence comparison between layout definition data containing a chip identifier ChipID, design starting coordinates and physical dimensions of the ChipID, and pixel-level test original data containing physical performance indexes. For each ChipID, the geometric center point coordinates are calculated according to the starting coordinates and the physical dimensions, the center point coordinates are mapped back to the grid index of the test data, the chip performance parameters at the corresponding positions are automatically extracted, and finally the extracted performance parameters are associated with the ChipID to generate a chip-level performance parameter report. The application solves the problems that test data and chip positions are difficult to accurately associate and manual extraction is low in efficiency in the prior art, realizes automatic conversion of test data from 'pixel level' to 'chip level', has the advantages of high precision, high automation degree, strong scalability and the like, and can be widely applied to the field of semiconductor wafer testing.

The present application relates to the technical field of wafer testing. Provided are a wafer test data processing method and apparatus, and an electronic device and a medium. The method comprises: acquiring a test sequence consisting of test data of a plurality of dies on a target wafer; dividing the plurality of pieces of test data in the test sequence, so as to obtain a plurality of sub-sequences; converting the test data in the sub-sequences, so as to obtain target sub-sequences; and for the target sub-sequences that meet a deletion condition, deleting same in corresponding processing threads. In the present application, the problem of memory overflow in a conventional CS architecture when processing large-scale wafer test data is effectively solved by means of a BS architecture and a memory optimization technique; the processing efficiency and response speed of a system are improved by means of techniques such as data chunking, stream processing and asynchronous generation; and the stability and reliability of a system are enhanced by means of optimizing memory usage and data processing flows.

A wafer test cassette having a fluid inlet and a fluid outlet, includes a first housing, a second housing, a heat source, and an isolation device. The first housing includes a probe card including probes. The second housing is coupled to the first housing, so that a test space is defined. The second housing carries a wafer arranged in the test space, and the probes are electrical contact with an upper surface of the wafer. The heat source heats a lower surface of the wafer, and a high temperature region is defined between the lower surface and the second housing. The solation device surrounds the high temperature region for thermally isolating the high temperature region from the test space. The fluid inlet receives a gas, the gas flows between the probe card and the upper surface of the wafer, and exits through the fluid outlet.

The embodiment of the invention provides a wafer test board and a wafer test method, and belongs to the technical field of wafer test. The wafer test board comprises an SOC chip, a sampling circuit and a probe connector which are all integrated on a PCB substrate. A first connecting pin of the universal SOC chip is connected with a first connecting end of the probe connector, and two ends of the sampling circuit are respectively connected with a sampling pin of the universal SOC chip and a second connecting end of the probe connector; the distance between the universal SOC chip and the probe connector is greater than 5cm; the clock frequency of the universal SOC chip is configured to be a clock configuration frequency lower than 100 MHz; and the universal SOC chip is used for determining qualified bare chips from the wafers to be tested according to read-write test results obtained by performing read-write tests on the bare chips and electrical sampling data obtained by performing electrical sampling on the bare chips through the sampling circuit. According to the embodiment of the invention, the test cost can be reduced on the premise of considering the wafer test reliability.

The application discloses a reference cell module of a non-volatile memory and a reference cell repair method. The reference cell repair method comprises: performing first reference cell repair in a wafer test stage; and performing second reference cell repair in a package test stage. The reference cell module of the non-volatile memory comprises a first subarray and a second subarray, and the reference cell repair comprises forming an address mapping between a first reference cell of the first subarray with defects and a second reference cell of the second subarray without defects and with the same threshold voltage. In the wafer test stage and the package test stage, the first reference cell with defects is repaired, so that the chip yield is improved.

Provided in the present disclosure are a silicon photonics wafer test apparatus and a test method therefor, and a silicon photonics wafer test system. The silicon photonics wafer test apparatus comprises a camera assembly and a deflection optical path assembly; a prober for carrying a silicon photonics wafer; a fiber coupling module; and a driving assembly. When the driving assembly moves the silicon photonics wafer into the imaging field of view of the camera assembly, the camera assembly is adjusted such that the coordinate system is parallel to scribe lines of the silicon photonics wafer; when the driving assembly moves the deflection optical path assembly into the imaging field of view of the camera assembly, the camera assembly captures lateral images of a fiber end from at least two different directions via the deflection optical path assembly. The fiber coupling module is used for adjusting the pose of the fiber end on the basis of the lateral images and the direction of the coordinate system of the camera assembly, enabling initial alignment between the fiber end and the silicon photonics wafer. The present disclosure reduces the operational difficulty of alignment coupling between the fiber end and a silicon photonics waveguide, thereby simplifying the apparatus structure and reducing apparatus costs.

The invention provides a wafer test lens module and a wafer test device.The lens module comprises a lens module base, a lifting structure capable of generating axial displacement relative to the lens module base and a lens body detachably connected with the lifting structure, and one end of the lifting structure is provided with a plurality of connecting units arranged at intervals in the circumferential direction; at least part of the connecting units are provided with first clamping parts, and the peripheral wall of the lens body is provided with second clamping parts used for being mutually clamped with the first clamping parts. According to the wafer test lens module and the wafer test device provided by the invention, one end of the lifting structure can be deformed, the size of the lifting structure can be changed, the second clamping part on the lens body can be clamped with the first clamping part, the lens body can also be easily detached from the lifting structure, the lens body can be conveniently replaced, the replacement process is simple, and the replacement efficiency is improved. The lens body cannot be scratched, the time for replacing the lens body is short, and the debugging time is short.

Provided are a wafer testing method and device thereof, and a chip testing method and device thereof, relating to the field of semiconductor manufacturing. The wafer testing method comprises: obtaining a bare chip in a wafer; connecting a wafer detection device to the bare chip, the wafer detection device sending a test signal to the bare chip and receiving an output signal of the bare chip, the test signal being a detection signal corresponding to detection of logic function, electrical performance or physical defects of the bare chip, and the output signal being an output signal corresponding to detection of logic function, electrical performance or physical defects of the bare chip. In this way, the accuracy and efficiency of wafer detection can be improved, timely and effective process optimization in the wafer processing process can be achieved, and in addition, the method can be compatible with conventional wafer detection devices, reducing the cost of modification of the wafer detection device.

The application relates to the technical field of wafer testing, in particular to a wafer feeding equipment and a wafer aging test system; the wafer feeding equipment comprises: a loading platform comprising a placing plane for placing wafers of different sizes; a wafer edge finding mechanism comprising a wafer image acquisition device, a first driving device and a first transmission device; the wafer image acquisition device is arranged above the placing plane; the first driving device is in driving connection with the first transmission device; the transmission end of the first transmission device is fixedly connected with the wafer image acquisition device, so that the wafer image acquisition device moves to acquire a wafer image under the driving of the first driving device; through the edge finding processing suitable for wafers of different sizes, the universality of the wafer feeding equipment is improved, and the aging test cost is reduced.

The utility model provides a wafer test bench assembly and a wafer test device. Wherein the test board assembly comprises a test carrying table and a covering part, the upper surface of the test carrying table is used for bearing a wafer to be tested, and the test carrying table is made of a conductive material; the cover member is annular, can be transferred and placed on the test stage or the wafer to cover the annular edge of the wafer, and can be insulated from the test stage. According to the wafer test bench assembly and the wafer test device provided by the invention, during detection, when a part of the probes move to the edge area of the wafer, the probes are only in contact with the surface of the covering part, so that a passage can be prevented from being accidentally formed between the probes and the test platform deck, and the effectiveness and the accuracy of a crystal grain area on the wafer during detection can be guaranteed.

The application discloses a wafer test offset detection method and system based on a MAP graph and a storage medium, and comprises the following steps: obtaining a MAP graph of a wafer to be detected, calculating the overall yield of the annular region between the outermost circle and each inner circle of the MAP graph; arranging all annular regions in ascending order according to the radius difference between the outermost circle and the inner circle corresponding to each annular region to obtain a target queue, and determining the first annular region in the target queue as a target annular region when the overall yield of the first annular region is greater than or equal to a preset overall yield; dividing the target annular region into a plurality of identical arc-shaped regions, and obtaining the overall yield of each arc-shaped region; and determining that the wafer to be detected has an offset when the difference between the highest overall yield and the lowest overall yield in all arc-shaped regions is greater than a preset difference. The application can timely find the map shift generated in the wafer test process, improve the judgment accuracy, and avoid causing significant economic losses.

The application discloses a wafer testing device and a control method thereof. The wafer testing device comprises a bearing table, a lifting mechanism, a camera device and a laser device. The bearing table is provided with a testing position for placing a wafer. The lifting mechanism is installed on the bearing table in a lifting manner. The camera device is installed on the lifting mechanism, and a camera end of the camera device faces the testing position. The camera device is used to acquire image information of the wafer placed on the testing position. The laser device is installed on the lifting mechanism, and a light-emitting end of the laser device faces the testing position. The laser device is used to emit testing laser to the wafer placed on the testing position. The laser focus emitted by the laser device is higher than a visual focusing surface of the camera device. The wafer testing device solves the problem that the laser device is prone to colliding with a carrier or a clamp on the bearing table due to careless operation.

This invention relates to the field of semiconductor manufacturing technology, specifically to an intelligent conversion system for a unified format of wafer test mapping files. The system includes a file acquisition and reception module, an intelligent recognition and unified conversion engine, a standard mapping file generation and output module, and an access control and management module. The intelligent recognition and unified conversion engine automatically parses multi-format mapping files using a deep learning model and quickly adapts to new formats through a meta-learning mechanism; the access control and management module ensures operational security and data integrity; the system can also achieve cross-node collaborative evolution through federated learning. This invention achieves fully automatic, high-precision, and high-security conversion of wafer test mapping files to internal standard formats, overcoming the shortcomings of traditional manual processing, such as low efficiency, error-proneness, and inability to quickly adapt to new formats, significantly improving the intelligence, flexibility, and reliability of semiconductor packaging production.

This application provides a wafer testing apparatus and a wafer testing method. The wafer testing apparatus may include: a first optical path loop for connecting test points in the non-functional areas of the chip cells of the wafer under test, used to measure a first optical signal; a second optical path loop for connecting coupling test points between the non-functional areas and functional areas of the chip cells of the wafer under test, used to measure a second optical signal; wherein the first and second optical signals are used to determine the chip end-face optical loss of the chip cells of the wafer under test; and a third optical path loop for connecting test points in the functional areas of the chip cells of the wafer under test, used to measure a third optical signal, wherein the second and third optical signals are used to determine the on-chip optical loss of the chip cells of the wafer under test; wherein all chip cells of the wafer under test are configured with a set of the first, second, and third optical path loops. Based on the above apparatus, wafer testing can be achieved using simpler circuits.

The application relates to the technical field of wafer testing, and discloses a wafer carrier mechanism, a wafer testing device and a control method thereof. The wafer carrier mechanism is used for placing a wafer and comprises a base, a sliding seat, a first screw rod, a first driving piece, a connecting piece, a second screw rod, a second driving piece, a guide rod and a wafer carrier table. The first driving piece is used for driving the first screw rod to rotate, so that the connecting piece and the second screw rod are lifted relative to the first screw rod, thereby lifting the sliding seat and the wafer carrier table. The second driving piece is used for driving the second screw rod to rotate, so that the second screw rod is lifted relative to the connecting piece, thereby lifting the sliding seat and the wafer carrier table. The wafer carrier mechanism can realize micro-motion of the wafer carrier table through two screw rods, and the micro-motion of one screw rod will not cause abrasion of the other screw rod. When the first screw rod or the second screw rod is abraded, the other screw rod can be used to continue driving the wafer carrier table to micro-move, thereby effectively prolonging the overall service life of the screw rod transmission mechanism.

Embodiments of the present invention relate to a wafer test system and a method of operating the wafer system. According to embodiments of the present invention, an electrical test is performed on a wafer comprising a plurality of dies, an active state occurring in the wafer is detected when the electrical test is performed, and a failure status can be determined for the plurality of dies included in the wafer based on the electrical test results for the wafer and active state information received from a detection device.

The invention relates to the technical field of sensing product testing, in particular to a super-large array packaging conductivity testing device which comprises a wafer testing table, an open circuit testing plate and a short circuit testing plate, an objective table is installed at the top of the wafer testing table, and a swing arm positioning seat is installed at the top of the wafer testing table and on the back face of the objective table. The outer wall of the swing arm positioning seat is provided with a test probe, the top of the wafer test bench and the back surface of the swing arm positioning seat are provided with a main control unit, and the outer wall of the main control unit is connected with the swing arm positioning seat through a test line. According to the super-large array packaging conductivity testing device, the open circuit testing plate and the short circuit testing plate in the device are used for testing the to-be-tested product, and the problems that an existing testing device and an existing testing method cannot directly point-contact the two ends for measurement, the accuracy of a testing result is poor, the efficiency is low, and the product is prone to being damaged are solved.

The application discloses a kind of wafer test system calibration methods, the calibration method includes electrical parameter calibration and displacement parameter calibration, wherein, electrical parameter calibration method is: to the test machine in wafer test system sends standard source control signal, and gathers the first electric signal that test machine issues and is transferred to probe card, and the second electric signal that probe card detects and is returned to test machine;First and second electric signal corresponding with pre-set electric signal are compared, to realize the integrity calibration of wafer test system test machine electrical parameter;Displacement parameter calibration method is: to probe station sends displacement signal, simultaneously obtains the displacement information of probe station measured using laser interferometer, the displacement information is compared with pre-set displacement value, to realize the calibration of wafer test system displacement.The application can realize the calibration of electrical parameter and non-electrical parameter of wafer test system simultaneously, effectively improve the test accuracy and reliability of wafer test system.

The application relates to the technical field of wafer testing equipment, in particular to a heating aging test tool, which comprises a storage rack, a wafer clamp placed on the storage rack, a detection assembly comprising a plurality of elastic probes and a heating disc located on one side of the storage rack, and a hot air flow guide assembly comprising an air outlet male head arranged on one side of the heating disc, a heat conduction cover provided with an air guide pipe away from one side of the air outlet male head, and a cavity with gradually increased air volume and gradually reduced air flow rate from the inside to the outside of the air guide pipe. The hot air flow guide assembly is arranged on the conveying frame, the heat of the heating disc is guided to the upper side of the wafer through the air flow of the heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow rate and the hot air volume of each space are adjusted, the influence of heat loss in the air flow process is reduced, the heating effect of each part of the wafer is similar, and the detection effect is improved.