774 results about "Wafer testing" patented technology

The invention provides a wafer-level test yield prediction and process optimization method and system based on big data, and relates to the technical field of wafer-level tests.The wafer-level test yield prediction and process optimization method comprises the steps that wafer manufacturing process data is obtained, a time-sequence-sensitive multi-modal data fusion network is constructed, a LSTM and GNN combined mixed architecture is adopted, and a multi-modal data fusion network is constructed; self-adaptive weight distribution is carried out through an attention mechanism to predict the yield; and when the predicted yield is lower than a threshold value, triggering a layered progressive process optimization system, and adjusting process parameters through an equipment parameter optimization layer and a process level optimization layer. According to the invention, the accurate prediction of the wafer test yield and the automatic optimization of the process parameters are realized, the production efficiency is improved, and the manufacturing cost is reduced.

The invention provides a wafer testing device capable of being rapidly maintained, and relates to the technical field of semiconductors, the wafer testing device comprises a fixed plate, the fixed plate is provided with a control module, and a power supply module, a probe card, a heating lifting module and at least one testing module which are connected with the control module, and a wafer to be tested is integrally arranged in the probe card. The power supply module is connected with the probe card to supply power to the to-be-tested wafer, a heater and a probe are arranged in the heating lifting module, and the heating lifting module is used for driving the to-be-tested wafer in the probe card to be in contact with the probe and heating the to-be-tested wafer. The test module comprises a bottom plate which is in push-pull connection with the fixed plate along the first direction and a switch array measurement assembly which is arranged on the bottom plate and is in plug-in connection with the bottom plate along the second direction, and the switch array measurement assembly is used for testing different parameters of the to-be-tested wafer when the to-be-tested wafer is in contact with the probe. The switch array measurement assembly is in plug-in connection with the bottom plate, and the bottom plate is in push-pull connection with the fixed plate, thereby facilitating the replacement of the test module, and achieving the quick disassembly and assembly.

A wafer-level burn-in test fixture, a wafer-level burn-in test device, a test method, and a wafer-level burn-in test system, which relate to the technical field of wafer testing. The wafer-level burn-in test device comprises a wafer-level burn-in test fixture and a lifting mechanism, wherein the wafer-level burn-in test fixture comprises a cover plate assembly, a lower sealing assembly, a heat sink and a heating device, wherein the heat sink is configured to bear a wafer; the cover plate assembly comprises a first PCB and a test micropositioner connected to the first PCB; the lower sealing assembly comprises a lower sealing cover, which is connected to the cover plate assembly to form a test cavity; the heat sink and the heating device are located in the test cavity; and the heating device is located between the lower sealing cover and the heat sink. The lifting mechanism is configured to be controlled to extend and retract vertically, and movably abuts against the wafer-level burn-in test fixture so as to drive the lower sealing assembly to move upwards to be connected to the cover plate assembly to form the test cavity.

The invention provides a multi-probe array real-time pressure optimization and control method for wafer testing, and relates to the technical field of semiconductor testing, and the method comprises the steps: collecting real-time pressure data and a wafer stress limit value, building an initial distribution state, calculating the contact area and angle through displacement, determining a stress concentration factor, and carrying out the pressure correction, calculating strain rate distribution to identify a sensitive area to perform pressure compensation, monitoring a stress-strain ratio to identify a microcrack initiation point to determine an optimal pressurization parameter, and performing real-time monitoring and early warning. According to the invention, the damage risk in the wafer testing process can be reduced, and the testing precision and the yield can be improved.

The utility model belongs to the technical field of semiconductors, and discloses a wafer bearing device and wafer testing equipment. The wafer bearing device comprises a bearing disc, a cooling member and a heating member. One side of the bearing disc is used for bearing wafers, and the bearing disc is provided with a plurality of adsorption holes used for adsorbing and fixing the wafers; the cooling piece is fixedly arranged on the other side of the bearing disc, and a cooling flow channel allowing cooling liquid to circularly flow is defined between the cooling piece and the bearing disc; the heating member is arranged on one side, far away from the bearing disc, of the cooling member and is used for heating the wafer. When the bearing device is used, heat generated by the heating piece can be transmitted into the bearing disc only through the one-layer structure of the cooling piece during transmission, so that the temperature control precision of the bearing disc is effectively improved, and when automatic control is carried out according to an actual control program, the temperature difference amplitude of the bearing disc can be kept at + / -0.5 DEG C or even lower; therefore, the bearing disc can keep good temperature uniformity in the wafer testing process.

The invention provides a WAT test method and system, and the method comprises the steps: carrying out the initial wafer test based on a WAT test file to obtain an initial test result of a tested parameter, judging whether the initial test result of the tested parameter is in a control line range or not based on a control line file, if yes, judging the tested parameter as a pass parameter, and if not, judging the tested parameter as a pass parameter; if not, the tested parameter is judged to be a failure parameter, the failure parameter is recorded in a failure parameter recording module, then a failure action is triggered for the failure parameter recorded in the failure parameter recording module, and the failure action comprises in-situ retest or ectopic retest. According to the WAT test method and system, when the data is judged to be abnormal, failure parameters can be automatically recorded, measures are taken for the failure parameters, and the links of waiting for an engineer to check data, selecting the failure parameters by the engineer, establishing a test program by the WAT engineer and waiting for a test wafer are omitted; therefore, the test and data analysis efficiency can be effectively improved.

The embodiment of the invention provides a wafer testing device and testing method, and belongs to the technical field of wafer testing. The wafer testing device comprises an MEMS probe chip installed and connected on a testing machine, and a testing position used for fixing a tested chip. A test contact of a probe of the MEMS probe chip is in contact with a PAD of a tested chip during testing, and the MEMS probe chip is used for collecting a detection signal of the tested chip; wherein a probe of the MEMS probe chip is integrated in the MEMS probe chip based on a cantilever beam type; and the test machine is used for generating a test result corresponding to the tested chip based on the detection signal of the tested chip. The MEMS probe chip in the scheme of the invention adopts a modular design, is convenient to quickly replace, reduces the maintenance cost and time, and provides a better solution for the test requirements of high-frequency and high-density packaged chips.

The embodiment of the invention discloses a wafer test result generation method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductor chips, and the method comprises the steps: obtaining a plurality of test files generated by carrying out multiple tests on the same wafer; integrating the plurality of test files, and only reserving an optimal test result for a plurality of test results of the same semiconductor chip on the wafer; and obtaining a final test result of the wafer based on the integrated test file. The technical scheme provided by the embodiment of the invention can be suitable for a wafer test scene, and can solve the problems of low wafer test data processing efficiency and inaccurate test result extraction in the prior art.

The invention discloses silicon optical wafer testing equipment and an optical fiber pose adjusting mechanism, method and system thereof. The optical fiber pose adjusting mechanism comprises a camera assembly and a deflection optical path assembly. The probe station is used for bearing a silicon optical wafer; an optical fiber coupling module; when the driving assembly drives the silicon optical wafer to be located in the imaging view field of the camera assembly, the camera assembly is adjusted to enable the coordinate system to be parallel to the cutting channel of the silicon optical wafer; when the driving assembly drives the deflection optical path assembly to move into an imaging view field of the camera assembly, the camera assembly collects lateral images of the end part of the optical fiber in at least two different directions through the deflection optical path assembly; and the optical fiber coupling module is used for performing pose adjustment on the end part of the optical fiber according to the lateral image and the direction of the coordinate system of the camera assembly, so that the end part of the optical fiber is preliminarily aligned with the silicon optical wafer. The operation difficulty and the equipment structure of alignment coupling between the optical fiber end part and the silicon optical waveguide are simplified, and the equipment cost is reduced.

The invention provides a wafer test data processing method and device, equipment and a medium, and can be applied to the technical field of chips. The method comprises the following steps: acquiring a standard test data file generated when a wafer is tested; analyzing the standard test data file to obtain data files respectively corresponding to the plurality of data types; wherein the data file comprises test record data belonging to a corresponding data type; based on the data files corresponding to the multiple data types respectively, respectively generating analyzable data corresponding to each preset category in the multiple preset categories; and outputting the analyzable data corresponding to each preset category. According to the invention, automatic analysis and classification of the wafer test data are realized, and the efficiency is high.

The invention relates to the technical field of wafer test equipment, in particular to a heating aging test tool which comprises a storage rack and further comprises a wafer clamp placed on the storage rack. The detection assembly comprises a plurality of elastic probes located on one side of the storage rack and a heating disc; and the hot air guide assembly comprises a ventilation male head arranged on one side of the heating disc, an air guide pipe is arranged on the side, away from the ventilation male head, of the heat conduction cover, the air amount in the cavity is gradually decreased from near to far away from the air guide pipe, and the air flow speed is gradually decreased. A hot air flow guide assembly is arranged on a conveying frame, heat of a heating disc is guided to the position above a wafer through airflow through a heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow speed and the contained hot air amount of each space are adjusted, and therefore the heat conduction efficiency of the wafer is improved. The influence of heat loss in the air flow process is reduced, so that the heating effects of all parts of the wafer are similar, and the detection effect is improved.

The embodiment of the invention provides a transmitting circuit, a receiving circuit, an integrated circuit chip and a test method. The transmitting circuit comprises a test data generation module, a to-be-tested transmitting module, a test receiving module and a test data detection module, wherein the test data generation module is configured to generate first test data; the to-be-tested sending module is configured to generate second test data based on the first test data; the test receiving module is configured to generate third test data based on the second test data; the test data detection module is configured to receive third test data and detect whether the third test data is consistent with the first test data, and the to-be-tested sending module is further configured to receive a first clock signal with an adjustable phase. The test receiving module and / or the test data detection module are / is further configured to receive a phase-adjustable second clock signal. According to the sending circuit, the circuit performance can be prevented from being affected, and performance testing, screening and grading of a physical layer circuit are achieved in the wafer testing stage.

The invention relates to a wafer probe test calibration method, device and equipment, a medium and a product, and relates to the field of semiconductor equipment, and the method comprises the steps: obtaining an initial OD value of a wafer test machine in a zero-pressure contact state between a probe on a probe card and a contact point on a wafer, and a length value of the probe; acquiring a first height difference between a first reference measurement point above the wafer and a second reference measurement point below the wafer; acquiring a second height difference between the first reference measurement point and the top surface of the wafer; acquiring a third height difference between the bottom surface of the probe card and the second reference measurement point; calculating a measurement distance value between the bottom surface of the probe and the contact point according to the first height difference, the second height difference, the third height difference and the length value; according to the method, the influence of the WAT machine difference and the product film thickness on OD value setting can be eliminated, and meanwhile, the product film layer change and the equipment state are monitored according to the target displacement value obtained through calibration.

The invention provides a wafer testing system and method, and belongs to the field of semiconductor testing. The wafer test system comprises a control host, a probe card and a test device, the probe card comprises a signal switch; the control host is used for generating a target mode test instruction and sending the target mode test instruction to the probe card; and the probe card is used for enabling the signal switch to select a corresponding target mode based on the target mode test instruction so as to acquire a test signal corresponding to the to-be-tested wafer device, and sending the test signal to the test device so as to obtain test data of the to-be-tested wafer device. Devices required for dynamic detection and static detection of wafer devices are integrated on the probe card, and mode selection is carried out through a signal switch. When a dynamic test and a static test need to be switched, the probe does not need to be switched, and only the signal switch needs to be switched on and off, so that the wafer test efficiency is improved.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention relates to the technical field of precision machinery manufacturing technology, and discloses a high-efficiency wafer test probe station, which comprises a base, the upper surface of the base is fixedly connected with a loading base and a motion control system, the output end of the motion control system is fixedly connected with a microscope, the upper surface of the loading base is fixedly connected with an objective table, and the objective table is fixedly connected with the output end of the motion control system. The interior of the base is in threaded connection with a synchronous adjusting mechanism and a support protection mechanism, the top of the synchronous adjusting mechanism is fixedly connected with a probe angle adjusting mechanism, and the upper surface of the probe angle adjusting mechanism is clamped with a probe seat, so that simultaneous adjustment of a plurality of probes can be realized, the test time is shortened, and the test efficiency is improved. Adjustment is carried out according to different wafer sizes to adapt to different test scenes; the angle of the probe is adjusted by adjusting the angle of the probe seat, so that the influence of resistance on a test signal is reduced in a low-resistance test.

Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

The invention discloses a clamping method for wafer test, which is used for loading a wafer into a test fixture, the test fixture comprises an upper cover plate, a lower substrate, a PCB (printed circuit board) mounted on the lower surface of the upper cover plate and a needle plate mounted in the center of the lower surface of the PCB and electrically connected with the PCB, and the upper surface of the lower substrate is provided with a groove for embedding the needle plate. A plurality of locking sleeves distributed at intervals in the circumferential direction are installed on the upper surface of the lower base plate and located on the outer side of the groove, a plurality of locking shells are correspondingly installed on the upper cover plate and located over the locking sleeves, and a first installation hole is formed in the upper surface of each locking shell. And a cap body part at the upper end of a lock rod capable of moving up and down is in sliding fit with the inner wall of the first mounting hole. On the basis that clamping, electric conduction, heating aging and inflation testing are carried out on the wafer in the sealing cavity, wafer installation is facilitated, synchronous locking and unlocking are achieved, pollution to the wafer is reduced, and the stability of locking force is kept all the time.

The invention relates to the technical field of wafer testing, and discloses a visual wafer identification probe station which comprises a processing table, a probe card, a bearing table assembly and an observation assembly. The probe card is selectively arranged on the processing table; the probe card comprises four groups of probe array assemblies; the bearing table assembly is used for driving the wafer to move in the space so as to be selectively matched with the probe card; the observation assembly comprises a driving assembly and four groups of visual monitoring assemblies, the four groups of visual monitoring assemblies are in one-to-one correspondence with the four groups of probe array assemblies, and the driving assembly is used for driving the four groups of visual monitoring assemblies to selectively monitor the corresponding probe array assemblies; the visual monitoring assembly comprises a camera and an adjusting assembly, and the adjusting assembly is used for adjusting the angle of the camera so as to monitor each probe body in the probe array assembly. The condition of the tip end of the probe body can be observed more accurately, so that the abrasion loss of the probe body can be compensated selectively, or the probe body or the probe card can be replaced selectively.

The utility model discloses a silicon optical wafer test device and an alignment coupling mechanism and a test system thereof. The alignment coupling mechanism comprises an optical fiber coupling module, a piezoelectric displacement table and a tail end connecting structure which are connected in sequence. The optical fiber coupling module comprises three translation assemblies and three rotating assemblies which are sequentially connected in series; the three translation assemblies are used for driving the tail end connecting structure to do translation motion in the first direction, the second direction and the third direction correspondingly. The three rotating assemblies are used for driving the tail end connecting structure to rotate with the first rotating shaft, the second rotating shaft and the third rotating shaft as the center correspondingly. The first direction, the second direction and the third direction are vertical in pairs; the first rotating shaft, the second rotating shaft and the third rotating shaft are perpendicular pairwise. Each assembly only needs to achieve motion adjustment on one degree of freedom, the function is single, precise control over motion adjustment is facilitated, all the assemblies only need to be sequentially connected in series, spliced and connected, implementation is simple and easy, and equipment cost can be reduced.

The invention relates to the technical field of wafer testing, and particularly provides a clamp for wafer aging test, which comprises a PCB (printed circuit board), the PCB is fixedly arranged below an upper cover plate, a fixer fixes a probe card below the PCB, the PCB covers a lower cover plate, and the fixer and the probe card are both positioned in a test cavity. The inner ring of the fixator protrudes inwards in the radial direction to form an annular bearing platform, the multiple positioning columns are installed on the surface of the bearing platform in an array mode in the circumferential direction, multiple positioning holes are formed in the edge of the probe card in the axial direction, each positioning column corresponds to one positioning hole in position, the positioning columns are embedded into the positioning holes, and the probe card is fixed to the bearing platform. A plurality of abutting columns with adjustable resilience force are elastically arranged on the side face of each positioning column in the circumferential direction, the tail ends of the abutting columns abut against the inner surfaces of the positioning holes, and the abutting columns can elastically move in the radial direction of the positioning columns. According to the invention, the problem of poor contact effect between the probe and the contact caused by deformation of the probe card due to a high-temperature atmosphere during an aging test can be avoided.

The invention provides a wafer testing device and method, and the device comprises a probe card table which comprises a probe card and a functional circuit, and the probe card is provided with a first-class bonding point and a second-class bonding point; the first-class bonding points and the second-class bonding points are electrically connected with chip pins of the wafer to be tested through probes; the two types of bonding points respectively correspond to different functional circuits; and the test console is in communication connection with the probe card table, is used for selecting a matched second-class bonding point according to the type of the wafer to be tested to be electrically connected with a chip pin of the wafer to be tested, and is also used for testing the wafer to be tested through the probe card table to obtain a test result. The probe card is provided with the first type of bonding points and the second type of bonding points, and the second type of bonding points can be flexibly selected according to the model of the to-be-tested wafer, so that the to-be-tested wafer is connected to different functional circuits, different functional tests are realized, the probe card table can be compatible with the to-be-tested wafers of different models, and the test efficiency is improved. The problem that existing ATE test equipment is poor in compatibility is solved.

The invention provides a wafer feeding and discharging machine, chip testing equipment and a control method thereof, and relates to the technical field of wafer testing. A conveying mechanism comprises a conveying disc used for conveying among a wafer feeding mechanism, a wafer discharging mechanism and a testing machine, the conveying disc is provided with a feeding area and a discharging area, the feeding area is used for placing a to-be-tested chip, and the discharging area is used for placing a tested chip. A first adsorption assembly of the loading and unloading carrying mechanism is used for carrying a tested chip on the wafer loading mechanism to the loading area, and a second adsorption assembly is used for carrying a tested chip in the unloading area to the wafer unloading mechanism. According to the technical scheme, the same conveying disc is adopted to carry the to-be-tested chips and the tested chips, discharging can be carried out while feeding is carried out, the conveying frequency can be reduced, and therefore the testing efficiency of the chips is improved.

The invention relates to the technical field of wafer testing, and discloses a wafer testing probe card and a wafer testing device. The discharging opening is formed in the outer surface wall of the machine shell; the control panel is fixedly installed on the side face of the machine shell. The movable seat is movably mounted on the inner bottom wall of the machine shell; the lifting seat is fixedly mounted on the top surface of the moving seat; and the detection seat is arranged at the top end of the lifting seat. Through the arrangement of the air blowing assembly, when the detection seat drives the wafer to move up and down, the pressing plate compresses or stretches the air guide bag along with pressing and releasing of the supporting plate, periodic compression and stretching of the air guide bag are controlled through the one-way valve between the guide pipe and the nozzle, intermittent air blowing to the probe is formed, extra energy supply is not needed, and the detection efficiency is improved. And moreover, the real-time performance and continuity of probe cleaning are realized, continuous cleaning of the surface of the probe in the test process is ensured, and test errors and chip damage caused by probe pollution are effectively prevented.

The invention discloses a metalized guide plate for a probe card and a manufacturing method thereof, and the method comprises the following steps: providing a substrate made of an insulating material, and carrying out the flattening of the two opposite side surfaces of the substrate; processing and drilling are conducted on the substrate, and a needle planting hole penetrating through the substrate is formed; performing photoetching on two opposite side surfaces of the substrate respectively to form photoresist layers; first conductive materials are deposited on the two opposite side surfaces of the substrate respectively, so that seed layers are formed on the inner wall surfaces of at least part of the needle planting holes and the two opposite side surfaces, corresponding to the at least part of the needle planting holes, of the substrate; electroplating a second conductive material on the surface of the seed layer to form an electroplated layer on the surface of the seed layer; and cleaning the substrate and removing the photoresist layer to obtain the metalized guide plate with the pattern circuit, so that the metalized guide plate has relatively high current resistance, and the stability of the probe card for high-current and high-power-consumption wafer test can be improved. The method is stable and controllable, high in yield and low in risk.

The utility model discloses silicon optical wafer test equipment. The silicon optical wafer test equipment comprises a camera assembly, a deflection optical path assembly, a probe station and an optical fiber coupling module, the driving assembly is used for driving the probe station and the deflection optical path assembly to move to the lower part of the camera assembly and the optical fiber end part of the optical fiber array in a mutual switching manner; the optical fiber coupling module is used for clamping the optical fiber end part of the optical fiber array; when the probe station moves to the position below the camera assembly, a cross cursor of a camera of the camera assembly is adjusted to be parallel to a cutting channel of the silicon optical wafer; when the deflection light path assembly moves into the imaging view field of the camera assembly, the camera assembly is used for collecting a first lateral image and a second lateral image through the deflection light path assembly and collecting a vertical image; and adjusting the end part of the optical fiber by using an optical fiber coupling module according to the image, so that the end part of the optical fiber and the optical waveguide are aligned and coupled. According to the application, the operation difficulty and the equipment structure for realizing alignment coupling between the optical fiber end part and the silicon optical waveguide are simplified, and the equipment cost is reduced.

The invention provides a probe card tip condition detection method, a probe card tip condition detection structure, a wafer and a wafer test method, and relates to a probe card tip condition detection method, which comprises the following steps: determining a plurality of probes to be tested of a probe card; a plurality of probe pads are determined, and a metal wire structure is arranged between every two probe pads in sequence so as to be connected to form a test circuit; probes to be tested are inserted into the corresponding probe pads for contact connection; dividing and designing a plurality of test groups based on the positions of the probe pads in the test circuit, and measuring the contact resistance of the to-be-tested probes and the corresponding probe pads; and judging the tip state of the to-be-tested probe based on the contact resistance of the to-be-tested probe and the corresponding probe pad. The probe point condition of the probe card is monitored by using an electrical test means, so that the test cost is reduced, and the test accuracy and the detection efficiency are further improved.

The invention belongs to the technical field of semiconductor wafer testing, and discloses a semiconductor wafer testing transfer device and a transfer method thereof.The semiconductor wafer testing transfer device comprises a transfer frame body, a protective cover is arranged at the top of the transfer frame body, a supporting frame is arranged in the transfer frame body, and a supporting rod is arranged in the supporting frame; the two ends of the supporting rod are each sleeved with an attaching block, vertical blocks are arranged at the bottoms of the two attaching blocks, clamping and conveying plates are arranged at the bottoms of the two vertical blocks, the supporting rod, the vertical blocks, the clamping and conveying plates, the leveling frame, the guiding and conveying plate, the buffering block and the receiving and conveying frame are matched, so that the device moves at one end of the supporting rod, and under the connection of the vertical blocks and the clamping and conveying plates, the clamping and conveying plates can move at one end of the supporting rod. The two leveling frames are driven to move when the semiconductor wafer is conveyed, position deviation during conveying of the semiconductor wafer is avoided, the conveying quality of the semiconductor wafer by the conveying device is improved, and the semiconductor wafer is conveyed to the surface of the guiding and conveying plate and conveyed to the interior of the receiving and conveying frame along the inclined guiding and conveying plate.

The invention relates to the technical field of semiconductor manufacturing equipment, in particular to a wafer test lifting mechanism, which comprises a bearing plate; the center driving device is located on the side, away from the bearing face, of the bearing plate, the center of the center driving device right faces the center of the bearing plate, the free end of the center driving device is connected with the bearing plate, and the free end of the center driving device can drive the bearing plate to do lifting motion in the z-axis direction; the four supporting driving devices are arranged on the periphery of the center driving device at intervals, the four supporting driving devices are located on the side, away from the bearing face, of the bearing plate, the four supporting driving devices correspond to the four corners of the bearing plate one to one, and the free ends of the supporting driving devices are in non-connection contact with the bearing plate; the free end of the supporting driving device and the free end of the center driving device synchronously ascend and descend in the z-axis direction. According to the invention, the wafer test requirements under the working conditions of large load and unbalance load can be met at least.

The invention provides a wafer test needle trace position intelligent calibration method and system based on multi-modal data, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: obtaining a wafer needle trace image and probe card contact force data, employing a radial polar coordinate convolution network to extract needle trace morphology features, and obtaining a wafer test needle trace position; the pressure and deformation relation is modeled by combining a five-layer full-connection neural network, the needle trace position deviation is calculated after feature fusion, calibration parameters are obtained based on multi-objective optimization functions such as position precision, contact stability and needle tip service life, the probe position is accurately adjusted, the test precision and efficiency are improved, and the service life of a probe card is prolonged.