499 results about "Wafer testing" patented technology

The invention provides a wafer-level test yield prediction and process optimization method and system based on big data, and relates to the technical field of wafer-level tests.The wafer-level test yield prediction and process optimization method comprises the steps that wafer manufacturing process data is obtained, a time-sequence-sensitive multi-modal data fusion network is constructed, a LSTM and GNN combined mixed architecture is adopted, and a multi-modal data fusion network is constructed; self-adaptive weight distribution is carried out through an attention mechanism to predict the yield; and when the predicted yield is lower than a threshold value, triggering a layered progressive process optimization system, and adjusting process parameters through an equipment parameter optimization layer and a process level optimization layer. According to the invention, the accurate prediction of the wafer test yield and the automatic optimization of the process parameters are realized, the production efficiency is improved, and the manufacturing cost is reduced.

The invention provides a multi-probe array real-time pressure optimization and control method for wafer testing, and relates to the technical field of semiconductor testing, and the method comprises the steps: collecting real-time pressure data and a wafer stress limit value, building an initial distribution state, calculating the contact area and angle through displacement, determining a stress concentration factor, and carrying out the pressure correction, calculating strain rate distribution to identify a sensitive area to perform pressure compensation, monitoring a stress-strain ratio to identify a microcrack initiation point to determine an optimal pressurization parameter, and performing real-time monitoring and early warning. According to the invention, the damage risk in the wafer testing process can be reduced, and the testing precision and the yield can be improved.

The embodiment of the invention provides a wafer testing device and testing method, and belongs to the technical field of wafer testing. The wafer testing device comprises an MEMS probe chip installed and connected on a testing machine, and a testing position used for fixing a tested chip. A test contact of a probe of the MEMS probe chip is in contact with a PAD of a tested chip during testing, and the MEMS probe chip is used for collecting a detection signal of the tested chip; wherein a probe of the MEMS probe chip is integrated in the MEMS probe chip based on a cantilever beam type; and the test machine is used for generating a test result corresponding to the tested chip based on the detection signal of the tested chip. The MEMS probe chip in the scheme of the invention adopts a modular design, is convenient to quickly replace, reduces the maintenance cost and time, and provides a better solution for the test requirements of high-frequency and high-density packaged chips.

The invention provides a wafer test data processing method and device, equipment and a medium, and can be applied to the technical field of chips. The method comprises the following steps: acquiring a standard test data file generated when a wafer is tested; analyzing the standard test data file to obtain data files respectively corresponding to the plurality of data types; wherein the data file comprises test record data belonging to a corresponding data type; based on the data files corresponding to the multiple data types respectively, respectively generating analyzable data corresponding to each preset category in the multiple preset categories; and outputting the analyzable data corresponding to each preset category. According to the invention, automatic analysis and classification of the wafer test data are realized, and the efficiency is high.

The invention relates to the technical field of wafer test equipment, in particular to a heating aging test tool which comprises a storage rack and further comprises a wafer clamp placed on the storage rack. The detection assembly comprises a plurality of elastic probes located on one side of the storage rack and a heating disc; and the hot air guide assembly comprises a ventilation male head arranged on one side of the heating disc, an air guide pipe is arranged on the side, away from the ventilation male head, of the heat conduction cover, the air amount in the cavity is gradually decreased from near to far away from the air guide pipe, and the air flow speed is gradually decreased. A hot air flow guide assembly is arranged on a conveying frame, heat of a heating disc is guided to the position above a wafer through airflow through a heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow speed and the contained hot air amount of each space are adjusted, and therefore the heat conduction efficiency of the wafer is improved. The influence of heat loss in the air flow process is reduced, so that the heating effects of all parts of the wafer are similar, and the detection effect is improved.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention relates to the technical field of wafer testing, and discloses a visual wafer identification probe station which comprises a processing table, a probe card, a bearing table assembly and an observation assembly. The probe card is selectively arranged on the processing table; the probe card comprises four groups of probe array assemblies; the bearing table assembly is used for driving the wafer to move in the space so as to be selectively matched with the probe card; the observation assembly comprises a driving assembly and four groups of visual monitoring assemblies, the four groups of visual monitoring assemblies are in one-to-one correspondence with the four groups of probe array assemblies, and the driving assembly is used for driving the four groups of visual monitoring assemblies to selectively monitor the corresponding probe array assemblies; the visual monitoring assembly comprises a camera and an adjusting assembly, and the adjusting assembly is used for adjusting the angle of the camera so as to monitor each probe body in the probe array assembly. The condition of the tip end of the probe body can be observed more accurately, so that the abrasion loss of the probe body can be compensated selectively, or the probe body or the probe card can be replaced selectively.

The utility model discloses a silicon optical wafer test device and an alignment coupling mechanism and a test system thereof. The alignment coupling mechanism comprises an optical fiber coupling module, a piezoelectric displacement table and a tail end connecting structure which are connected in sequence. The optical fiber coupling module comprises three translation assemblies and three rotating assemblies which are sequentially connected in series; the three translation assemblies are used for driving the tail end connecting structure to do translation motion in the first direction, the second direction and the third direction correspondingly. The three rotating assemblies are used for driving the tail end connecting structure to rotate with the first rotating shaft, the second rotating shaft and the third rotating shaft as the center correspondingly. The first direction, the second direction and the third direction are vertical in pairs; the first rotating shaft, the second rotating shaft and the third rotating shaft are perpendicular pairwise. Each assembly only needs to achieve motion adjustment on one degree of freedom, the function is single, precise control over motion adjustment is facilitated, all the assemblies only need to be sequentially connected in series, spliced and connected, implementation is simple and easy, and equipment cost can be reduced.

The invention relates to the technical field of wafer testing, and particularly provides a clamp for wafer aging test, which comprises a PCB (printed circuit board), the PCB is fixedly arranged below an upper cover plate, a fixer fixes a probe card below the PCB, the PCB covers a lower cover plate, and the fixer and the probe card are both positioned in a test cavity. The inner ring of the fixator protrudes inwards in the radial direction to form an annular bearing platform, the multiple positioning columns are installed on the surface of the bearing platform in an array mode in the circumferential direction, multiple positioning holes are formed in the edge of the probe card in the axial direction, each positioning column corresponds to one positioning hole in position, the positioning columns are embedded into the positioning holes, and the probe card is fixed to the bearing platform. A plurality of abutting columns with adjustable resilience force are elastically arranged on the side face of each positioning column in the circumferential direction, the tail ends of the abutting columns abut against the inner surfaces of the positioning holes, and the abutting columns can elastically move in the radial direction of the positioning columns. According to the invention, the problem of poor contact effect between the probe and the contact caused by deformation of the probe card due to a high-temperature atmosphere during an aging test can be avoided.

The invention provides a wafer feeding and discharging machine, chip testing equipment and a control method thereof, and relates to the technical field of wafer testing. A conveying mechanism comprises a conveying disc used for conveying among a wafer feeding mechanism, a wafer discharging mechanism and a testing machine, the conveying disc is provided with a feeding area and a discharging area, the feeding area is used for placing a to-be-tested chip, and the discharging area is used for placing a tested chip. A first adsorption assembly of the loading and unloading carrying mechanism is used for carrying a tested chip on the wafer loading mechanism to the loading area, and a second adsorption assembly is used for carrying a tested chip in the unloading area to the wafer unloading mechanism. According to the technical scheme, the same conveying disc is adopted to carry the to-be-tested chips and the tested chips, discharging can be carried out while feeding is carried out, the conveying frequency can be reduced, and therefore the testing efficiency of the chips is improved.

The utility model discloses silicon optical wafer test equipment. The silicon optical wafer test equipment comprises a camera assembly, a deflection optical path assembly, a probe station and an optical fiber coupling module, the driving assembly is used for driving the probe station and the deflection optical path assembly to move to the lower part of the camera assembly and the optical fiber end part of the optical fiber array in a mutual switching manner; the optical fiber coupling module is used for clamping the optical fiber end part of the optical fiber array; when the probe station moves to the position below the camera assembly, a cross cursor of a camera of the camera assembly is adjusted to be parallel to a cutting channel of the silicon optical wafer; when the deflection light path assembly moves into the imaging view field of the camera assembly, the camera assembly is used for collecting a first lateral image and a second lateral image through the deflection light path assembly and collecting a vertical image; and adjusting the end part of the optical fiber by using an optical fiber coupling module according to the image, so that the end part of the optical fiber and the optical waveguide are aligned and coupled. According to the application, the operation difficulty and the equipment structure for realizing alignment coupling between the optical fiber end part and the silicon optical waveguide are simplified, and the equipment cost is reduced.

The invention relates to the technical field of semiconductor manufacturing equipment, in particular to a wafer test lifting mechanism, which comprises a bearing plate; the center driving device is located on the side, away from the bearing face, of the bearing plate, the center of the center driving device right faces the center of the bearing plate, the free end of the center driving device is connected with the bearing plate, and the free end of the center driving device can drive the bearing plate to do lifting motion in the z-axis direction; the four supporting driving devices are arranged on the periphery of the center driving device at intervals, the four supporting driving devices are located on the side, away from the bearing face, of the bearing plate, the four supporting driving devices correspond to the four corners of the bearing plate one to one, and the free ends of the supporting driving devices are in non-connection contact with the bearing plate; the free end of the supporting driving device and the free end of the center driving device synchronously ascend and descend in the z-axis direction. According to the invention, the wafer test requirements under the working conditions of large load and unbalance load can be met at least.

The invention provides a wafer test needle trace position intelligent calibration method and system based on multi-modal data, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: obtaining a wafer needle trace image and probe card contact force data, employing a radial polar coordinate convolution network to extract needle trace morphology features, and obtaining a wafer test needle trace position; the pressure and deformation relation is modeled by combining a five-layer full-connection neural network, the needle trace position deviation is calculated after feature fusion, calibration parameters are obtained based on multi-objective optimization functions such as position precision, contact stability and needle tip service life, the probe position is accurately adjusted, the test precision and efficiency are improved, and the service life of a probe card is prolonged.

The invention relates to the technical field of wafer testing, in particular to a wafer testing result visualization method and system. Through spatial discretization processing, continuous physical coordinates of test points are mapped to a fixed N * N regular grid, and mass and disordered coordinate points are classified into limited and ordered grid units through the conversion, so that the complexity of data positioning is reduced from O (n) to O (1). When rendering is carried out, a system can directly access grid data at any position through simple coordinate transformation without traversing all test points based on a data structure established on the basis of the regular grid. More importantly, the rendering mode is dynamically selected and drawn, so that the rendering calculation amount of the system does not depend on the total amount of test points any more, but depends on the number of grids in the current viewport. And the processing object is fundamentally optimized from a'test point 'to a'viewport inner grid', so that the data processing and rendering efficiency is greatly improved.

The invention discloses a wafer yield analysis method and device, and belongs to the technical field of semiconductor quality detection, and the method comprises the following steps: obtaining wafer defect data which comprises defect quantification data of each minimum segmentation unit on a wafer; wafer test data are obtained, and the wafer test data comprise electrical performance parameters corresponding to each test unit; according to the wafer defect data and the wafer test data, training a deep learning neural network to obtain a wafer defect prediction model; predicting a defect threshold value in the current tape-out step according to the wafer defect prediction model; and when the number of certain defects exceeds a defect threshold value, triggering a reworking process. According to the method, the deep learning neural network is trained through the defect quantification data and the corresponding wafer test data to obtain the mapping relation between the wafer defects and the electrical properties, so that the types of the wafer defects are associated with the wafer yield, the wafer yield is fed back to the corresponding tape-out step, and real-time monitoring of the process is realized.

The invention relates to the technical field of semiconductor wafer testing, in particular to a method for detecting Map Shift abnormity in wafer testing, which specifically comprises the following steps of: establishing Prober formula parameters, generating a wafer sample according to the Prober formula parameters, and testing the wafer sample to generate an MAP (0) file; analyzing the MAP (0) file, and obtaining and storing center grain coordinate information of the sample wafer as a standard comparison value; the test wafer generates a corresponding test result MAP (i) file; the MAP (i) file of the wafer is analyzed, and center grain coordinate information of the wafer is obtained; comparing the coordinates of the central crystal grains of the wafer; according to the method, the core coordinate parameters used when the Prober generates the MAP can be directly compared, the judgment is direct, the influence of the wafer edge yield distribution is avoided, the accuracy is high, the misjudgment caused by the product yield characteristic is effectively avoided, and the false alarm rate is reduced.

The invention provides a wafer test probe pressure control method and system, electronic equipment and a storage medium. The method comprises the following steps: acquiring probe card information and to-be-tested product information configured for a current test task; based on the probe card information and the to-be-tested product information, extracting a corresponding multi-dimensional parameter set from a pre-established probe card comprehensive parameter database; inputting the multi-dimensional parameter set into a preset probe pressure optimization model, and calculating a probe pressure control interval suitable for the current test task; sending the probe pressure control interval to a production execution system in communication connection with the probe station; executing the current test task under the control of the production execution system, and collecting an actual probe pressure value applied by the probe station in real time through the production execution system; in response to the fact that the actual needle pressure value exceeds the needle pressure control interval, the production execution system is triggered to execute needle pressure abnormal control operation, and the problem that the needle mark is large due to the fact that non-optimal fixed needle pressure is used is solved.

The invention discloses a wafer test data processing method, electronic equipment and a computer readable medium, and the method comprises the steps: analyzing binary wafer test data into structured wafer test data according to a binary file format specification of the binary wafer test data and a preset data analysis mode; wherein the structured wafer test data comprises global metadata and chip test data of each chip stored in a two-dimensional array, the chip test data comprises a BIN number and a test result state, and the test result state comprises one of a pass state and a failure state; rendering the structured wafer test data to a wafer graph storage file; and generating a test report file according to the wafer graph storage file. The time period from testing to report generation can be shortened, the wafer testing efficiency is improved, the accuracy and reliability of the wafer graph and the testing report are improved, the manpower demand can be reduced, the operation cost can be reduced, and resources are saved.

The invention relates to the technical field of temperature change testing, and provides a rapid temperature change test box for wafer testing, which comprises an experimental device, a test box is installed on one side of the experimental device, a partition device is installed in the middle of the middle of the interior of the test box, and a sliding assembly is sleeved with the partition device. The upper end of the sliding assembly is fixedly connected with a driving device, and the driving device penetrates through the top of the test box and is installed above the test box. The wafer clamp flexibly clamps the wafer, stacking of the wafer during testing is avoided, the wafer is connected with the clamping block through the rotating disc, and the rotating fan rotates along with cold air or hot air, so that hot air or cold air swollen in a temperature change experiment can be conveniently gathered around the wafer and fully and comprehensively contacted with the wafer, the accuracy of the experiment is ensured, and the test efficiency is improved. And meanwhile, the rotating fan drives the wafer clamped by the rotating disc to rotate in the wafer clamp, so that water drops generated by heat release and condensation of air on the surface of the wafer are wiped by the brush strip, and the phenomenon that the test result is easily influenced due to corrosion of the wafer is prevented.

The invention provides wafer testing equipment, and relates to the technical field of wafer testing. A heating part, a test probe assembly and a tested wafer are placed in a test cavity formed by connecting a test seat and a first PCB (printed circuit board), a first Pad position is arranged at the bottom of the test seat, and a first switching probe is in contact with the heating part and is connected with the first Pad position. The switching assembly and the power-up mechanism are located at the bottom of the wafer test fixture, and the driving mechanism is located at the top of the wafer test fixture and is arranged to controllably drive the wafer test fixture to move downwards, so that the first PCB is in contact with the switching assembly and the first Pad position is in contact with the household appliance mechanism, and the test of the tested wafer is realized. According to the technical scheme, the heating component is placed in the testing cavity and is close to the tested wafer, generated heat can be quickly transferred to the tested wafer, the temperature rise rate is high, the high-temperature testing efficiency of the tested wafer is improved, and the influence on the environment temperature is small.

The embodiment of the invention discloses a chip grading method and a related device, relates to the technical field of integrated circuits, and can improve the accuracy of chip grading and effectively reduce resource waste. The method comprises the steps that the mapping relation among a first parameter, a second parameter and a third parameter of a chip sample is determined, a grading auxiliary function is obtained, the first parameter and the second parameter are obtained by conducting wafer testing on the chip sample, and the third parameter is obtained by conducting testing after packaging on the chip sample; obtaining a parameter value of a first parameter and a parameter value of a second parameter of a to-be-graded chip, and grading the to-be-graded chip according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and grading description information of the to-be-graded chip, the grading description information is used for describing a corresponding relation between different grades of the chip and the value interval of the third parameter. The chip grading method is suitable for grading various chips.

The present application provides a method and structure for detecting the tip condition of a probe card, a wafer, and a wafer testing method. It relates to a method for detecting the tip condition of a probe card, including: determining a plurality of probes to be tested on the probe card; determining a plurality of probe pads, and sequentially arranging a metal wire structure between two probe pads to form a test circuit by connection; respectively inserting the probes to be tested into the corresponding probe pads for contact connection; dividing and designing a plurality of test groups based on the positions of the probe pads in the test circuit, and measuring the contact resistance between the probes to be tested and the corresponding probe pads; and judging the tip state of the probes to be tested based on the contact resistance between the probes to be tested and the corresponding probe pads. The present application monitors the tip condition of the probe card by means of electrical testing, which not only reduces the testing cost, but also further improves the testing accuracy and detection efficiency.

Present disclosure relates to field of semiconductor manufacturing, provides photonic integrated chip, array and testing method thereof. Chip includes functional assembly, light test assembly and electric test assembly manufactured through semiconductor process. Light test assembly and electric test assembly are connected respectively to different sides of functional assembly; functional assembly includes N functional units, and N is positive integer; each functional unit includes optical interface and first pad; first pad is configured to input or output electric signal in working environment; light test assembly includes main beam port and light splitting unit; input end of light splitting unit connects with main beam port; a plurality of output ends of light splitting unit connect with optical interfaces of N functional units; electric test assembly connects electrically with first pads, configured to test electrical performance of N functional units. Chip is configured to improve photoelectric test efficiency during wafer test.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

A probe system includes a wafer cassette, a wafer processing device, a computer and a transfer assembly. The wafer cassette stores a plurality of wafers. The wafer processing device is configured to test the wafer. The computer stores a test recipe, displays a plurality of virtual wafers corresponding to the plurality of first wafer cassette, creates a first virtual wafer group by selecting one or more virtual wafers from the first virtual wafer group, wherein the first virtual wafer group corresponds to the test recipe, and issues a load command. The transfer assembly transfers a selected wafer, which is one of the plurality of wafers stored in the first wafer cassette corresponding to a first virtual wafer within the first virtual wafer group, to the wafer processing device according to the load command for testing, wherein the wafer processing device tests the selected wafer based on the test recipe.

The invention relates to a lithium battery charging chip test method and circuit, and the method comprises the steps: distributing corresponding test resources according to the attribute information of each pin in a charging chip, building a connection, carrying out a pin connectivity test, collecting each performance parameter of the charging chip, comparing the performance parameters with a preset target specification value, and obtaining a test result. Generating a corresponding parameter deviation vector; inputting the parameter deviation vector into a trimming model, calculating a corresponding trimming parameter vector, and encoding the trimming parameter vector into corresponding EFUSE target configuration data; according to the method, target EFUSE configuration data is written into a charging chip in a segmented mode, all the written content of the EFUSE in the charging chip is read, integrity comparison is conducted on all the written content and a pre-stored standard signature, the certainty and traceability of the EFUSE burning process in the wafer testing stage are improved, and the reliability of the EFUSE burning process in the wafer testing stage is improved. The chip waste rate caused by mismatching of test resources or unstable write-in control is reduced, parallel testing of multiple chips can be supported, and the mass production test efficiency and the overall production line yield are improved.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The invention provides a heat sink and wafer feeding and discharging device, and relates to the technical field of wafer testing. The bearing platform is provided with the bearing structure used for bearing the heat sink, and the bearing structure is further provided with the notch. The pushing mechanism is installed at the notch and comprises a first driving part and a push rod which are in transmission connection, and under driving of the first driving part, the push rod moves in the direction close to the heat sink and pushes the heat sink, so that the outer side wall of the heat sink abuts against the inner wall of the bearing structure, and therefore the heat sink is positioned. According to the technical scheme, the pushing mechanism is integrated on the bearing platform, positioning of the heat sink can be achieved only by pushing the outer side wall of the heat sink to abut against the inner wall of the bearing structure through the push rod, the structure is simple, and the occupied space is small.

The invention provides a wafer test data processing method and device, electronic equipment and a medium, and relates to the technical field of wafer testing, and the method comprises the steps: obtaining a test sequence composed of test data of a plurality of DIEs on a target wafer; dividing a plurality of test data in the test sequence to obtain a plurality of subsequences; converting the test data in each sub-sequence to obtain a target sub-sequence; and deleting the target subsequences meeting the deletion conditions in the corresponding processing threads. Through the BS architecture and the memory optimization technology, the problem of memory overflow when a traditional CS architecture processes large-scale wafer test data is effectively solved. The processing efficiency and the response speed of the system are improved through the technologies of data block processing, streaming processing, asynchronous generation and the like. The stability and the reliability of the system are enhanced by optimizing the memory use and the data processing flow.