352 results about "Wafer testing" patented technology

The invention relates to the technical field of wafer test equipment, in particular to a heating aging test tool which comprises a storage rack and further comprises a wafer clamp placed on the storage rack. The detection assembly comprises a plurality of elastic probes located on one side of the storage rack and a heating disc; and the hot air guide assembly comprises a ventilation male head arranged on one side of the heating disc, an air guide pipe is arranged on the side, away from the ventilation male head, of the heat conduction cover, the air amount in the cavity is gradually decreased from near to far away from the air guide pipe, and the air flow speed is gradually decreased. A hot air flow guide assembly is arranged on a conveying frame, heat of a heating disc is guided to the position above a wafer through airflow through a heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow speed and the contained hot air amount of each space are adjusted, and therefore the heat conduction efficiency of the wafer is improved. The influence of heat loss in the air flow process is reduced, so that the heating effects of all parts of the wafer are similar, and the detection effect is improved.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention relates to the technical field of wafer testing, and discloses a visual wafer identification probe station which comprises a processing table, a probe card, a bearing table assembly and an observation assembly. The probe card is selectively arranged on the processing table; the probe card comprises four groups of probe array assemblies; the bearing table assembly is used for driving the wafer to move in the space so as to be selectively matched with the probe card; the observation assembly comprises a driving assembly and four groups of visual monitoring assemblies, the four groups of visual monitoring assemblies are in one-to-one correspondence with the four groups of probe array assemblies, and the driving assembly is used for driving the four groups of visual monitoring assemblies to selectively monitor the corresponding probe array assemblies; the visual monitoring assembly comprises a camera and an adjusting assembly, and the adjusting assembly is used for adjusting the angle of the camera so as to monitor each probe body in the probe array assembly. The condition of the tip end of the probe body can be observed more accurately, so that the abrasion loss of the probe body can be compensated selectively, or the probe body or the probe card can be replaced selectively.

The utility model discloses a silicon optical wafer test device and an alignment coupling mechanism and a test system thereof. The alignment coupling mechanism comprises an optical fiber coupling module, a piezoelectric displacement table and a tail end connecting structure which are connected in sequence. The optical fiber coupling module comprises three translation assemblies and three rotating assemblies which are sequentially connected in series; the three translation assemblies are used for driving the tail end connecting structure to do translation motion in the first direction, the second direction and the third direction correspondingly. The three rotating assemblies are used for driving the tail end connecting structure to rotate with the first rotating shaft, the second rotating shaft and the third rotating shaft as the center correspondingly. The first direction, the second direction and the third direction are vertical in pairs; the first rotating shaft, the second rotating shaft and the third rotating shaft are perpendicular pairwise. Each assembly only needs to achieve motion adjustment on one degree of freedom, the function is single, precise control over motion adjustment is facilitated, all the assemblies only need to be sequentially connected in series, spliced and connected, implementation is simple and easy, and equipment cost can be reduced.

The invention relates to the technical field of wafer testing, and particularly provides a clamp for wafer aging test, which comprises a PCB (printed circuit board), the PCB is fixedly arranged below an upper cover plate, a fixer fixes a probe card below the PCB, the PCB covers a lower cover plate, and the fixer and the probe card are both positioned in a test cavity. The inner ring of the fixator protrudes inwards in the radial direction to form an annular bearing platform, the multiple positioning columns are installed on the surface of the bearing platform in an array mode in the circumferential direction, multiple positioning holes are formed in the edge of the probe card in the axial direction, each positioning column corresponds to one positioning hole in position, the positioning columns are embedded into the positioning holes, and the probe card is fixed to the bearing platform. A plurality of abutting columns with adjustable resilience force are elastically arranged on the side face of each positioning column in the circumferential direction, the tail ends of the abutting columns abut against the inner surfaces of the positioning holes, and the abutting columns can elastically move in the radial direction of the positioning columns. According to the invention, the problem of poor contact effect between the probe and the contact caused by deformation of the probe card due to a high-temperature atmosphere during an aging test can be avoided.

The utility model discloses silicon optical wafer test equipment. The silicon optical wafer test equipment comprises a camera assembly, a deflection optical path assembly, a probe station and an optical fiber coupling module, the driving assembly is used for driving the probe station and the deflection optical path assembly to move to the lower part of the camera assembly and the optical fiber end part of the optical fiber array in a mutual switching manner; the optical fiber coupling module is used for clamping the optical fiber end part of the optical fiber array; when the probe station moves to the position below the camera assembly, a cross cursor of a camera of the camera assembly is adjusted to be parallel to a cutting channel of the silicon optical wafer; when the deflection light path assembly moves into the imaging view field of the camera assembly, the camera assembly is used for collecting a first lateral image and a second lateral image through the deflection light path assembly and collecting a vertical image; and adjusting the end part of the optical fiber by using an optical fiber coupling module according to the image, so that the end part of the optical fiber and the optical waveguide are aligned and coupled. According to the application, the operation difficulty and the equipment structure for realizing alignment coupling between the optical fiber end part and the silicon optical waveguide are simplified, and the equipment cost is reduced.

The invention relates to the technical field of wafer testing, in particular to a wafer testing result visualization method and system. Through spatial discretization processing, continuous physical coordinates of test points are mapped to a fixed N * N regular grid, and mass and disordered coordinate points are classified into limited and ordered grid units through the conversion, so that the complexity of data positioning is reduced from O (n) to O (1). When rendering is carried out, a system can directly access grid data at any position through simple coordinate transformation without traversing all test points based on a data structure established on the basis of the regular grid. More importantly, the rendering mode is dynamically selected and drawn, so that the rendering calculation amount of the system does not depend on the total amount of test points any more, but depends on the number of grids in the current viewport. And the processing object is fundamentally optimized from a'test point 'to a'viewport inner grid', so that the data processing and rendering efficiency is greatly improved.

The invention discloses a wafer yield analysis method and device, and belongs to the technical field of semiconductor quality detection, and the method comprises the following steps: obtaining wafer defect data which comprises defect quantification data of each minimum segmentation unit on a wafer; wafer test data are obtained, and the wafer test data comprise electrical performance parameters corresponding to each test unit; according to the wafer defect data and the wafer test data, training a deep learning neural network to obtain a wafer defect prediction model; predicting a defect threshold value in the current tape-out step according to the wafer defect prediction model; and when the number of certain defects exceeds a defect threshold value, triggering a reworking process. According to the method, the deep learning neural network is trained through the defect quantification data and the corresponding wafer test data to obtain the mapping relation between the wafer defects and the electrical properties, so that the types of the wafer defects are associated with the wafer yield, the wafer yield is fed back to the corresponding tape-out step, and real-time monitoring of the process is realized.

The invention relates to the technical field of semiconductor wafer testing, in particular to a method for detecting Map Shift abnormity in wafer testing, which specifically comprises the following steps of: establishing Prober formula parameters, generating a wafer sample according to the Prober formula parameters, and testing the wafer sample to generate an MAP (0) file; analyzing the MAP (0) file, and obtaining and storing center grain coordinate information of the sample wafer as a standard comparison value; the test wafer generates a corresponding test result MAP (i) file; the MAP (i) file of the wafer is analyzed, and center grain coordinate information of the wafer is obtained; comparing the coordinates of the central crystal grains of the wafer; according to the method, the core coordinate parameters used when the Prober generates the MAP can be directly compared, the judgment is direct, the influence of the wafer edge yield distribution is avoided, the accuracy is high, the misjudgment caused by the product yield characteristic is effectively avoided, and the false alarm rate is reduced.

The invention provides a wafer test probe pressure control method and system, electronic equipment and a storage medium. The method comprises the following steps: acquiring probe card information and to-be-tested product information configured for a current test task; based on the probe card information and the to-be-tested product information, extracting a corresponding multi-dimensional parameter set from a pre-established probe card comprehensive parameter database; inputting the multi-dimensional parameter set into a preset probe pressure optimization model, and calculating a probe pressure control interval suitable for the current test task; sending the probe pressure control interval to a production execution system in communication connection with the probe station; executing the current test task under the control of the production execution system, and collecting an actual probe pressure value applied by the probe station in real time through the production execution system; in response to the fact that the actual needle pressure value exceeds the needle pressure control interval, the production execution system is triggered to execute needle pressure abnormal control operation, and the problem that the needle mark is large due to the fact that non-optimal fixed needle pressure is used is solved.

The embodiment of the invention discloses a chip grading method and a related device, relates to the technical field of integrated circuits, and can improve the accuracy of chip grading and effectively reduce resource waste. The method comprises the steps that the mapping relation among a first parameter, a second parameter and a third parameter of a chip sample is determined, a grading auxiliary function is obtained, the first parameter and the second parameter are obtained by conducting wafer testing on the chip sample, and the third parameter is obtained by conducting testing after packaging on the chip sample; obtaining a parameter value of a first parameter and a parameter value of a second parameter of a to-be-graded chip, and grading the to-be-graded chip according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and grading description information of the to-be-graded chip, the grading description information is used for describing a corresponding relation between different grades of the chip and the value interval of the third parameter. The chip grading method is suitable for grading various chips.

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

The invention relates to a lithium battery charging chip test method and circuit, and the method comprises the steps: distributing corresponding test resources according to the attribute information of each pin in a charging chip, building a connection, carrying out a pin connectivity test, collecting each performance parameter of the charging chip, comparing the performance parameters with a preset target specification value, and obtaining a test result. Generating a corresponding parameter deviation vector; inputting the parameter deviation vector into a trimming model, calculating a corresponding trimming parameter vector, and encoding the trimming parameter vector into corresponding EFUSE target configuration data; according to the method, target EFUSE configuration data is written into a charging chip in a segmented mode, all the written content of the EFUSE in the charging chip is read, integrity comparison is conducted on all the written content and a pre-stored standard signature, the certainty and traceability of the EFUSE burning process in the wafer testing stage are improved, and the reliability of the EFUSE burning process in the wafer testing stage is improved. The chip waste rate caused by mismatching of test resources or unstable write-in control is reduced, parallel testing of multiple chips can be supported, and the mass production test efficiency and the overall production line yield are improved.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The application provides a wafer test probe card and a wafer test system. The wafer test probe card provided by the application comprises a mainboard, an interface assembly and a detection assembly. The interface assembly is arranged between the mainboard and the detection assembly. The mainboard comprises m first resource configuration modules. The detection assembly comprises a resource assembly module. The first resource configuration modules and the resource assembly module are connected through the interface assembly. The wafer test probe card provided by the application splits the construction of a test resource circuit into a general first resource configuration module for providing a test channel resource corresponding to a test task and a corresponding circuit component, and a special resource assembly module for assembling a test circuit corresponding to the test task based on the test channel resource and the circuit component provided by the first resource configuration module. In this way, the special components can be reduced, the general components can be compatible and reused during wafer testing, and the cost can be reduced.

The invention provides a temperature control assembly for a probe card and the probe card, and relates to the field of wafer testing. The temperature control assembly for the probe card comprises a cover plate; the heating assembly is arranged on the side, away from the probe card, of the cover plate, and the heating assembly is electrically connected with the testing machine table; the heating buffer assembly is arranged on one side, close to the probe card, of the cover plate; the heat preservation assembly is arranged on the side, close to the probe card, of the cover plate, and the heat preservation assembly is an assembly with a closed pattern and is distributed on the outer side of the probe card; wherein the cover plate, the heat preservation assembly and the probe card form a heat receiving space, and the orthographic projection of the heating assembly on the cover plate is within the orthographic projection of the heating buffer assembly and the heat preservation assembly on the cover plate. According to the embodiment of the invention, the probe mark offset caused by temperature difference generated by heating of the probe card in the test process can be avoided, so that the test efficiency can be improved.

The invention relates to wafer test equipment, which comprises an electric test assembly, which is arranged on a mounting rack and comprises a telescopic member, a fixed end of the telescopic member is provided with a probe disc, the probe disc is provided with a plurality of probes corresponding to electrode pads of a wafer chip to be tested one by one, the probe disc is provided with a plurality of through holes between the probes, and the through holes are communicated with the probe disc. The telescopic end of the telescopic piece is provided with a suction cup, the suction cup is located below the probe disc, and the suction cup is provided with a plurality of suction rods extending into the through holes; and a light testing assembly. According to the wafer test equipment, the to-be-tested wafer is fixed on the suction rod after the angle and the position of the to-be-tested wafer are adjusted, and then the suction cup is driven to move downwards, so that the probes on the probe disc can be in contact with the metal bonding pads of the chips on the to-be-tested wafer, and electrical performance tests can be simultaneously carried out on all the chips on the wafer through the plurality of probes; and the optical fiber array disc is moved to be positioned on the wafer, so that all chips can be subjected to optical testing at one time, and the testing efficiency of the wafer is greatly improved.

The embodiment of the invention provides a power device test method and device, electronic equipment and a storage medium, and the method comprises the steps: sequentially applying a plurality of gradually increased voltages to a wafer for forming a power device in a wafer test stage, and obtaining the leakage current values of the wafer under the plurality of voltages; determining a wafer meeting a preset first test condition according to the leakage current values of the wafer under the plurality of voltages; in the static parameter test stage, sequentially applying a plurality of gradually increased voltages to the power device, and obtaining leakage current values of the power device under the plurality of voltages; the power device is obtained by packaging a wafer meeting a preset first test condition; and determining the power device meeting a preset second test condition according to the leakage current values of the power device under the plurality of voltages. Through preliminary testing in the wafer stage, wafers with defects can be effectively identified, the failure rate of a final product is reduced, retesting is carried out in the static parameter testing stage, and the quality of a power device is ensured.

The utility model relates to an anti-ink-splashing wafer dotting device, which belongs to the technical field of semiconductor wafer testing and comprises a basic support, an adjustable support, a fixed support, a coil, a funnel, a connecting rod, a spring, an ink guide wire, a limit screw I and a limit screw II. The spring is axially and fixedly connected below the connecting rod, the coil is axially and fixedly connected below the spring, the funnel is axially arranged below the coil, and the ink guide wire is arranged below the funnel. An ink fixing pipe is arranged in the funnel, the position for fixing the ink fixing pipe is higher than the upper edge of the funnel, the slender ink fixing pipe can ensure that the ink guide wire does not generate large deformation bending and ink splashing when moving up and down in the coil and the connecting rod, and the inner wall of the part, extending into the funnel, of the ink fixing pipe is provided with a round hole, so that the ink in the funnel is not blocked. The ink fixing pipe prevents ink on the ink guide wire from splashing to the surface of the wafer, and the ink on the ink guide wire falls into the ink fixing pipe when splashing, so that the ink cannot be splashed to the surface of the wafer to contaminate the surface of the wafer, and the product quality and the production efficiency are improved.

The application provides a memory operation method and a memory chip. The method comprises the following steps: obtaining an operation depth; wherein the operation depth is determined in wafer testing and stored in a storage unit; the operation depth represents a threshold voltage change level of the storage unit after operation; when the operation is performed, the operation depth is used for depth checking until the operation depth is reached. The application can accurately test the operation depth of the memory chip, and then guide the actual operation by using the operation depth, so as to achieve the purpose of accurately controlling the operation effect, and the problem that the threshold voltage of the storage unit becomes complex and uncontrollable can be avoided.

The application belongs to the chip testing technical field, and particularly relates to a semiconductor chip testing method, testing equipment and testing system. The testing method applied to finished product testing equipment comprises the following steps: in the case of performing finished product testing on the i-th semiconductor chip in the m-th detection batch, comparing and analyzing the i-th chip identification of the i-th semiconductor chip with the detected chip identification of the detected chip to obtain an analysis result; if the analysis result shows that the i-th chip identification does not exist in the detected chip identification, determining the matching result between the i-th chip identification and the wafer test file corresponding to the m-th detection batch uploaded by the wafer test equipment; determining whether to write the i-th chip identification into the finished product test file based on the matching result; and determining the finished product test result of the m-th detection batch based on the number of chip identifications in the finished product test file and the number of semiconductor chips in the m-th detection batch.

The invention relates to the technical field of power semiconductor wafer testing, and discloses a power semiconductor wafer electrical parameter testing system and method, and the system comprises a dynamic testing device which is electrically connected with a wafer bearing device, a static testing device which is electrically connected with the wafer bearing device, and a wafer bearing device which is electrically connected with a switching device. The wafer bearing device is electrically connected with the static testing device, the dynamic testing device is electrically connected with the wafer bearing device, the switching device is electrically connected with the static testing device and the dynamic testing device, and the control device is electrically connected with the switching device and used for controlling the switching device to conduct the wafer bearing device and the dynamic testing device or conduct the wafer bearing device and the static testing device. Two types of tests can be completed by only using one test needle seat, and the two types of tests can be completed through one-time needle pressing, so that the damage to the wafer is reduced.

The invention discloses a wafer testing machine and a storage container for the wafer testing machine. The wafer testing machine comprises a chuck, a probe card, a storage container and a carrying device. And the probe card is arranged above the chuck relative to the chuck. The storage container comprises a plurality of drawers which are used for bearing test samples or auxiliary devices. And the carrying device is used for carrying the test sample or the auxiliary device among the chuck, the storage container and the wafer bearing box. According to the wafer testing machine, the overall testing time can be shortened.

The embodiment of the invention provides a wafer test method, test equipment and a storage medium. The method comprises the following steps: setting an initial probe pressure of a probe card of the test equipment in a wafer test process; performing a contact resistance test on the wafer through the probe card based on the initial probe pressure; if the wafer does not pass the contact resistance test, performing contact resistance retest on the wafer; if the wafer passes the contact resistance test or passes the contact resistance retest, performing an electrical function test on the wafer; and if the wafer passes the electrical function test, carrying out a next-stage test on the wafer. According to the embodiment of the invention, by setting the initial probe pressure of the probe card, good contact between the probe card and the crystal grain in the first test process of the wafer is ensured, the accuracy of a wafer test result is improved, and the test efficiency of the wafer is further improved.

The application discloses a chip performance parameter automatic extraction method and system based on chip geometric coordinate mapping, a storage medium and electronic equipment, and belongs to the technical field of semiconductor testing. The application establishes a unified physical coordinate system, and performs coincidence comparison between layout definition data containing a chip identifier ChipID, design starting coordinates and physical dimensions of the ChipID, and pixel-level test original data containing physical performance indexes. For each ChipID, the geometric center point coordinates are calculated according to the starting coordinates and the physical dimensions, the center point coordinates are mapped back to the grid index of the test data, the chip performance parameters at the corresponding positions are automatically extracted, and finally the extracted performance parameters are associated with the ChipID to generate a chip-level performance parameter report. The application solves the problems that test data and chip positions are difficult to accurately associate and manual extraction is low in efficiency in the prior art, realizes automatic conversion of test data from 'pixel level' to 'chip level', has the advantages of high precision, high automation degree, strong scalability and the like, and can be widely applied to the field of semiconductor wafer testing.

The present application relates to the technical field of wafer testing. Provided are a wafer test data processing method and apparatus, and an electronic device and a medium. The method comprises: acquiring a test sequence consisting of test data of a plurality of dies on a target wafer; dividing the plurality of pieces of test data in the test sequence, so as to obtain a plurality of sub-sequences; converting the test data in the sub-sequences, so as to obtain target sub-sequences; and for the target sub-sequences that meet a deletion condition, deleting same in corresponding processing threads. In the present application, the problem of memory overflow in a conventional CS architecture when processing large-scale wafer test data is effectively solved by means of a BS architecture and a memory optimization technique; the processing efficiency and response speed of a system are improved by means of techniques such as data chunking, stream processing and asynchronous generation; and the stability and reliability of a system are enhanced by means of optimizing memory usage and data processing flows.

The invention provides a semiconductor device with a test element group and a test method of the semiconductor device. The test element group is arranged in a scribing groove in a substrate; n chips adjacent to the test element group share the test element group, and N is greater than or equal to 2; a test circuit is arranged in the test element group, and the test circuit comprises a phase decoder. According to the invention, a plurality of chip sharing test element groups based on phase identification can effectively distinguish sources or positions of a plurality of chips; and the test circuit selects a corresponding chip in the N chips according to the received phase signal, and tests the corresponding chip by using the test element group, and a dynamic identification and selection mechanism is adopted. The probe card is simplified, and the maintenance cost of the probe card is reduced. The number of test pads is reduced, wafer area waste is reduced, the test efficiency is improved, and the test circuit is automatically removed along with the cutting channel after the wafer is tested. The test circuit does not occupy the internal space of the chip, the test time is shortened, and interference and power consumption risks after packaging are reduced.

A wafer test cassette having a fluid inlet and a fluid outlet, includes a first housing, a second housing, a heat source, and an isolation device. The first housing includes a probe card including probes. The second housing is coupled to the first housing, so that a test space is defined. The second housing carries a wafer arranged in the test space, and the probes are electrical contact with an upper surface of the wafer. The heat source heats a lower surface of the wafer, and a high temperature region is defined between the lower surface and the second housing. The solation device surrounds the high temperature region for thermally isolating the high temperature region from the test space. The fluid inlet receives a gas, the gas flows between the probe card and the upper surface of the wafer, and exits through the fluid outlet.

The embodiment of the invention provides a wafer test board and a wafer test method, and belongs to the technical field of wafer test. The wafer test board comprises an SOC chip, a sampling circuit and a probe connector which are all integrated on a PCB substrate. A first connecting pin of the universal SOC chip is connected with a first connecting end of the probe connector, and two ends of the sampling circuit are respectively connected with a sampling pin of the universal SOC chip and a second connecting end of the probe connector; the distance between the universal SOC chip and the probe connector is greater than 5cm; the clock frequency of the universal SOC chip is configured to be a clock configuration frequency lower than 100 MHz; and the universal SOC chip is used for determining qualified bare chips from the wafers to be tested according to read-write test results obtained by performing read-write tests on the bare chips and electrical sampling data obtained by performing electrical sampling on the bare chips through the sampling circuit. According to the embodiment of the invention, the test cost can be reduced on the premise of considering the wafer test reliability.