Manufacturing process of transient voltage suppression diode chip

Abstract

The invention discloses a manufacturing process of a transient voltage suppression diode chip. The manufacturing process of the transient voltage suppression diode chip includes two production processes: a diffusion process and a GPP process. The steps of the diffusion process include original silicon wafer testing, original silicon wafer washing, phosphorus attachment, phosphorus diffusion, phosphorus wafer separation, single side sand blasting, single blasting washing, boron coating, boron diffusion, boron wafer separation, boron side sand blasting, and boron blasting washing, wherein the step of boron diffusion comprises primary boron diffusion and secondary boron diffusion; and the steps of the GPP process sequentially include oxidation, primary photoetching, groove etching, photoresist sintering, groove washing, SIPOS passive film formation, glassivation, secondary photoetching, surface etching, and nickel-gold plating. The manufacturing process of the transient voltage suppression diode chip in the invention reduces defects of the chip, enables voltage distribution to be relatively concentrated, and reduces reverse leakage current at the same time.

Description

technical field [0001] The invention relates to the manufacturing field of a semiconductor device, in particular to a manufacturing process of a transient voltage suppression diode chip. Background technique [0002] Today's transient voltage suppression diode chip manufacturing process is divided into diffusion process and GPP process. [0003] The diffusion process steps are: original silicon wafer test → original silicon wafer cleaning → phosphorus addition → phosphorus diffusion → phosphorus crystal separation → single-side sand blasting → single blowing cleaning → boron coating → boron diffusion → boron crystal separation → boron blowing → boron blowing cleaning . Among them, the boron-coated silicon wafer is only subjected to boron diffusion once, and the process is as follows: push the silicon wafer into a diffusion furnace at 500°C, control the temperature of the diffusion furnace to rise to 1262°C at a rate of 5°C / min, and keep the temperature at 1262°C for 10 hour...

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Problems solved by technology

[0005] like figure 1 As shown, the first layer of the PN junction interface of the P (boron) region 33 is the glass passivation layer 44. There is still a relatively high concentration of interface states at the interface between silicon and glass, and there are microbubbles in the glass on the interface, which makes the device work. Increased reverse leakage current

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