372 results about "Decoupling capacitor" patented technology

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

Disclosed in the present invention is a packaging structure of a half-bridge power module. The packaging structure comprises an insulating and thermal conductive plate, a multi-layer circuit board, a plastic package body and a bridge arm switch. Further disclosed in the present invention is the use of a packaging structure of a half-bridge power module in an OBC power source converter, a DCDC isolated converter, a non-isolated power source converter, a cardiac arrest awakening apparatus, and a circuit module formed by means of combining multiple half bridges such as ANPC, TNPC and Heric. Further disclosed in the present invention is a manufacturing method for a packaging structure of a half-bridge power module. The method comprises: performing assembling; providing an overflow region; and synchronously performing filling and grinding to remove the overflow region. In the present invention, a minimum size and a low impedance are achieved by means of DBC, flexible pin leading-out and welding are realized by means of a PCB, the reliability, safety and heat dissipation of modules are supported by means of a plastic packaging body, and the extension of a temperature monitoring unit and a decoupling capacitor is supported.

A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent the first interposer such that the first surface of the decoupling capacitor is adjacent the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures may be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures may be stacked to form a multilayer structure.

The invention discloses an ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator. The ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator is composed of a transformer T1, a transformer T2, a transformer T3, a transformer T4, a head oscillator HR1, a head oscillator HR2, a head oscillator HR3, a head oscillator HR4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a plurality of decoupling capacitors Cecap. According to the voltage-controlled oscillator, noise is prevented from being converted into phase noise by means of second and third harmonic impedance broadening, inductance loss reduction, reduction of the sensitive time of the resonant cavity to the noise and the like, the phase noise generated by the voltage-controlled oscillator can be effectively reduced, and excellent noise performance is obtained.

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

The invention discloses an orthogonally stacked double-sided cooling power module and a preparation method thereof. The orthogonally stacked double-sided cooling power module comprises a decoupling capacitor, a copper-clad ceramic substrate, a power chip and a metal cushion block, the metal cushion blocks and the power chips are stacked and connected layer by layer in a metal cushion block-power chip-metal cushion block mode to form a series chipset, and the copper-clad ceramic substrate is connected with the two sides of the metal cushion blocks in the series chipset and is perpendicular to the power chips. According to the invention, through the cooperative effect of orthogonal stacking packaging and double-face cooling of the double copper cushion blocks, the electrical and thermal performance of the cooling power module is cooperatively optimized, the parasitic inductance of the power module is significantly reduced, the transient over-current supporting capability is significantly improved, and the packaging technology has good flexibility and is suitable for large-scale production. The method is suitable for power modules of different packaging types.

The invention discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, a middle layer and a decoupling capacitor, the chip layer is electrically connected with the substrate layer; the middle layer is located between the upper chip layer and the lower chip layer, and the upper connecting layer and the lower connecting layer are windowing type copper blocks, are externally connected with DC terminals and are used for connecting the upper substrate layer and the decoupling capacitor; and the decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity to be connected with the copper layers in the laminated layer and the substrate to form the middle layer, the inductance of the machine body is obviously reduced, the heat dissipation effect is improved, the machine body has obvious advantages in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of a power electronic system can be effectively improved.

Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.

The invention provides a decoupling capacitor adjusting method and device, a server and a readable storage medium, which are applied to the technical field of computers, and the method comprises the following steps: firstly, adjusting the power consumption of a load module to enable a voltage adjusting module to output a load current to the load module through a board-level power supply circuit; acquiring a spectrum curve, a maximum current value and a minimum current value of the load current, creating a load model of the load module based on the spectrum curve, the maximum current value and the minimum current value, creating a PDN model based on the load model, controlling the PDN model to operate and acquiring a load terminal voltage of the load model, according to the method, the load model is created on the basis of the PDN actual measurement parameters, it can be ensured that the characteristics shown by the load model are highly attached to the actual load change, the load model is high in credibility, the accuracy and success rate of adjusting the decoupling capacitor are higher, the design period of the PDN is shortened, and the design efficiency of the board-level power supply circuit is improved. And practical application requirements are met.

The invention relates to a semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitors. A backside power and ground distribution network is formed on a semiconductor wafer by providing a decoupling capacitor on a backside of a semiconductor substrate layer; selectively etching a TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact an integrated device connection feature; then forming a ground TSV conductor in the TSV opening, the ground TSV conductor providing a direct electrical connection between a first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer; and also forming a power TSV conductor that provides a direct electrical connection between a second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly electrically connected to the second capacitor plate, and where the ground TSV conductor is not directly electrically connected to the second integrated device connection feature. And wherein the power TSV conductor is not directly electrically connected to the first capacitor plate.

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND / OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

The utility model relates to a nitrogen making machine electromagnetic compatibility processing device, which comprises a device body, and the device body comprises a nitrogen making machine shell. The shielding box is provided with an accommodating chamber and comprises a shielding box body and a shielding box cover which are mutually occluded and sealed, and a conductive rubber strip is arranged between the contact surfaces of the shielding box body and the shielding box cover; the filtering assembly is arranged in the shielding box accommodating chamber and comprises a common mode inductor and a high-frequency decoupling capacitor; the common mode inductor is arranged in the shielding box, the interface assembly is exposed on the side wall of the shielding box, the interface assembly comprises an input interface and an output interface which are oppositely arranged, the input interface comprises an aviation socket, the output interface comprises a feed-through filter, the aviation socket is connected with the common mode inductor, and the common mode inductor is connected with the feed-through filter. According to the nitrogen making machine equipment, the anti-interference performance can be improved, and meanwhile, the external interference capability of the nitrogen making machine serving as a disturbance source is also reduced.

The invention discloses a packaging structure of a half-bridge power module. The packaging structure comprises an insulating heat-conducting plate, a multi-layer circuit board, a plastic packaging body and a bridge arm switch, on the other hand, the invention discloses application of the packaging structure of the half-bridge power module in a vehicle-mounted OBC power converter, a DCDC isolation converter, a non-isolation power converter, a cardiac arrest wake-up device and a circuit module formed by combining multiple half bridges such as ANPC, TNPC and Heric. The invention further discloses a manufacturing method of the packaging structure of the half-bridge power module. The manufacturing method comprises the steps of assembling, arranging the overflow area and synchronously filling and grinding to remove the overflow area. The minimum size and low impedance are achieved through the DBC, flexible pin outgoing and welding are achieved through the PCB, the reliability, safety and heat dissipation of the module are supported through the plastic package body, and the expansion temperature monitoring unit and the decoupling capacitor are supported.

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. One device involves: a circuital arrangement (200A) comprising an integrated circuit, IC, the IC comprising: a shunt switch (T1); a decoupling capacitance (Cd) connecting a source terminal of the switch to a first pin (P1) of the IC; wherein the circuital arrangement further comprises: a storage capacitance (Cs) disposed outside the IC and coupled to the first pin of the IC; a resonance-canceling inductance (L2) disposed outside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current, AC, -short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance (L_IC) inside the IC and a parasitic ground inductance (L_PCB) outside the IC with ii) a parallel arrangement of the decoupling capacitance (Cd) and a parasitic capacitance (Cp), the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement.

The invention belongs to the technical field of power electronics, and relates to a high-side-ratio non-isolated hybrid switched capacitor converter which is used for direct 48V-1V power conversion of a data center and comprises switching tubes S1 to S38, flying capacitors C1 to C15, inductors L1 to L8, an input end Vin, an output end Vout and a grounding end. The switch tubes S1-S6 and the flying capacitors C1-C3 form a 4: 1 switched capacitor buck converter part; the switch tubes S7-S38, the flying capacitors C4-C15 and the inductors L1-L8 form a voltage-adjustable multi-channel mixed buck converter; mixing of the pre-buck converter and the voltage-adjustable buck converter is achieved through the exchange bus, the advantages of the pre-buck converter and the voltage-adjustable buck converter can be well fused, the defects of the pre-buck converter and the voltage-adjustable buck converter can be overcome, a bus decoupling capacitor is not needed, and the number of switches can be reduced. According to the multi-channel mixed buck converter, a capacitance channel is added, the conduction loss of an inductance channel is reduced, ripples are reduced, the duty ratio is increased, and the voltage stress of a switching tube is reduced; the hybrid switched capacitor converter has the advantages of being large in transformation ratio, high in power density and small in device stress.

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of resonance-canceling inductors to counteract the capacitive reactance caused by parasitic capacitances and / or decoupling capacitors utilized in such systems. Solutions that incorporate series resistors to distribute the resonance across the frequency band of operation are also described. Additionally, devices that employ digitally tuned capacitors to shift the resonance frequency outside the operational band are presented.

The invention discloses a silicon carbide power module dynamic current sharing method and system, and the method comprises the steps: setting a basic layout of a multi-chip parallel silicon carbide power module, and extracting circuit parasitic parameters; setting working conditions of the silicon carbide power module, and setting bus voltage, load current and power chip switching speed; setting the maximum allowable voltage overshoot, and limiting the total capacitance value of the distributed decoupling capacitor bank according to the voltage overshoot; and according to the equivalent impedance of the parallel branches at the set switching speed after the distributed decoupling capacitor bank is added, the capacitance value of the distributed decoupling capacitor is adjusted, so that the equivalent impedance of each branch is the same. By integrating the distributed decoupling capacitors, the problem of non-uniform current distribution in the traditional parallel connection technology is solved, and the method has important theoretical and practical significance for improving the performance of a power electronic system.

One or more examples relate to methods and apparatuses for measuring a voltage node. An example method may include providing, between an input of a measurement circuit and a voltage node associated with a higher voltage domain than the measurement circuit, a circuit including decoupled capacitors, the decoupled capacitors including at least a first capacitor and a second capacitor; generating, by the measurement circuit, a first digital value representing a voltage level related to a voltage level at the voltage node at least partially responsive to performing a measurement process utilizing the circuit; and generating, by a processor, a second digital value representing the voltage level at the voltage node at least partially responsive to the first digital value and a scaling factor, the scaling factor representing a pre-specified relationship between the voltage level represented by the first digital value and the voltage level at the voltage node.

Package substrate with embedded capacitor package with a redistribution layer(s) (RDL(s)) for aligning capacitor terminals to die interconnects of a semiconductor die (“die”) in an integrated circuit (IC) package, and related IC packages and fabrication methods. The capacitor package can be embedded in a package substrate of an IC package, such as to provide a decoupling capacitance or filter for a die of the IC package. A RDL(s) is built on a substrate of a capacitor of the capacitor package such that RDL interconnects of the RDL(s) are coupled to capacitor terminals of the capacitor. The RDL(s) redistributes connections to the capacitor terminals of the capacitor, to a desired pattern and / or pitch to align the capacitor terminals with die interconnects of a die coupled to the package substrate of the IC package. This minimizes signal path length between the capacitor and die to minimize inductance in the capacitive loop.

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of a switch to remove a decoupling capacitor from an RF circuit on an integrated circuit (IC) pin where the storage cap is connected; or modifying the turn-on threshold of an electrostatic discharge protection device (ESD) on the IC pin with the storage cap present to reduce susceptibility to turning on the ESD with the RF signal; or de-Qing the analog and digital core capacitances to minimize their contribution to resonance; or a combination thereof.

The present invention discloses a method and system for optimizing the impedance of a digital system power distribution network, and relates to the technical field of power distribution networks. The method for optimizing the impedance of a digital system power distribution network matches a PDN decoupling solution set based on the parasitic parameters of the digital system power supply; uses the PDN decoupling solution set to decouple the mounted PCB and microsystem substrate of the digital system power supply, and determines the PDN decoupling solution with the best PDN decoupling effect as the benchmark PDN decoupling solution; matches the benchmark PDN decoupling solution to obtain an optimization solution set; uses the matched optimization solution set to optimize the benchmark PDN decoupling solution to obtain the optimal PDN decoupling solution. The PDN decoupling solution set and the optimization solution set obtained by matching take into account the parasitic parameters of the digital system power supply, the decoupling requirements of the mounted PCB and the microsystem substrate, and solves the contradiction between the limited internal space of the microsystem and the large demand for decoupling capacitors.

The invention relates to the technical field of wiring structures, and discloses a low-power-consumption communication circuit board wiring structure, which comprises a shell internally provided with a plurality of layers of circuit boards for protecting the whole device; the wiring structure is arranged on the multilayer circuit board and is used for providing enough electric energy; the control module is fixed on the multi-layer circuit board and is used for controlling the start and stop states of each functional module on the multi-layer circuit board; the differential signal wiring module is fixed on the multilayer circuit board and is used for transmitting high-frequency signals; and the decoupling capacitor module is fixed on the multilayer circuit board and is used for reducing power supply noise and stabilizing power supply voltage. By introducing a special coating made of a high-conductivity material into the multilayer circuit board wiring structure and integrating advanced signal adjustment and calibration functions in the differential signal wiring module, the loss in the electric energy transmission process is effectively reduced, and the integrity and anti-interference capability of signals are remarkably improved in high-frequency signal transmission.

The invention relates to the technical field of electromagnetic interference filtering, in particular to a control board card electromagnetic interference suppression method. According to the method, electromagnetic interference frequency and related parasitic parameters on a control board card are determined by analyzing electromagnetic interference generation and conduction mechanisms around the control board card on the LLC resonant converter, in Pspice simulation software, a sampling circuit is utilized to simulate circuit functions on a key loop, and influence of external electromagnetic interference on the key loop is analyzed, so that the LLC resonant converter is simulated. Based on the analyzed influence of electromagnetic interference on the control board card, the models of various devices on the filter circuit are determined, the designed filter circuit is added into a sampling circuit of the control board card, external electromagnetic interference is suppressed, a decoupling capacitor is added between a power supply of the control board card and the ground plane, internal resonance of the control board card is suppressed, and the control board card is controlled to be in a filtering state. The power density of the switching power supply system is improved, and the reliability of the control signal is ensured.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

The invention provides a chip, an arrangement method of a driving clock unit circuit on the chip, electronic equipment and the chip, and the chip comprises the driving clock unit circuit which is arranged on a first area of the chip. Wherein the driving clock unit circuit includes: an input port and an output port disposed at both ends of a first region; an active transistor disposed in a driving force core region located in an intermediate region of the first region; wherein the number and the arrangement mode of the effective transistors are determined according to the driving capability of the driving clock unit circuit; and the decoupling capacitor is used for filling a redundant region, in which the effective transistor does not exist, in the driving force core region.

The invention relates to a self-decoupling coil array for magnetic resonance imaging, which comprises resonance coils with detuning loops, the resonance coils are connected in series with decoupling capacitors, the two resonance coils are oppositely arranged at the positions where the decoupling capacitors are arranged so as to form decoupling units, and the multiple decoupling units are arranged in at least one direction. The decoupling units which are oppositely arranged at the position of the decoupling capacitor can enable one resonance coil to decouple the other resonance coil, and the decoupling units exist in the self-decoupling coil array in pairs, so that electric coupling does not occur in the whole self-decoupling coil array to realize self-decoupling. Compared with the prior art, the self-decoupling coil array for magnetic resonance imaging disclosed by the invention realizes decoupling between detuning resonance circuits by introducing additional electric coupling, so that the sensitivity is kept at a due level, and the imaging signal-to-noise ratio gain is more uniform.

The embodiment of the invention discloses a power amplifier circuit, a radio frequency chip and electronic equipment. The power amplifier circuit comprises at least two stages of cascaded power amplifiers, the low-frequency resonance network comprises a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a grounding end; the second capacitor is coupled between the first end of the power amplifier and the grounding end; the first inductor is coupled between the first capacitor and the second capacitor; the first capacitor comprises a decoupling capacitor.

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source / drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source / drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.