1042 results about "Decoupling capacitor" patented technology

A photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured by the same are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region in the pattern to add one or more decoupling capacitors. Once the region is identified, a feature located in the identified region is moved based on a design rule from a first position to a second position in the mask layout file to create a space in the identified region. The decoupling capacitors are placed in the space in the identified region.

In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her / himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit. The data link layer may be connected to one of the localized grids of the versatile power mesh which may have an increased density and / or wider strap width of a power / ground grid. Additional decoupling capacitance can be embedded in the lower layers of the semiconductor product and / or can be programmed from the configurable transistors fabric.

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.

A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.