229 results about "Decoupling capacitor" patented technology

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention discloses an orthogonally stacked double-sided cooling power module and a preparation method thereof. The orthogonally stacked double-sided cooling power module comprises a decoupling capacitor, a copper-clad ceramic substrate, a power chip and a metal cushion block, the metal cushion blocks and the power chips are stacked and connected layer by layer in a metal cushion block-power chip-metal cushion block mode to form a series chipset, and the copper-clad ceramic substrate is connected with the two sides of the metal cushion blocks in the series chipset and is perpendicular to the power chips. According to the invention, through the cooperative effect of orthogonal stacking packaging and double-face cooling of the double copper cushion blocks, the electrical and thermal performance of the cooling power module is cooperatively optimized, the parasitic inductance of the power module is significantly reduced, the transient over-current supporting capability is significantly improved, and the packaging technology has good flexibility and is suitable for large-scale production. The method is suitable for power modules of different packaging types.

The invention discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, a middle layer and a decoupling capacitor, the chip layer is electrically connected with the substrate layer; the middle layer is located between the upper chip layer and the lower chip layer, and the upper connecting layer and the lower connecting layer are windowing type copper blocks, are externally connected with DC terminals and are used for connecting the upper substrate layer and the decoupling capacitor; and the decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity to be connected with the copper layers in the laminated layer and the substrate to form the middle layer, the inductance of the machine body is obviously reduced, the heat dissipation effect is improved, the machine body has obvious advantages in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of a power electronic system can be effectively improved.

Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.

The invention relates to a semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitors. A backside power and ground distribution network is formed on a semiconductor wafer by providing a decoupling capacitor on a backside of a semiconductor substrate layer; selectively etching a TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact an integrated device connection feature; then forming a ground TSV conductor in the TSV opening, the ground TSV conductor providing a direct electrical connection between a first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer; and also forming a power TSV conductor that provides a direct electrical connection between a second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly electrically connected to the second capacitor plate, and where the ground TSV conductor is not directly electrically connected to the second integrated device connection feature. And wherein the power TSV conductor is not directly electrically connected to the first capacitor plate.

Package substrate with embedded capacitor package with a redistribution layer(s) (RDL(s)) for aligning capacitor terminals to die interconnects of a semiconductor die (“die”) in an integrated circuit (IC) package, and related IC packages and fabrication methods. The capacitor package can be embedded in a package substrate of an IC package, such as to provide a decoupling capacitance or filter for a die of the IC package. A RDL(s) is built on a substrate of a capacitor of the capacitor package such that RDL interconnects of the RDL(s) are coupled to capacitor terminals of the capacitor. The RDL(s) redistributes connections to the capacitor terminals of the capacitor, to a desired pattern and / or pitch to align the capacitor terminals with die interconnects of a die coupled to the package substrate of the IC package. This minimizes signal path length between the capacitor and die to minimize inductance in the capacitive loop.

The invention relates to the technical field of electromagnetic interference filtering, in particular to a control board card electromagnetic interference suppression method. According to the method, electromagnetic interference frequency and related parasitic parameters on a control board card are determined by analyzing electromagnetic interference generation and conduction mechanisms around the control board card on the LLC resonant converter, in Pspice simulation software, a sampling circuit is utilized to simulate circuit functions on a key loop, and influence of external electromagnetic interference on the key loop is analyzed, so that the LLC resonant converter is simulated. Based on the analyzed influence of electromagnetic interference on the control board card, the models of various devices on the filter circuit are determined, the designed filter circuit is added into a sampling circuit of the control board card, external electromagnetic interference is suppressed, a decoupling capacitor is added between a power supply of the control board card and the ground plane, internal resonance of the control board card is suppressed, and the control board card is controlled to be in a filtering state. The power density of the switching power supply system is improved, and the reliability of the control signal is ensured.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

The embodiment of the invention discloses a power amplifier circuit, a radio frequency chip and electronic equipment. The power amplifier circuit comprises at least two stages of cascaded power amplifiers, the low-frequency resonance network comprises a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a grounding end; the second capacitor is coupled between the first end of the power amplifier and the grounding end; the first inductor is coupled between the first capacitor and the second capacitor; the first capacitor comprises a decoupling capacitor.

The present invention belongs to the field of intelligent monitoring technology, specifically relating to a health monitoring system and its preparation method. The system comprises a health monitoring mask and a host computer. The health monitoring mask includes the mask and its built-in respiratory monitoring unit, heart rate monitoring unit, and health monitoring unit. The host computer includes a display interface and its built-in data processing module. The respiratory monitoring unit includes a thermoelectric device made of P-type and N-type semiconductor thermoelectric particles. The heart rate monitoring unit consists of a MAX30102 integrated on a flexible PCB, a voltage regulator circuit, a decoupling capacitor, and a pull-up resistor. The health monitoring unit is sewn into the mask and includes an ADC conversion unit I, a microcontroller chip with a built-in Bluetooth module and an integrated circuit bus. The host computer includes a display interface and a data processing module to receive monitoring data from the respiratory monitoring unit and the heart rate monitoring unit, match the data into groups, and perform multi-source fusion. Based on the multi-source fusion data, the health status of the human body can be identified and judged.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Semiconductor device packages including leads for enhanced video bandwidth and related operating criteria are described. An example package includes a flange having a top surface, a frame secured to the flange, and a pair of output leads. The frame forms an air cavity bounded in part by the top surface of the flange. The pair of output leads extend from outside the frame, through at least a portion of the frame, and to within the air cavity. The package also includes a decoupling lead positioned between the pair of output leads. The package also includes a second decoupling lead positioned between the pair of output leads in some examples. The decoupling lead or leads between the output leads facilitate the use of off-package decoupling capacitors to meet video bandwidth and other operating specifications. The package can also include one or more additional decoupling leads between input leads.

The utility model relates to a kind of temperature chip test circuit of supporting fast and slow power-on and fast reset, mainly including chip U1, chip U2, chip port P1 to be measured, the 15 pin of chip U2, 14 pin connect external IIC bus, the 4,5,6,7 pin of chip U2 are general I / O pin, respectively connect the 13,5,6,12 pin of chip U1, and there is also decoupling capacitor C2 on the 16 pin of chip U2, the 8 pin,11 pin of chip U1 is connected to GND by resistance R2 and capacitor C3 respectively, the 2,3,9,10 pin of chip U1 are all connected to the 1 pin of chip port P1 to be measured, and there is also decoupling capacitor C1 on the 14 pin of chip U1.The utility model circuit simple structure, cost is lower, can be easily integrated into original test circuit, under the premise of retaining original test project, increase the performance evaluation and screening of temperature chip under the mode of fast power-on and slow power-on, and have fast and thorough reset function.

This invention belongs to the field of wireless communication technology. It provides a differential amplifier system and a method for improving common-mode stability. The invention uses a large decoupling capacitor C1 at the transformer center tap to provide AC ground, and a common-mode resistor R1 to improve the circuit's common-mode stability. Since the common-mode resistor R1 is not in the differential signal loop path, the use of common-mode resistor technology does not affect differential-mode performance. Because the required common-mode resistor value is small, this design occupies a small layout area. This invention solves the problem of low common-mode stability in differential amplifiers.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

An amplifier device, such as a Doherty amplifier device, may include an extra lead and decoupling capacitor coupled to radio frequency (RF) cold points of output impedance matching circuitry of multiple amplification paths, such as a carrier path and peaking path, of the amplifier device. The extra lead and the decoupling capacitor are configured to provide low frequency resonance decoupling for the multiple amplification paths. A drain bias voltage may be provided to the drain terminals of transistors of amplifiers of the amplifier device via the extra lead. An integrated passive device (IPD) including a wire fence and one or more conductive pads may be disposed between a carrier amplifier die and a peaking amplifier. The extra lead may be coupled to the RF cold points via the IPD. The wire fence may mitigate RF interference between the carrier amplifier die and the peaking amplifier die.

The present invention relates to a circuitry system (1). The circuitry system (1) comprises a reservoir power rail (12), a regulated power rail (14), a logic circuitry (18) connected to the regulated power rail (14), wherein each of the reservoir power rail (12), regulated power rail (14) and logic circuitry (18) is connected to respective voltage supply source (16), characterized by a dynamic decoupling capacitor (10) connecting the reservoir power rail (12) to the regulated power rail (14), and in communication with the logic circuitry (18), wherein the dynamic decoupling capacitor (10) is configured to match a total-charge of injected-current, ldecap, from the reservoir power rail (12) with a total-charge of load-current, lload, supplying to the logic circuitry (18). A method for regulating voltage of the circuitry system (1) is also disclosed herein.

The utility model relates to a lithium battery charging and discharging management circuit with a protection function, which comprises a charging input filtering unit, a power adjusting unit, a battery protection unit, a feedback control unit, a logic switching unit and an output interface unit, and is characterized in that the charging input filtering unit suppresses input interference through a symmetrical inductor and a multistage decoupling capacitor; the power adjusting unit is used for converting the input energy into a target charging parameter; the battery protection unit works cooperatively with the protection chip through the back-to-back double MOSFET array, so that overvoltage / undervoltage quick turn-off is realized; the feedback control unit compares the voltage division sampling signal with an adjustable reference by using a dual-comparator network to generate a PWM closed-loop adjusting signal; and the logic switching unit constructs a logic AND circuit through a multi-channel MOSFET switch group, and responds to a protection signal to forcibly cut off a power path. And dynamic adjustment and multiple protection mechanisms are fused through modular design, so that the charging and discharging efficiency and the system safety are remarkably improved, and the method is suitable for a high-reliability lithium battery management system.

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

The invention belongs to the field of manufacturing of printed circuits and assemblies thereof, and discloses a low-inductance lamination assembly method of a pulse power module, which comprises the following steps: placing a power semiconductor device and a decoupling capacitor into a cavity of a core substrate in a coplanar manner; laminating insulating layers and selectively windowing by using a closed-loop control method based on plasma spectrum monitoring; and finally, a bridging conductive layer directly bridging the top terminal of the element is formed through metal deposition. According to the invention, a lamination step is multiplexed as a key electrical connection forming process, and the dimension of a traditional three-dimensional commutation loop is reduced to a quasi-two-dimensional plane on a topological structure; therefore, current path geometric abrupt change and inductance bottleneck caused by vertical via holes are broken, and a structural basis is established for improving the electrical performance and electromagnetic compatibility of the module.

A semiconductor device is provided. The semiconductor device comprises a first circuit and a capacitor circuit. The first circuit has an input terminal configured to receive an input signal. The capacitor circuit comprises a first transistor and a second transistor. The first transistor is coupled between a first supply voltage and the input terminal. Source / drain terminals of the first transistor are coupled to each other. The second transistor is stacked above the first transistor and coupled between a second supply voltage and the input terminal. Source / drain terminals of the second transistor are coupled to each other. The first and second transistors are decoupling capacitors of the first circuit.

Embodiments of the disclosure provide a semiconductor device. The semiconductor device includes a circuit and a first bitcell array. The circuit is coupled to a first power rail and a second power rail. The first bitcell array includes a first subarray having a plurality of first bitcells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first bitcells are configured as a decoupling capacitor between the first power rail and the second power rail.

A package having a capacitor structure and a method of forming the same are provided. The package includes a first die; a second die bonded onto the first die; an isolation region disposed on the first die and laterally encapsulating the second die; at least one first through-via disposed aside the second die and penetrating through the isolation region; an electrode layer disposed on the at least one first through-via; and a capacitor dielectric layer disposed between the at least one first through-via and the electrode layer to separate the at least one first through-via from the electrode layer, wherein the at least one first through-via, the capacitor dielectric layer, and the electrode layer constitute a capacitor structure.

The present invention provides a chip design method and a chip design system. The chip design method includes: reading a netlist; identifying multiple interfaces of a submodule in a chip based on the netlist; confirming the interface position of at least one designated interface among the multiple interfaces; determining the location of an interface unit based on the interface position of the at least one designated interface and a designated spacing; and determining the location of a decoupling capacitor based on the location of the interface unit. The chip design method and chip design system of the present invention can automatically and efficiently design the location of the interface unit and the decoupling capacitor in a chip.

The invention provides an image sensor. The image sensor comprises a plurality of pixel circuits arranged in an array; the pixel circuit comprises a photodiode, a floating diffusion part, a transmission transistor, a dual-conversion gain transistor, a reset transistor, a power supply voltage line and at least one decoupling capacitor, wherein the decoupling capacitor comprises a substrate; the N-type region is arranged on one side of the substrate, and the N-type region comprises an N-type source region and an N-type drain region; the N-type source electrode region and the N-type drain electrode region are respectively grounded; the gate insulating layer is arranged on one side, far away from the substrate, of the N-type region; the at least one vertical transmission grid electrode is arranged on one side, far away from the N-type region, of the grid electrode insulating layer; the vertical transmission grid comprises a top part and at least two vertical poles extending towards the N-type region; and the top of the vertical transmission grid of the decoupling capacitor is electrically connected with a power supply voltage line. The capacitance value of the decoupling capacitor can be improved, and row noise in a pixel circuit of the image sensor can be reduced.

The application discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, an intermediate layer and a decoupling capacitor; the chip layer is electrically connected with the substrate layer; the intermediate layer is located between the upper chip layer and the lower chip layer; the upper connecting layer and the lower connecting layer are windowed copper blocks, and are externally connected with DC terminals and used for connecting the upper substrate layer and the decoupling capacitor; the decoupling capacitor is two groups of capacitors arranged on the side of the intermediate layer and electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity, the intermediate layer is connected with the copper layer in the laminated layer and the substrate, the body inductance is obviously reduced, the heat dissipation effect is improved, obvious advantages are obtained in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of the power electronic system can be effectively improved.

The invention belongs to the technical field of automotive electronics, and relates to a high-anti-interference controller PCB layout structure for an electric power steering system, a PCB is a multilayer board, and the PCB layout structure is characterized in that a power ground loop of a high-frequency switching circuit is directly connected to a grounding end of a common mode inductor to realize single-point discharge of high-frequency noise; the analog signal circuit is far away from the high-frequency digital signal circuit in layout; the MCU power supply decoupling capacitors are arranged around the MCU in a distributed star network; the PCB layout structure is provided with a power ground plane and a signal ground plane which are completely isolated, and the power ground plane and the signal ground plane are connected only through a single common mode inductor; in the PCB layout structure, a driving signal, a feedback signal, a sampling signal and a power signal of the inverter bridge part are respectively arranged in different PCB layers; the current sampling precision and the system reliability are remarkably improved, the steering hand feeling is improved, the electromagnetic compatibility is excellent, and the engineering application value is very high.

An integrated circuit (IC) includes one or more testable voltage decoupling (DCAP) cells. Each of the testable DCAP cells includes (i) one or more decoupling capacitors connected between supply rails of the IC, and (ii) a decoupling-test active logic (DTAL) circuit, which has a normal input-output response and is configured to deviate from the normal input-output response in response to a fault in the DCAP cell.

The invention relates to a circuit system (1). The circuit system (1) comprises an energy storage power supply rail (12), a regulated power supply rail (14), a logic circuit (18) connected to the regulated power supply rail (14), where each of the energy storage power supply rail (12), the regulated power supply rail (14) and the logic circuit (18) is connected to a common ground (16), where a dynamic decoupling capacitor (10) connects the energy storage power supply rail (12) to the regulated power supply rail (14) and communicates with the logic circuit (18), wherein the dynamic decoupling capacitor (10) is configured to match the total charge of the injection current Idecap from the energy storage supply rail (12) with the total charge of the load current Iload provided to the logic circuit (18). A method of regulating a voltage by a regulating circuitry (1) is encompassed herein.

This utility model relates to the field of circuit technology and discloses a dual 85 test circuit for an AC-DC power supply chip. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (with a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. This utility model overcomes the shortcomings of THB testing and whole-machine dual 85 testing, achieving the advantage of performing dual 85 testing under simulated actual operating conditions (PWM operation state) while increasing the number of tests to 77 PCS.