28 results about "Decoupling capacitor" patented technology

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

Embodiments of the disclosure provide a semiconductor device. The semiconductor device includes a circuit and a first bitcell array. The circuit is coupled to a first power rail and a second power rail. The first bitcell array includes a first subarray having a plurality of first bitcells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first bitcells are configured as a decoupling capacitor between the first power rail and the second power rail.

This utility model relates to the field of circuit technology and discloses a dual 85 test circuit for an AC-DC power supply chip. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (with a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. This utility model overcomes the shortcomings of THB testing and whole-machine dual 85 testing, achieving the advantage of performing dual 85 testing under simulated actual operating conditions (PWM operation state) while increasing the number of tests to 77 PCS.

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces, and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures can be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures can be stacked to form a multilayer structure.

The present disclosure provides a capacitor configuration method, device and equipment of a power distribution network and a storage medium. The method establishes an equivalent circuit model of a power distribution network without adding on-board decoupling capacitors, and then determines a target capacitor circuit corresponding to the equivalent circuit model based on solving constraint conditions and an objective function. The objective function is established based on the demand for on-board decoupling capacitor cost to optimize the number of decoupling capacitors and avoid over-design of on-board decoupling capacitors, thereby wasting costs. The constraint condition is established based on the impedance of the on-board decoupling capacitor to meet the electrical performance requirement, so as to ensure that the saved capacitor cost can still meet the actual impedance requirement. The impedance simulation of the equivalent circuit model with the target capacitor circuit is further verified to determine whether the target capacitor circuit meets the requirement, so as to ensure that the final target power distribution network can achieve ideal decoupling effect without over-design.

This invention relates to the field of artificial power network technology, specifically to a high-voltage artificial power network system and equipment. It includes a DC decoupling network module integrating decoupling capacitors and discharge resistors for power protection; and a DC load network module electrically interconnected with the DC decoupling network module via cables, integrating a multi-stage resistor array, a heat exchanger system, control components, and a cooling subsystem. The cooling subsystem is configured for water-air heat exchange or water-water heat exchange based on the current output stage of the multi-stage resistor array. This invention features efficient heat dissipation and precise temperature control, real-time closed-loop temperature monitoring, and over-temperature alarms for safety. It can promptly observe localized temperature rises and water levels caused by poor cable contact. Connecting to a host computer via a communication module allows for real-time monitoring by the host computer software, and interlocking protection is implemented with the power supply equipment and the tested equipment, simplifying maintenance.

This invention relates to a method for optimizing the placement of bridging capacitors to improve signal quality across split regions on a PCB board. The method includes the following steps: establishing a bridging capacitor simulation model for signal lines crossing a split region of a reference plane; setting the bridging capacitor simulation model to a movable state, using the distance between the bridging capacitor and the signal line as a scanning variable; performing a step-by-step scan within a preset distance range to obtain signal quality parameters at different distances; determining the maximum effective compensation distance of the bridging capacitor relative to the signal line based on the scan results and a preset judgment criterion; and determining the number of bridging capacitors and their placement positions based on the maximum effective compensation distance and the actual width of the cross-segment signal region to be compensated. This invention quantifies the impact of capacitor placement distance on signal quality, scientifically determines the maximum effective compensation distance of the bridging capacitors, and enables reasonable planning of the number and placement of capacitors, balancing wiring density and cost while ensuring signal quality.

The application discloses a kind of three-port converter energy balance control method based on power distribution of pulse frequency sudden drop, in the case where load frequency suddenly drops, the power distribution mode of AC / DC converter is switched, and the fastest change rate that AC / DC converter can provide is controlled to control input source power linearly decreases and linearly increases, after a short adjustment time, energy storage capacitor charging and discharging can be balanced, then the system enters new steady state.Compared with load frequency sudden increase, when three-phase alternating current source input power is too small, pulse load frequency sudden drop is limited by the power distribution mode of AC / DC converter, and it can make pulse load voltage fluctuate, so that the dynamic recovery time of decoupling capacitor voltage is too long, and the original power distribution mode cannot meet the demand of pulse load, so the power distribution mode of AC / DC converter needs to be switched.The problem that the dynamic performance of existing pulse power compensation control method is not optimal after load pulse frequency suddenly drops is solved.

A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

An integrated circuit includes a first decoupling capacitor cell having a first discharge path and a second decoupling capacitor cell having a second discharge path, where the first discharge path is formed at an external region of the first decoupling capacitor cell, and the second discharge path is formed at an internal region of the second decoupling capacitor cell.

A wafer-scale silicon substrate incorporates vertically integrated power delivery through conductive pillars and multiple isolated power domains. The substrate includes through-silicon vias, redistribution wiring layers, and lithographically defined power and ground planes and decoupling capacitors. Semiconductor stacks are bonded to an upper surface while power modules are attached to an underside, delivering regulated current through the pillars directly into each domain. Redundant power channels, isolation trenches, and domain-specific regulators enable high-current wafer-scale operation without organic interposers, providing uniform electrical and thermal balance across the all-silicon computational domain.

This invention discloses a multi-chip parallel orthogonal current sharing module and its fabrication method. The module provides a first chip layer where the lower power semiconductor devices are arranged in a planar symmetrical layout, and the vertical positions of each lower power semiconductor device correspond to the corresponding upper power semiconductor device. Due to the vertical position correspondence combined with the planar symmetrical layout, the inductance of each path within the first and second chip layers is consistent, thus easily achieving a better current sharing effect. Furthermore, the metal pads connected to the lower part of the decoupling capacitor, which are set in the copper plate holes at the AC end, are arranged parallel to each lower metal pad. This allows the decoupling capacitor to have reverse mutual inductance with each lower power semiconductor device. The upper metal pads of the capacitor are also arranged parallel to the upper metal pads of the capacitor, thereby achieving reverse mutual inductance between the decoupling capacitor and each upper power semiconductor device. This, in turn, cancels out the vertical path mutual inductance, achieving the goal of reducing parasitic inductance.

A fully differential power amplifier has an input matching network, a plurality of stacked transistors connected by a plurality of inter stack networks (ISNs), and an output matching network for amplification and conditioning of signal components. The differential amplifier uses a modified cascode FET topology with the FETs connected by gate decoupling capacitors to strongly attenuate common mode oscillations and eliminate the need for a source degeneration inductor or matching transformer. Inter stack networks provide signal conditioning and filtering between amplification stages to improve amplifier performance metrics such as long-term reliability, output power, and efficiency.

A mechanism for facilitating quasi-square wave control of a totem pole power factor correction system that makes use of rectifying diodes in the rectifying system and comprises a synchronous boost PFC converter. The mechanism comprises a boost input decoupler, formed of a pair of clamping diodes and decoupling capacitors, that decouples the input of the synchronous boost PFC converter from an input interface (which receives an AC input signal for conversion).

An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

A cell region of a semiconductor device includes: substrates, each of which including: substantially uniformly sized clock gate blocks each of which including a clock gate; and substantially uniformly sized decap blocks each of which including a decoupling capacitor. For each substrate, at least one of a condition (A) or a condition (B) is true. The condition (A) includes each row has a first odd-even or a first even-odd intra-row arrangement of the clock gate blocks and the decap blocks, the rows are interleaved with respect to the first odd-even and even-odd intra-row arrangements; and row-wise arrangements of the substrates are different. The condition (B) includes each column has a second odd-even or a second even-odd intra-column arrangement of the clock gate blocks or the decap blocks, the columns are interleaved with respect to the second odd-even and even-odd intra-column arrangements; and column-wise arrangements of the substrates are different.

The present disclosure provides a semiconductor die with decoupling capacitors. The semiconductor die includes a plurality of first bonding pads, a plurality of second bonding pads, a plurality of bonding metals, and a plurality of decoupling capacitors. The plurality of first and second bonding pads are coupled to a power supply voltage and a reference voltage, respectively. The plurality of bonding metals are disposed on a plurality of central regions of the plurality of first and second bonding pads. The plurality of decoupling capacitors are disposed under the plurality of first and second bonding pads and overlap a plurality of peripheral regions of the plurality of first and second bonding pads. The plurality of decoupling capacitors are connected in parallel. First endpoints of the plurality of decoupling capacitors are electrically connected to the plurality of first bonding pads, and second endpoints of the plurality of decoupling capacitors are electrically connected to the plurality of second bonding pads.

The present invention relates to a self-decoupling coil array for magnetic resonance imaging, comprising resonant coils each having a detuning loop, wherein decoupling capacitors are connected in series to the resonant coils; at the positions where the decoupling capacitors are arranged, the two resonant coils are oppositely arranged to form decoupling units, and a plurality of decoupling units are arranged in at least one direction. The decoupling units oppositely arranged at the positions of the decoupling capacitors enable one resonant coil to be decoupled from the other resonant coil, and the decoupling units are present in pairs in the self-decoupling coil array, thereby preventing electrical coupling throughout the entire self‑decoupling coil array and thus achieving self‑decoupling. Compared with the prior art, the self-decoupling coil array for magnetic resonance imaging disclosed in the present application achieves decoupling between detuned resonant circuits by introducing additional electrical coupling, so that the sensitivity remains at an appropriate level and the imaging signal-to-noise ratio gain becomes more uniform.

This application discloses a power converter, a control method, and related devices. The power converter includes a controller, a DC / DC circuit, a decoupling capacitor, and a three-phase power conversion circuit. Each phase of the three-phase power conversion circuit includes a four-switch Buck-Boost circuit. The DC side of the three-phase power conversion circuit is connected to a DC source, and the AC side is connected to a load in a star configuration. The first and second terminals of the DC / DC circuit are connected to the positive terminal of the DC source and the neutral point of the load, respectively. The third terminal of the DC / DC circuit is used to connect to the negative terminal of the DC source. The first terminal of the decoupling capacitor is connected to the second output terminal of the DC / DC circuit, and the second terminal of the decoupling capacitor is connected to the negative terminal of the DC source. The controller controls the output voltage of the DC / DC circuit so that the second harmonic power on the decoupling capacitor has the same amplitude but opposite phase to the second harmonic power on the AC side of the power converter, thereby suppressing the second harmonic power of the output power.

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

An integrated circuit is disclosed. The integrated circuit includes: a first decoupling capacitor cell having a first discharge path; and a second decoupling capacitor cell having a second discharge path, wherein the first discharge path is formed in an external region of the first decoupling capacitor cell, and the second discharge path is formed in an internal region of the second decoupling capacitor cell.

The present disclosure relates to semiconductor structures and, more particularly, to low leakage decoupling capacitor structures and methods of manufacture. The structure includes: a first gate structure comprising a gate dielectric region with a first thickness; and a second gate structure adjacent to the first gate structure, the second gate structure comprising a gate dielectric region with a second thickness different from the gate dielectric region with the first thickness.

This invention discloses a parasitic cancellation gain unit and a distributed amplifier, belonging to the field of amplifier technology. The parasitic cancellation gain unit is a parasitic cancellation common-source cascode gain unit, comprising two groups of small transistors and multiple parallel embedded capacitors. Each group of small transistors includes four small transistors connected in parallel, and the two groups of small transistors respectively replace a single large transistor in the common-source and common-gate stages. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitors and decoupling capacitors of the common-source cascode gain unit to cancel the influence of parasitic inductance generated by the traces. A distributed amplifier is composed of multiple stages of the above-mentioned parasitic cancellation gain units and input / output transmission lines. This invention solves the problems of limited bandwidth, significant parasitic effects, and large size of distributed amplifiers under traditional bulk CMOS technology.