77 results about "Decoupling capacitor" patented technology

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

This invention belongs to the field of wireless communication technology. It provides a differential amplifier system and a method for improving common-mode stability. The invention uses a large decoupling capacitor C1 at the transformer center tap to provide AC ground, and a common-mode resistor R1 to improve the circuit's common-mode stability. Since the common-mode resistor R1 is not in the differential signal loop path, the use of common-mode resistor technology does not affect differential-mode performance. Because the required common-mode resistor value is small, this design occupies a small layout area. This invention solves the problem of low common-mode stability in differential amplifiers.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

An amplifier device, such as a Doherty amplifier device, may include an extra lead and decoupling capacitor coupled to radio frequency (RF) cold points of output impedance matching circuitry of multiple amplification paths, such as a carrier path and peaking path, of the amplifier device. The extra lead and the decoupling capacitor are configured to provide low frequency resonance decoupling for the multiple amplification paths. A drain bias voltage may be provided to the drain terminals of transistors of amplifiers of the amplifier device via the extra lead. An integrated passive device (IPD) including a wire fence and one or more conductive pads may be disposed between a carrier amplifier die and a peaking amplifier. The extra lead may be coupled to the RF cold points via the IPD. The wire fence may mitigate RF interference between the carrier amplifier die and the peaking amplifier die.

The utility model relates to a lithium battery charging and discharging management circuit with a protection function, which comprises a charging input filtering unit, a power adjusting unit, a battery protection unit, a feedback control unit, a logic switching unit and an output interface unit, and is characterized in that the charging input filtering unit suppresses input interference through a symmetrical inductor and a multistage decoupling capacitor; the power adjusting unit is used for converting the input energy into a target charging parameter; the battery protection unit works cooperatively with the protection chip through the back-to-back double MOSFET array, so that overvoltage / undervoltage quick turn-off is realized; the feedback control unit compares the voltage division sampling signal with an adjustable reference by using a dual-comparator network to generate a PWM closed-loop adjusting signal; and the logic switching unit constructs a logic AND circuit through a multi-channel MOSFET switch group, and responds to a protection signal to forcibly cut off a power path. And dynamic adjustment and multiple protection mechanisms are fused through modular design, so that the charging and discharging efficiency and the system safety are remarkably improved, and the method is suitable for a high-reliability lithium battery management system.

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

A semiconductor device is provided. The semiconductor device comprises a first circuit and a capacitor circuit. The first circuit has an input terminal configured to receive an input signal. The capacitor circuit comprises a first transistor and a second transistor. The first transistor is coupled between a first supply voltage and the input terminal. Source / drain terminals of the first transistor are coupled to each other. The second transistor is stacked above the first transistor and coupled between a second supply voltage and the input terminal. Source / drain terminals of the second transistor are coupled to each other. The first and second transistors are decoupling capacitors of the first circuit.

Embodiments of the disclosure provide a semiconductor device. The semiconductor device includes a circuit and a first bitcell array. The circuit is coupled to a first power rail and a second power rail. The first bitcell array includes a first subarray having a plurality of first bitcells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first bitcells are configured as a decoupling capacitor between the first power rail and the second power rail.

The invention belongs to the technical field of automotive electronics, and relates to a high-anti-interference controller PCB layout structure for an electric power steering system, a PCB is a multilayer board, and the PCB layout structure is characterized in that a power ground loop of a high-frequency switching circuit is directly connected to a grounding end of a common mode inductor to realize single-point discharge of high-frequency noise; the analog signal circuit is far away from the high-frequency digital signal circuit in layout; the MCU power supply decoupling capacitors are arranged around the MCU in a distributed star network; the PCB layout structure is provided with a power ground plane and a signal ground plane which are completely isolated, and the power ground plane and the signal ground plane are connected only through a single common mode inductor; in the PCB layout structure, a driving signal, a feedback signal, a sampling signal and a power signal of the inverter bridge part are respectively arranged in different PCB layers; the current sampling precision and the system reliability are remarkably improved, the steering hand feeling is improved, the electromagnetic compatibility is excellent, and the engineering application value is very high.

This utility model relates to the field of circuit technology and discloses a dual 85 test circuit for an AC-DC power supply chip. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (with a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. This utility model overcomes the shortcomings of THB testing and whole-machine dual 85 testing, achieving the advantage of performing dual 85 testing under simulated actual operating conditions (PWM operation state) while increasing the number of tests to 77 PCS.

The application discloses a power distribution network decoupling capacitor arrangement optimization method based on an improved genetic algorithm. First, the ports of the power distribution network are prioritized to obtain port ordering subcolumns corresponding to various capacitors; then, according to the port ordering subcolumns corresponding to various capacitors, optimal capacitors and corresponding ports for placement are selected from a capacitor library in sequence until the observation impedance is less than the target impedance at all frequency points, and an initial decoupling capacitor arrangement is obtained; finally, after the initial decoupling capacitor arrangement is iteratively optimized by using the improved genetic algorithm, an optimal decoupling capacitor arrangement is obtained. The method has high search efficiency, fast convergence speed and good robustness, the genetic algorithm is modified according to the capacitor combination optimization application scene, and the optimal capacitor configuration meeting the target impedance can be efficiently found.

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces, and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures can be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures can be stacked to form a multilayer structure.

A semiconductor chip device includes a substrate with a first dielectric material of a first permittivity value. A power input line and ground line are positioned in the substrate and arranged to form a decoupling capacitor. A region of the substrate in between the power input line and the ground line is doped with a second dielectric material of a second permittivity value that is higher than the first permittivity value. The region doped with the second dielectric material lacks a signal body. By incorporating a region with higher permittivity, in what is generally unused space for power delivery, the region becomes a decoupling capacitor for nearby power delivery elements. By adding decoupling capacitance to the previously unused space, noise in a circuit is more easily controlled and the chip device becomes more reliable.

The invention relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip power management system, electronic equipment and a three-dimensional integrated chip power management method. The side wall annular power supply bus surrounds the side wall area of the chip stacking body to form a closed annular conductor; and a plurality of tap distribution units arranged on the side wall annular power supply bus, wherein the plurality of tap distribution units are used for electrically connecting the power supply network of each layer of chip in the chip stack to the side wall annular power supply bus. Therefore, the closed annular power supply conductor is constructed on the side wall of the three-dimensional integrated chip stacking body and is connected with the packaging shell in parallel, the decoupling capacitor is integrated, and segmented monitoring control is performed, so that the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient power network reliability and the like caused by traditional TSV longitudinal power supply in a high-density 3D IC are solved; and the power supply integrity and reliability of the three-dimensional integrated chip are improved, and the system life is prolonged.

The present disclosure provides a capacitor configuration method, device and equipment of a power distribution network and a storage medium. The method establishes an equivalent circuit model of a power distribution network without adding on-board decoupling capacitors, and then determines a target capacitor circuit corresponding to the equivalent circuit model based on solving constraint conditions and an objective function. The objective function is established based on the demand for on-board decoupling capacitor cost to optimize the number of decoupling capacitors and avoid over-design of on-board decoupling capacitors, thereby wasting costs. The constraint condition is established based on the impedance of the on-board decoupling capacitor to meet the electrical performance requirement, so as to ensure that the saved capacitor cost can still meet the actual impedance requirement. The impedance simulation of the equivalent circuit model with the target capacitor circuit is further verified to determine whether the target capacitor circuit meets the requirement, so as to ensure that the final target power distribution network can achieve ideal decoupling effect without over-design.

The application is suitable for the field of silicon-based radio frequency and millimeter wave integrated circuit technology, and provides a satellite distributed configuration numerical control unit, a micro single sheet and an antenna unit, which comprises a decoupling capacitor module, a main control module and a distributed satellite module; the positive electrode of the decoupling capacitor module and the power supply pin of the main control module are connected with the power supply pin of the numerical control unit, and the negative electrode of the decoupling capacitor module and the ground pin of the main control module are connected with the ground pin of the numerical control unit; the distributed satellite module comprises a first satellite sub-module, a second satellite sub-module, a third satellite sub-module and a fourth satellite sub-module, and the connection mode of the first satellite sub-module with the main control module, the connection mode of the second satellite sub-module with the main control module, the connection mode of the third satellite sub-module with the main control module and the connection mode of the fourth satellite sub-module with the main control module are the same. The numerical control unit has the bandwidth universality suitable for various microwave bands and the universality suitable for various semiconductor manufacturing processes.

A semiconductor device is disclosed herein. The semiconductor device includes a buried semiconductor layer disposed over a substrate and having a first conductivity type, an epitaxial layer disposed over the buried semiconductor layer and having an opposite second conductivity type, a deep trench isolation structure extending through the epitaxial layer, the buried semiconductor layer, and into the substrate, and a capacitor disposed over the substrate The capacitor interfaces with the deep trench isolation structure and is electrically coupled to the buried semiconductor layer.

A semiconductor device includes a passive device including a passive device including a first backside contact, a shallow trench isolation (STI) above the first backside contact and covering a top surface and an upper half of sidewalls of the first backside contact, and an interconnection layer covering a bottom surface of the first backside contact.

The utility model discloses a multichannel programmable PWM drive circuit based on FPGA, comprising a first decoupling capacitor, a second decoupling capacitor, an FPGA chip, a bidirectional buffer chip, and an extended PWM output chip, the input end of the FPGA chip is connected with a + 1.2 V power supply signal, a + 3.3 V power supply signal, and a clock signal, the output end of the FPGA chip and the input end of the bidirectional buffer chip are connected with the + 3.3 V power supply signal, and the output end of the bidirectional buffer chip is connected with the output end of the extended PWM output chip. The first decoupling capacitor and the second decoupling capacitor are electrically connected with the output end of the bidirectional buffer chip, and the output end of the bidirectional buffer chip and the input end of the extended PWM output chip are connected with VCC voltage signals. The parallel multi-channel PWM drive circuit based on the FPGA can solve the technical problems that when a traditional parallel multi-channel PWM drive circuit based on the FPGA is used for guaranteeing phase synchronization and frequency consistency among multiple channels, complex clock management is depended, the parallel multi-channel PWM drive circuit is easily influenced by wiring delay and clock skew, and therefore waveform distortion is easily caused.

The embodiment of the invention discloses a performance enhancing structure applied to a switch. The performance enhancing structure comprises a chip-level heat dissipation assembly, a board-level management and heat dissipation assembly and a system control heat dissipation assembly, the phase change material layer is arranged on the surface of the switching chip; the board-level management and heat dissipation assembly comprises a liquid cooling pipeline and an electromagnetic wave absorbing layer, and the path of the liquid cooling pipeline is thermally coupled with the phase change material layer and the electromagnetic wave absorbing layer; the system control heat dissipation assembly comprises a main liquid cooling loop and a flow regulating valve, and the main liquid cooling loop is connected with the liquid cooling pipeline to form a closed circulation loop; the board-level management and heat dissipation assembly further comprises a magnetoelectric composite dielectric layer arranged on the printed circuit board, and the path of the magnetoelectric composite dielectric layer and the path of the liquid cooling pipeline are overlapped to provide a decoupling circuit. The embodiment of the invention can be used for absorbing pulse type heat, improving electromagnetic compatibility, giving consideration to the effects of heat dissipation and capacitor decoupling, realizing highly integrated design, improving space utilization rate, and not influencing the effect of the decoupling capacitor due to temperature.

This invention relates to the field of artificial power network technology, specifically to a high-voltage artificial power network system and equipment. It includes a DC decoupling network module integrating decoupling capacitors and discharge resistors for power protection; and a DC load network module electrically interconnected with the DC decoupling network module via cables, integrating a multi-stage resistor array, a heat exchanger system, control components, and a cooling subsystem. The cooling subsystem is configured for water-air heat exchange or water-water heat exchange based on the current output stage of the multi-stage resistor array. This invention features efficient heat dissipation and precise temperature control, real-time closed-loop temperature monitoring, and over-temperature alarms for safety. It can promptly observe localized temperature rises and water levels caused by poor cable contact. Connecting to a host computer via a communication module allows for real-time monitoring by the host computer software, and interlocking protection is implemented with the power supply equipment and the tested equipment, simplifying maintenance.

The invention relates to a decoupling capacitor in a semiconductor device and a method of forming the same. The semiconductor device includes a buried semiconductor layer (110) disposed over a substrate and having a first conductivity type, an epitaxial layer (112) disposed over the buried semiconductor layer and having an opposite second conductivity type, a deep trench isolation structure (120) extending through the epitaxial layer, the buried semiconductor layer and into the substrate, and a capacitor (122 / 132) disposed over the substrate. The capacitor interfaces with the deep trench isolation structure and is electrically coupled to the buried semiconductor layer.

A multi-layer printed circuit board includes a substrate having a first side and a second side opposite the first side, a central via pad disposed on the first side and having a plurality of central-extensions extending outwardly therefrom, a first via pad disposed on the first side and having at least one first-extension extending outwardly therefrom, a second via pad disposed on the first side and having at least one first-extension extending outwardly therefrom, wherein each central-extension has a first-connection-edge, wherein each first-extension has a second-connection-edge, wherein a first first-connection edge of a first central-extension faces a second-connection-edge of the first via pad, and a line perpendicular to the first first-connection edge and to the second-connection-edge of the first via pad forms an angle with a via-to-via axis line between the central via pad and the first via pad, and the angle is greater than a predetermined threshold angle.

The application belongs to the technical field of power management integrated circuits, and particularly relates to a low-voltage power rail circuit applied to a high-side floating basin of a motor driving circuit. The circuit realizes a stable power rail in the floating basin through a super source follower architecture and a bias of MOS tube threshold tracking. The circuit has the advantages that it can track the MOS tube threshold voltage to realize lower static power consumption, can realize fast transient response under different load conditions, has good anti-dv / dt noise capability, and can realize small overshoot voltage during load switching under small decoupling capacitance, thereby reducing the circuit area.

This invention relates to a method for optimizing the placement of bridging capacitors to improve signal quality across split regions on a PCB board. The method includes the following steps: establishing a bridging capacitor simulation model for signal lines crossing a split region of a reference plane; setting the bridging capacitor simulation model to a movable state, using the distance between the bridging capacitor and the signal line as a scanning variable; performing a step-by-step scan within a preset distance range to obtain signal quality parameters at different distances; determining the maximum effective compensation distance of the bridging capacitor relative to the signal line based on the scan results and a preset judgment criterion; and determining the number of bridging capacitors and their placement positions based on the maximum effective compensation distance and the actual width of the cross-segment signal region to be compensated. This invention quantifies the impact of capacitor placement distance on signal quality, scientifically determines the maximum effective compensation distance of the bridging capacitors, and enables reasonable planning of the number and placement of capacitors, balancing wiring density and cost while ensuring signal quality.

The application discloses a kind of three-port converter energy balance control method based on power distribution of pulse frequency sudden drop, in the case where load frequency suddenly drops, the power distribution mode of AC / DC converter is switched, and the fastest change rate that AC / DC converter can provide is controlled to control input source power linearly decreases and linearly increases, after a short adjustment time, energy storage capacitor charging and discharging can be balanced, then the system enters new steady state.Compared with load frequency sudden increase, when three-phase alternating current source input power is too small, pulse load frequency sudden drop is limited by the power distribution mode of AC / DC converter, and it can make pulse load voltage fluctuate, so that the dynamic recovery time of decoupling capacitor voltage is too long, and the original power distribution mode cannot meet the demand of pulse load, so the power distribution mode of AC / DC converter needs to be switched.The problem that the dynamic performance of existing pulse power compensation control method is not optimal after load pulse frequency suddenly drops is solved.

The present disclosure provides an integrated circuit device and associated methods of manufacture and operation having a standard well tap cell disposed over a semiconductor substrate having first and second regions, where the standard well tap cell includes a first tie-rod transistor disposed between a first plurality of LOD protection transistors in the first region, and a second tie-rod transistor disposed between a second plurality of LOD protection transistors in the second region. And a second tie bar transistor disposed between a second plurality of LOD protection transistors in the second region, wherein the first plurality of LOD protection transistors and the second plurality of LOD protection transistors include a first transistor connected as a first decoupling capacitor between a first voltage source and a second voltage source, a second transistor connected as a second decoupling capacitor between the first voltage source and the second voltage source, and a plurality of further dummy transistors, each having a gate, a source, and a drain terminal commonly connected to the supply voltage.

The invention relates to a hardware mainboard based on a Pantou M900 processor, and belongs to the field of computer hardware design. According to the scheme, a main processor, power management, a memory, an expansion interface and an embedded control module are integrated through a modular architecture. The core technical means comprises the following steps of: disclosing hierarchical power supply time sequence control logic, and determining an enabling dependency relationship of each voltage domain and an execution process of an embedded controller; a decoupling capacitor network of the LPDDR4 memory subsystem and a PCB layout are forcibly stipulated to completely copy the verified design; quantitative physical design parameters of the high-speed differential interface are provided; and hardware interfaces of the embedded controller and each controlled unit are completely disclosed. The system has the technical effects that the problems of power supply time sequence black box, high-speed signal rule deficiency and opaque system management interface in high-end SoC platform development are solved, the reliability, performance consistency and manufacturability of a hardware platform are ensured, and intelligent power supply and thermal management are realized.

The application provides a millimeter wave radio frequency power amplifier and a millimeter wave radio frequency transceiver. In the amplifier, input differential signals are connected to the gates of a pair of amplification tubes and a pair of auxiliary tubes through a pair of tube-decoupling capacitors of the auxiliary tubes and a pair of tube-decoupling capacitors of the amplification tubes; the sources of the pair of auxiliary tubes and the pair of amplification tubes are grounded; the drains of the first amplification tube and the first auxiliary tube and the source of the first common-gate tube are connected; the drains of the second amplification tube and the second auxiliary tube and the source of the second common-gate tube are connected; the gates of the pair of common-gate tubes are connected; a common-gate tube gate bias voltage is connected to the gates of the pair of common-gate tubes through a bias resistor, and the other end of a grounding capacitor is connected to the gates of the pair of common-gate tubes; the drains of the pair of common-gate tubes are connected to a parallel capacitor and a primary coil inductance of an output balun, and a secondary coil inductance of the output balun is connected to a single-ended output signal. The application can improve the OP1dB of the radio frequency power amplifier without improving the working voltage of the power amplifier.

The application discloses a silicon carbide power module dynamic current sharing method and system, sets a basic layout of a multi-chip parallel silicon carbide power module, and extracts circuit parasitic parameters; sets silicon carbide power module working conditions, sets bus voltage, load current, and power chip switching speed; sets the highest allowable voltage overshoot, limits the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot; according to the equivalent impedance of the parallel branch after the distributed decoupling capacitor group is added under the set switching speed, the capacitance value of the distributed decoupling capacitor is adjusted, so that the equivalent impedances of the branches are the same. The application solves the problem of uneven current distribution in the traditional parallel technology by integrating the distributed decoupling capacitor, and has important theoretical and practical significance for improving the performance of a power electronic system.