285 results about "Decoupling capacitor" patented technology

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

Disclosed in the present invention is a packaging structure of a half-bridge power module. The packaging structure comprises an insulating and thermal conductive plate, a multi-layer circuit board, a plastic package body and a bridge arm switch. Further disclosed in the present invention is the use of a packaging structure of a half-bridge power module in an OBC power source converter, a DCDC isolated converter, a non-isolated power source converter, a cardiac arrest awakening apparatus, and a circuit module formed by means of combining multiple half bridges such as ANPC, TNPC and Heric. Further disclosed in the present invention is a manufacturing method for a packaging structure of a half-bridge power module. The method comprises: performing assembling; providing an overflow region; and synchronously performing filling and grinding to remove the overflow region. In the present invention, a minimum size and a low impedance are achieved by means of DBC, flexible pin leading-out and welding are realized by means of a PCB, the reliability, safety and heat dissipation of modules are supported by means of a plastic packaging body, and the extension of a temperature monitoring unit and a decoupling capacitor is supported.

The invention discloses an ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator. The ultra-low phase noise harmonic wave type four-core voltage-controlled oscillator is composed of a transformer T1, a transformer T2, a transformer T3, a transformer T4, a head oscillator HR1, a head oscillator HR2, a head oscillator HR3, a head oscillator HR4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a plurality of decoupling capacitors Cecap. According to the voltage-controlled oscillator, noise is prevented from being converted into phase noise by means of second and third harmonic impedance broadening, inductance loss reduction, reduction of the sensitive time of the resonant cavity to the noise and the like, the phase noise generated by the voltage-controlled oscillator can be effectively reduced, and excellent noise performance is obtained.

The invention discloses an orthogonally stacked double-sided cooling power module and a preparation method thereof. The orthogonally stacked double-sided cooling power module comprises a decoupling capacitor, a copper-clad ceramic substrate, a power chip and a metal cushion block, the metal cushion blocks and the power chips are stacked and connected layer by layer in a metal cushion block-power chip-metal cushion block mode to form a series chipset, and the copper-clad ceramic substrate is connected with the two sides of the metal cushion blocks in the series chipset and is perpendicular to the power chips. According to the invention, through the cooperative effect of orthogonal stacking packaging and double-face cooling of the double copper cushion blocks, the electrical and thermal performance of the cooling power module is cooperatively optimized, the parasitic inductance of the power module is significantly reduced, the transient over-current supporting capability is significantly improved, and the packaging technology has good flexibility and is suitable for large-scale production. The method is suitable for power modules of different packaging types.

The invention discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, a middle layer and a decoupling capacitor, the chip layer is electrically connected with the substrate layer; the middle layer is located between the upper chip layer and the lower chip layer, and the upper connecting layer and the lower connecting layer are windowing type copper blocks, are externally connected with DC terminals and are used for connecting the upper substrate layer and the decoupling capacitor; and the decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity to be connected with the copper layers in the laminated layer and the substrate to form the middle layer, the inductance of the machine body is obviously reduced, the heat dissipation effect is improved, the machine body has obvious advantages in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of a power electronic system can be effectively improved.

Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.

The invention provides a decoupling capacitor adjusting method and device, a server and a readable storage medium, which are applied to the technical field of computers, and the method comprises the following steps: firstly, adjusting the power consumption of a load module to enable a voltage adjusting module to output a load current to the load module through a board-level power supply circuit; acquiring a spectrum curve, a maximum current value and a minimum current value of the load current, creating a load model of the load module based on the spectrum curve, the maximum current value and the minimum current value, creating a PDN model based on the load model, controlling the PDN model to operate and acquiring a load terminal voltage of the load model, according to the method, the load model is created on the basis of the PDN actual measurement parameters, it can be ensured that the characteristics shown by the load model are highly attached to the actual load change, the load model is high in credibility, the accuracy and success rate of adjusting the decoupling capacitor are higher, the design period of the PDN is shortened, and the design efficiency of the board-level power supply circuit is improved. And practical application requirements are met.

The invention relates to a semiconductor circuit with selective backside power and ground distribution and maximum area decoupling capacitors. A backside power and ground distribution network is formed on a semiconductor wafer by providing a decoupling capacitor on a backside of a semiconductor substrate layer; selectively etching a TSV opening through the decoupling capacitor and the backside of the semiconductor substrate layer to contact an integrated device connection feature; then forming a ground TSV conductor in the TSV opening, the ground TSV conductor providing a direct electrical connection between a first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer; and also forming a power TSV conductor that provides a direct electrical connection between a second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly electrically connected to the second capacitor plate, and where the ground TSV conductor is not directly electrically connected to the second integrated device connection feature. And wherein the power TSV conductor is not directly electrically connected to the first capacitor plate.

The utility model relates to a nitrogen making machine electromagnetic compatibility processing device, which comprises a device body, and the device body comprises a nitrogen making machine shell. The shielding box is provided with an accommodating chamber and comprises a shielding box body and a shielding box cover which are mutually occluded and sealed, and a conductive rubber strip is arranged between the contact surfaces of the shielding box body and the shielding box cover; the filtering assembly is arranged in the shielding box accommodating chamber and comprises a common mode inductor and a high-frequency decoupling capacitor; the common mode inductor is arranged in the shielding box, the interface assembly is exposed on the side wall of the shielding box, the interface assembly comprises an input interface and an output interface which are oppositely arranged, the input interface comprises an aviation socket, the output interface comprises a feed-through filter, the aviation socket is connected with the common mode inductor, and the common mode inductor is connected with the feed-through filter. According to the nitrogen making machine equipment, the anti-interference performance can be improved, and meanwhile, the external interference capability of the nitrogen making machine serving as a disturbance source is also reduced.

The invention discloses a packaging structure of a half-bridge power module. The packaging structure comprises an insulating heat-conducting plate, a multi-layer circuit board, a plastic packaging body and a bridge arm switch, on the other hand, the invention discloses application of the packaging structure of the half-bridge power module in a vehicle-mounted OBC power converter, a DCDC isolation converter, a non-isolation power converter, a cardiac arrest wake-up device and a circuit module formed by combining multiple half bridges such as ANPC, TNPC and Heric. The invention further discloses a manufacturing method of the packaging structure of the half-bridge power module. The manufacturing method comprises the steps of assembling, arranging the overflow area and synchronously filling and grinding to remove the overflow area. The minimum size and low impedance are achieved through the DBC, flexible pin outgoing and welding are achieved through the PCB, the reliability, safety and heat dissipation of the module are supported through the plastic package body, and the expansion temperature monitoring unit and the decoupling capacitor are supported.

The invention belongs to the technical field of power electronics, and relates to a high-side-ratio non-isolated hybrid switched capacitor converter which is used for direct 48V-1V power conversion of a data center and comprises switching tubes S1 to S38, flying capacitors C1 to C15, inductors L1 to L8, an input end Vin, an output end Vout and a grounding end. The switch tubes S1-S6 and the flying capacitors C1-C3 form a 4: 1 switched capacitor buck converter part; the switch tubes S7-S38, the flying capacitors C4-C15 and the inductors L1-L8 form a voltage-adjustable multi-channel mixed buck converter; mixing of the pre-buck converter and the voltage-adjustable buck converter is achieved through the exchange bus, the advantages of the pre-buck converter and the voltage-adjustable buck converter can be well fused, the defects of the pre-buck converter and the voltage-adjustable buck converter can be overcome, a bus decoupling capacitor is not needed, and the number of switches can be reduced. According to the multi-channel mixed buck converter, a capacitance channel is added, the conduction loss of an inductance channel is reduced, ripples are reduced, the duty ratio is increased, and the voltage stress of a switching tube is reduced; the hybrid switched capacitor converter has the advantages of being large in transformation ratio, high in power density and small in device stress.

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

The invention discloses a silicon carbide power module dynamic current sharing method and system, and the method comprises the steps: setting a basic layout of a multi-chip parallel silicon carbide power module, and extracting circuit parasitic parameters; setting working conditions of the silicon carbide power module, and setting bus voltage, load current and power chip switching speed; setting the maximum allowable voltage overshoot, and limiting the total capacitance value of the distributed decoupling capacitor bank according to the voltage overshoot; and according to the equivalent impedance of the parallel branches at the set switching speed after the distributed decoupling capacitor bank is added, the capacitance value of the distributed decoupling capacitor is adjusted, so that the equivalent impedance of each branch is the same. By integrating the distributed decoupling capacitors, the problem of non-uniform current distribution in the traditional parallel connection technology is solved, and the method has important theoretical and practical significance for improving the performance of a power electronic system.

Package substrate with embedded capacitor package with a redistribution layer(s) (RDL(s)) for aligning capacitor terminals to die interconnects of a semiconductor die (“die”) in an integrated circuit (IC) package, and related IC packages and fabrication methods. The capacitor package can be embedded in a package substrate of an IC package, such as to provide a decoupling capacitance or filter for a die of the IC package. A RDL(s) is built on a substrate of a capacitor of the capacitor package such that RDL interconnects of the RDL(s) are coupled to capacitor terminals of the capacitor. The RDL(s) redistributes connections to the capacitor terminals of the capacitor, to a desired pattern and / or pitch to align the capacitor terminals with die interconnects of a die coupled to the package substrate of the IC package. This minimizes signal path length between the capacitor and die to minimize inductance in the capacitive loop.

The invention relates to the technical field of wiring structures, and discloses a low-power-consumption communication circuit board wiring structure, which comprises a shell internally provided with a plurality of layers of circuit boards for protecting the whole device; the wiring structure is arranged on the multilayer circuit board and is used for providing enough electric energy; the control module is fixed on the multi-layer circuit board and is used for controlling the start and stop states of each functional module on the multi-layer circuit board; the differential signal wiring module is fixed on the multilayer circuit board and is used for transmitting high-frequency signals; and the decoupling capacitor module is fixed on the multilayer circuit board and is used for reducing power supply noise and stabilizing power supply voltage. By introducing a special coating made of a high-conductivity material into the multilayer circuit board wiring structure and integrating advanced signal adjustment and calibration functions in the differential signal wiring module, the loss in the electric energy transmission process is effectively reduced, and the integrity and anti-interference capability of signals are remarkably improved in high-frequency signal transmission.

The invention relates to the technical field of electromagnetic interference filtering, in particular to a control board card electromagnetic interference suppression method. According to the method, electromagnetic interference frequency and related parasitic parameters on a control board card are determined by analyzing electromagnetic interference generation and conduction mechanisms around the control board card on the LLC resonant converter, in Pspice simulation software, a sampling circuit is utilized to simulate circuit functions on a key loop, and influence of external electromagnetic interference on the key loop is analyzed, so that the LLC resonant converter is simulated. Based on the analyzed influence of electromagnetic interference on the control board card, the models of various devices on the filter circuit are determined, the designed filter circuit is added into a sampling circuit of the control board card, external electromagnetic interference is suppressed, a decoupling capacitor is added between a power supply of the control board card and the ground plane, internal resonance of the control board card is suppressed, and the control board card is controlled to be in a filtering state. The power density of the switching power supply system is improved, and the reliability of the control signal is ensured.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

The invention relates to a self-decoupling coil array for magnetic resonance imaging, which comprises resonance coils with detuning loops, the resonance coils are connected in series with decoupling capacitors, the two resonance coils are oppositely arranged at the positions where the decoupling capacitors are arranged so as to form decoupling units, and the multiple decoupling units are arranged in at least one direction. The decoupling units which are oppositely arranged at the position of the decoupling capacitor can enable one resonance coil to decouple the other resonance coil, and the decoupling units exist in the self-decoupling coil array in pairs, so that electric coupling does not occur in the whole self-decoupling coil array to realize self-decoupling. Compared with the prior art, the self-decoupling coil array for magnetic resonance imaging disclosed by the invention realizes decoupling between detuning resonance circuits by introducing additional electric coupling, so that the sensitivity is kept at a due level, and the imaging signal-to-noise ratio gain is more uniform.

The embodiment of the invention discloses a power amplifier circuit, a radio frequency chip and electronic equipment. The power amplifier circuit comprises at least two stages of cascaded power amplifiers, the low-frequency resonance network comprises a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a grounding end; the second capacitor is coupled between the first end of the power amplifier and the grounding end; the first inductor is coupled between the first capacitor and the second capacitor; the first capacitor comprises a decoupling capacitor.

The present invention belongs to the field of intelligent monitoring technology, specifically relating to a health monitoring system and its preparation method. The system comprises a health monitoring mask and a host computer. The health monitoring mask includes the mask and its built-in respiratory monitoring unit, heart rate monitoring unit, and health monitoring unit. The host computer includes a display interface and its built-in data processing module. The respiratory monitoring unit includes a thermoelectric device made of P-type and N-type semiconductor thermoelectric particles. The heart rate monitoring unit consists of a MAX30102 integrated on a flexible PCB, a voltage regulator circuit, a decoupling capacitor, and a pull-up resistor. The health monitoring unit is sewn into the mask and includes an ADC conversion unit I, a microcontroller chip with a built-in Bluetooth module and an integrated circuit bus. The host computer includes a display interface and a data processing module to receive monitoring data from the respiratory monitoring unit and the heart rate monitoring unit, match the data into groups, and perform multi-source fusion. Based on the multi-source fusion data, the health status of the human body can be identified and judged.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Semiconductor device packages including leads for enhanced video bandwidth and related operating criteria are described. An example package includes a flange having a top surface, a frame secured to the flange, and a pair of output leads. The frame forms an air cavity bounded in part by the top surface of the flange. The pair of output leads extend from outside the frame, through at least a portion of the frame, and to within the air cavity. The package also includes a decoupling lead positioned between the pair of output leads. The package also includes a second decoupling lead positioned between the pair of output leads in some examples. The decoupling lead or leads between the output leads facilitate the use of off-package decoupling capacitors to meet video bandwidth and other operating specifications. The package can also include one or more additional decoupling leads between input leads.

The utility model relates to a kind of temperature chip test circuit of supporting fast and slow power-on and fast reset, mainly including chip U1, chip U2, chip port P1 to be measured, the 15 pin of chip U2, 14 pin connect external IIC bus, the 4,5,6,7 pin of chip U2 are general I / O pin, respectively connect the 13,5,6,12 pin of chip U1, and there is also decoupling capacitor C2 on the 16 pin of chip U2, the 8 pin,11 pin of chip U1 is connected to GND by resistance R2 and capacitor C3 respectively, the 2,3,9,10 pin of chip U1 are all connected to the 1 pin of chip port P1 to be measured, and there is also decoupling capacitor C1 on the 14 pin of chip U1.The utility model circuit simple structure, cost is lower, can be easily integrated into original test circuit, under the premise of retaining original test project, increase the performance evaluation and screening of temperature chip under the mode of fast power-on and slow power-on, and have fast and thorough reset function.

This invention belongs to the field of wireless communication technology. It provides a differential amplifier system and a method for improving common-mode stability. The invention uses a large decoupling capacitor C1 at the transformer center tap to provide AC ground, and a common-mode resistor R1 to improve the circuit's common-mode stability. Since the common-mode resistor R1 is not in the differential signal loop path, the use of common-mode resistor technology does not affect differential-mode performance. Because the required common-mode resistor value is small, this design occupies a small layout area. This invention solves the problem of low common-mode stability in differential amplifiers.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

An amplifier device, such as a Doherty amplifier device, may include an extra lead and decoupling capacitor coupled to radio frequency (RF) cold points of output impedance matching circuitry of multiple amplification paths, such as a carrier path and peaking path, of the amplifier device. The extra lead and the decoupling capacitor are configured to provide low frequency resonance decoupling for the multiple amplification paths. A drain bias voltage may be provided to the drain terminals of transistors of amplifiers of the amplifier device via the extra lead. An integrated passive device (IPD) including a wire fence and one or more conductive pads may be disposed between a carrier amplifier die and a peaking amplifier. The extra lead may be coupled to the RF cold points via the IPD. The wire fence may mitigate RF interference between the carrier amplifier die and the peaking amplifier die.

The present invention relates to a circuitry system (1). The circuitry system (1) comprises a reservoir power rail (12), a regulated power rail (14), a logic circuitry (18) connected to the regulated power rail (14), wherein each of the reservoir power rail (12), regulated power rail (14) and logic circuitry (18) is connected to respective voltage supply source (16), characterized by a dynamic decoupling capacitor (10) connecting the reservoir power rail (12) to the regulated power rail (14), and in communication with the logic circuitry (18), wherein the dynamic decoupling capacitor (10) is configured to match a total-charge of injected-current, ldecap, from the reservoir power rail (12) with a total-charge of load-current, lload, supplying to the logic circuitry (18). A method for regulating voltage of the circuitry system (1) is also disclosed herein.

The invention discloses a reference power supply fluctuation stabilization method for a successive approximation analog-to-digital converter, which is applied to a sectional successive approximation analog-to-digital converter. Designing a linear charge compensation circuit, and improving a reference power supply circuit of the fine quantization ADC; the reference power supply circuit of the fine quantization ADC comprises a buffer and a linear charge compensation circuit. The linear charge compensation circuit comprises a binary capacitor array used for providing compensation charges and a control circuit, serves as an auxiliary power supply circuit and is used for rapidly stabilizing reference power supply fluctuation generated by most significant bit switching of the fine quantization ADC before comparison of least significant bits, and the conversion precision of fine quantization is improved. According to the invention, the influence of the reference power supply fluctuation on the conversion precision can be reduced, and the conversion speed and the conversion precision of the SAR ADC can be improved; and meanwhile, the requirements on a high-power-consumption on-chip reference power supply driver and a large-area on-chip decoupling capacitor are greatly reduced, and the power consumption and the area overhead of the SAR ADC are reduced.

The utility model relates to a lithium battery charging and discharging management circuit with a protection function, which comprises a charging input filtering unit, a power adjusting unit, a battery protection unit, a feedback control unit, a logic switching unit and an output interface unit, and is characterized in that the charging input filtering unit suppresses input interference through a symmetrical inductor and a multistage decoupling capacitor; the power adjusting unit is used for converting the input energy into a target charging parameter; the battery protection unit works cooperatively with the protection chip through the back-to-back double MOSFET array, so that overvoltage / undervoltage quick turn-off is realized; the feedback control unit compares the voltage division sampling signal with an adjustable reference by using a dual-comparator network to generate a PWM closed-loop adjusting signal; and the logic switching unit constructs a logic AND circuit through a multi-channel MOSFET switch group, and responds to a protection signal to forcibly cut off a power path. And dynamic adjustment and multiple protection mechanisms are fused through modular design, so that the charging and discharging efficiency and the system safety are remarkably improved, and the method is suitable for a high-reliability lithium battery management system.

A voltage-controlled oscillator (VCO) is disclosed that includes an inductor-capacitor (LC) tank coupled with a first voltage supply node, a pair of cross-coupled transistors that are coupled with the LC tank and coupled with each other at a tail node, and a high-frequency current return path to the first voltage supply node. The high-frequency return path includes a first decoupling capacitor coupled with the first voltage supply node and a second voltage supply node, and a first inductor coupled with the tail node and the second voltage supply node. The first inductor is formed as a first conductive trace and has a quality factor (Q) value of 25 or greater.