148 results about "Decoupling capacitor" patented technology

Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Semiconductor device packages including leads for enhanced video bandwidth and related operating criteria are described. An example package includes a flange having a top surface, a frame secured to the flange, and a pair of output leads. The frame forms an air cavity bounded in part by the top surface of the flange. The pair of output leads extend from outside the frame, through at least a portion of the frame, and to within the air cavity. The package also includes a decoupling lead positioned between the pair of output leads. The package also includes a second decoupling lead positioned between the pair of output leads in some examples. The decoupling lead or leads between the output leads facilitate the use of off-package decoupling capacitors to meet video bandwidth and other operating specifications. The package can also include one or more additional decoupling leads between input leads.

The utility model relates to a kind of temperature chip test circuit of supporting fast and slow power-on and fast reset, mainly including chip U1, chip U2, chip port P1 to be measured, the 15 pin of chip U2, 14 pin connect external IIC bus, the 4,5,6,7 pin of chip U2 are general I / O pin, respectively connect the 13,5,6,12 pin of chip U1, and there is also decoupling capacitor C2 on the 16 pin of chip U2, the 8 pin,11 pin of chip U1 is connected to GND by resistance R2 and capacitor C3 respectively, the 2,3,9,10 pin of chip U1 are all connected to the 1 pin of chip port P1 to be measured, and there is also decoupling capacitor C1 on the 14 pin of chip U1.The utility model circuit simple structure, cost is lower, can be easily integrated into original test circuit, under the premise of retaining original test project, increase the performance evaluation and screening of temperature chip under the mode of fast power-on and slow power-on, and have fast and thorough reset function.

This invention belongs to the field of wireless communication technology. It provides a differential amplifier system and a method for improving common-mode stability. The invention uses a large decoupling capacitor C1 at the transformer center tap to provide AC ground, and a common-mode resistor R1 to improve the circuit's common-mode stability. Since the common-mode resistor R1 is not in the differential signal loop path, the use of common-mode resistor technology does not affect differential-mode performance. Because the required common-mode resistor value is small, this design occupies a small layout area. This invention solves the problem of low common-mode stability in differential amplifiers.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

An amplifier device, such as a Doherty amplifier device, may include an extra lead and decoupling capacitor coupled to radio frequency (RF) cold points of output impedance matching circuitry of multiple amplification paths, such as a carrier path and peaking path, of the amplifier device. The extra lead and the decoupling capacitor are configured to provide low frequency resonance decoupling for the multiple amplification paths. A drain bias voltage may be provided to the drain terminals of transistors of amplifiers of the amplifier device via the extra lead. An integrated passive device (IPD) including a wire fence and one or more conductive pads may be disposed between a carrier amplifier die and a peaking amplifier. The extra lead may be coupled to the RF cold points via the IPD. The wire fence may mitigate RF interference between the carrier amplifier die and the peaking amplifier die.

The present invention relates to a circuitry system (1). The circuitry system (1) comprises a reservoir power rail (12), a regulated power rail (14), a logic circuitry (18) connected to the regulated power rail (14), wherein each of the reservoir power rail (12), regulated power rail (14) and logic circuitry (18) is connected to respective voltage supply source (16), characterized by a dynamic decoupling capacitor (10) connecting the reservoir power rail (12) to the regulated power rail (14), and in communication with the logic circuitry (18), wherein the dynamic decoupling capacitor (10) is configured to match a total-charge of injected-current, ldecap, from the reservoir power rail (12) with a total-charge of load-current, lload, supplying to the logic circuitry (18). A method for regulating voltage of the circuitry system (1) is also disclosed herein.

The utility model relates to a lithium battery charging and discharging management circuit with a protection function, which comprises a charging input filtering unit, a power adjusting unit, a battery protection unit, a feedback control unit, a logic switching unit and an output interface unit, and is characterized in that the charging input filtering unit suppresses input interference through a symmetrical inductor and a multistage decoupling capacitor; the power adjusting unit is used for converting the input energy into a target charging parameter; the battery protection unit works cooperatively with the protection chip through the back-to-back double MOSFET array, so that overvoltage / undervoltage quick turn-off is realized; the feedback control unit compares the voltage division sampling signal with an adjustable reference by using a dual-comparator network to generate a PWM closed-loop adjusting signal; and the logic switching unit constructs a logic AND circuit through a multi-channel MOSFET switch group, and responds to a protection signal to forcibly cut off a power path. And dynamic adjustment and multiple protection mechanisms are fused through modular design, so that the charging and discharging efficiency and the system safety are remarkably improved, and the method is suitable for a high-reliability lithium battery management system.

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

The invention belongs to the field of manufacturing of printed circuits and assemblies thereof, and discloses a low-inductance lamination assembly method of a pulse power module, which comprises the following steps: placing a power semiconductor device and a decoupling capacitor into a cavity of a core substrate in a coplanar manner; laminating insulating layers and selectively windowing by using a closed-loop control method based on plasma spectrum monitoring; and finally, a bridging conductive layer directly bridging the top terminal of the element is formed through metal deposition. According to the invention, a lamination step is multiplexed as a key electrical connection forming process, and the dimension of a traditional three-dimensional commutation loop is reduced to a quasi-two-dimensional plane on a topological structure; therefore, current path geometric abrupt change and inductance bottleneck caused by vertical via holes are broken, and a structural basis is established for improving the electrical performance and electromagnetic compatibility of the module.

A semiconductor device is provided. The semiconductor device comprises a first circuit and a capacitor circuit. The first circuit has an input terminal configured to receive an input signal. The capacitor circuit comprises a first transistor and a second transistor. The first transistor is coupled between a first supply voltage and the input terminal. Source / drain terminals of the first transistor are coupled to each other. The second transistor is stacked above the first transistor and coupled between a second supply voltage and the input terminal. Source / drain terminals of the second transistor are coupled to each other. The first and second transistors are decoupling capacitors of the first circuit.

Embodiments of the disclosure provide a semiconductor device. The semiconductor device includes a circuit and a first bitcell array. The circuit is coupled to a first power rail and a second power rail. The first bitcell array includes a first subarray having a plurality of first bitcells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first bitcells are configured as a decoupling capacitor between the first power rail and the second power rail.

The invention provides an image sensor. The image sensor comprises a plurality of pixel circuits arranged in an array; the pixel circuit comprises a photodiode, a floating diffusion part, a transmission transistor, a dual-conversion gain transistor, a reset transistor, a power supply voltage line and at least one decoupling capacitor, wherein the decoupling capacitor comprises a substrate; the N-type region is arranged on one side of the substrate, and the N-type region comprises an N-type source region and an N-type drain region; the N-type source electrode region and the N-type drain electrode region are respectively grounded; the gate insulating layer is arranged on one side, far away from the substrate, of the N-type region; the at least one vertical transmission grid electrode is arranged on one side, far away from the N-type region, of the grid electrode insulating layer; the vertical transmission grid comprises a top part and at least two vertical poles extending towards the N-type region; and the top of the vertical transmission grid of the decoupling capacitor is electrically connected with a power supply voltage line. The capacitance value of the decoupling capacitor can be improved, and row noise in a pixel circuit of the image sensor can be reduced.

The application discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, an intermediate layer and a decoupling capacitor; the chip layer is electrically connected with the substrate layer; the intermediate layer is located between the upper chip layer and the lower chip layer; the upper connecting layer and the lower connecting layer are windowed copper blocks, and are externally connected with DC terminals and used for connecting the upper substrate layer and the decoupling capacitor; the decoupling capacitor is two groups of capacitors arranged on the side of the intermediate layer and electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity, the intermediate layer is connected with the copper layer in the laminated layer and the substrate, the body inductance is obviously reduced, the heat dissipation effect is improved, obvious advantages are obtained in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of the power electronic system can be effectively improved.

The invention belongs to the technical field of automotive electronics, and relates to a high-anti-interference controller PCB layout structure for an electric power steering system, a PCB is a multilayer board, and the PCB layout structure is characterized in that a power ground loop of a high-frequency switching circuit is directly connected to a grounding end of a common mode inductor to realize single-point discharge of high-frequency noise; the analog signal circuit is far away from the high-frequency digital signal circuit in layout; the MCU power supply decoupling capacitors are arranged around the MCU in a distributed star network; the PCB layout structure is provided with a power ground plane and a signal ground plane which are completely isolated, and the power ground plane and the signal ground plane are connected only through a single common mode inductor; in the PCB layout structure, a driving signal, a feedback signal, a sampling signal and a power signal of the inverter bridge part are respectively arranged in different PCB layers; the current sampling precision and the system reliability are remarkably improved, the steering hand feeling is improved, the electromagnetic compatibility is excellent, and the engineering application value is very high.

The invention relates to a circuit system (1). The circuit system (1) comprises an energy storage power supply rail (12), a regulated power supply rail (14), a logic circuit (18) connected to the regulated power supply rail (14), where each of the energy storage power supply rail (12), the regulated power supply rail (14) and the logic circuit (18) is connected to a common ground (16), where a dynamic decoupling capacitor (10) connects the energy storage power supply rail (12) to the regulated power supply rail (14) and communicates with the logic circuit (18), wherein the dynamic decoupling capacitor (10) is configured to match the total charge of the injection current Idecap from the energy storage supply rail (12) with the total charge of the load current Iload provided to the logic circuit (18). A method of regulating a voltage by a regulating circuitry (1) is encompassed herein.

This utility model relates to the field of circuit technology and discloses a dual 85 test circuit for an AC-DC power supply chip. A high-voltage DC power supply is connected to the SW pin of the AC-DC chip through a current-limiting resistor network. A current detection module consists of a first resistor connected in series between the CS pin of the AC-DC chip and ground. A power supply module includes a decoupling capacitor connected between the VDD pin of the AC-DC chip and ground, and a power supply providing DC voltage to the VDD pin. A feedback control module includes an RC network (with a second resistor connected in series with the first capacitor) connected in parallel between the COMP pin of the AC-DC chip and ground. Multiple test circuits are integrated in parallel on the same PCB board to form a multi-channel test system. This utility model overcomes the shortcomings of THB testing and whole-machine dual 85 testing, achieving the advantage of performing dual 85 testing under simulated actual operating conditions (PWM operation state) while increasing the number of tests to 77 PCS.

A power device threshold voltage measurement circuit and its operation method thereof are provided. The measurement circuit includes a switch component, a device under test, a common source capacitor and a decoupling capacitor. The switch component and the device under test forms a half bridge circuit and the common source capacitor is in series connected at the source of the device under test. The device under test is connected as a lower switch of the half bridge circuit and the decoupling capacitor is connected between the device under test and the common source capacitor. By applying an OFF-state stress mode and a measurement mode successively afterwards, a threshold voltage of the device under test is obtained. And the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.

The application discloses a power distribution network decoupling capacitor arrangement optimization method based on an improved genetic algorithm. First, the ports of the power distribution network are prioritized to obtain port ordering subcolumns corresponding to various capacitors; then, according to the port ordering subcolumns corresponding to various capacitors, optimal capacitors and corresponding ports for placement are selected from a capacitor library in sequence until the observation impedance is less than the target impedance at all frequency points, and an initial decoupling capacitor arrangement is obtained; finally, after the initial decoupling capacitor arrangement is iteratively optimized by using the improved genetic algorithm, an optimal decoupling capacitor arrangement is obtained. The method has high search efficiency, fast convergence speed and good robustness, the genetic algorithm is modified according to the capacitor combination optimization application scene, and the optimal capacitor configuration meeting the target impedance can be efficiently found.

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces, and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures can be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures can be stacked to form a multilayer structure.

A semiconductor chip device includes a substrate with a first dielectric material of a first permittivity value. A power input line and ground line are positioned in the substrate and arranged to form a decoupling capacitor. A region of the substrate in between the power input line and the ground line is doped with a second dielectric material of a second permittivity value that is higher than the first permittivity value. The region doped with the second dielectric material lacks a signal body. By incorporating a region with higher permittivity, in what is generally unused space for power delivery, the region becomes a decoupling capacitor for nearby power delivery elements. By adding decoupling capacitance to the previously unused space, noise in a circuit is more easily controlled and the chip device becomes more reliable.

The invention relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip power management system, electronic equipment and a three-dimensional integrated chip power management method. The side wall annular power supply bus surrounds the side wall area of the chip stacking body to form a closed annular conductor; and a plurality of tap distribution units arranged on the side wall annular power supply bus, wherein the plurality of tap distribution units are used for electrically connecting the power supply network of each layer of chip in the chip stack to the side wall annular power supply bus. Therefore, the closed annular power supply conductor is constructed on the side wall of the three-dimensional integrated chip stacking body and is connected with the packaging shell in parallel, the decoupling capacitor is integrated, and segmented monitoring control is performed, so that the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient power network reliability and the like caused by traditional TSV longitudinal power supply in a high-density 3D IC are solved; and the power supply integrity and reliability of the three-dimensional integrated chip are improved, and the system life is prolonged.

The present disclosure provides a capacitor configuration method, device and equipment of a power distribution network and a storage medium. The method establishes an equivalent circuit model of a power distribution network without adding on-board decoupling capacitors, and then determines a target capacitor circuit corresponding to the equivalent circuit model based on solving constraint conditions and an objective function. The objective function is established based on the demand for on-board decoupling capacitor cost to optimize the number of decoupling capacitors and avoid over-design of on-board decoupling capacitors, thereby wasting costs. The constraint condition is established based on the impedance of the on-board decoupling capacitor to meet the electrical performance requirement, so as to ensure that the saved capacitor cost can still meet the actual impedance requirement. The impedance simulation of the equivalent circuit model with the target capacitor circuit is further verified to determine whether the target capacitor circuit meets the requirement, so as to ensure that the final target power distribution network can achieve ideal decoupling effect without over-design.

The utility model discloses a CAN communication and protection interface module of an electric energy metering box assembly and verification all-in-one machine, and the module comprises a CAN transceiver which is provided with a data transmitting end, a data receiving end, a standby control end, a differential output high end, and a differential output low end; the decoupling capacitor clings to the power supply end of the CAN transceiver and is connected with the ground end; the terminal resistor is directly bridged between the differential output high end and the differential output low end of the CAN transceiver; the TVS protection array adopts a bridge type structure and is used for respectively connecting the differential output high end and the differential output low end to a power supply and the ground through a diode array; and the differential signal pin is connected to the differential output high end and the differential output low end, and the plurality of parallel ground pins are connected with the system ground through wide wiring. The CAN communication and protection interface module of the electric energy metering box assembly and verification all-in-one machine has the characteristics of high anti-interference capability, low power consumption and high reliability.

The application discloses a kind of orthogonal stacked double-sided cooling power module and preparation method thereof, including decoupling capacitor, copper clad ceramic substrate, power chip and metal pad;The metal pad and power chip are connected by layer-by-layer stacking in the mode of metal pad-power chip-metal pad to form a series chip set, the copper clad ceramic substrate is connected with the two sides of metal pad in series chip set, and it is perpendicular to power chip.The synergistic effect of orthogonal stacked packaging and double copper pad double-sided cooling in the application optimizes the electrical and thermal performance of the cooling power module, significantly reduces the parasitic inductance of the power module, and significantly improves the transient overcurrent support capability.

The application is suitable for the field of silicon-based radio frequency and millimeter wave integrated circuit technology, and provides a satellite distributed configuration numerical control unit, a micro single sheet and an antenna unit, which comprises a decoupling capacitor module, a main control module and a distributed satellite module; the positive electrode of the decoupling capacitor module and the power supply pin of the main control module are connected with the power supply pin of the numerical control unit, and the negative electrode of the decoupling capacitor module and the ground pin of the main control module are connected with the ground pin of the numerical control unit; the distributed satellite module comprises a first satellite sub-module, a second satellite sub-module, a third satellite sub-module and a fourth satellite sub-module, and the connection mode of the first satellite sub-module with the main control module, the connection mode of the second satellite sub-module with the main control module, the connection mode of the third satellite sub-module with the main control module and the connection mode of the fourth satellite sub-module with the main control module are the same. The numerical control unit has the bandwidth universality suitable for various microwave bands and the universality suitable for various semiconductor manufacturing processes.

A semiconductor device is disclosed herein. The semiconductor device includes a buried semiconductor layer disposed over a substrate and having a first conductivity type, an epitaxial layer disposed over the buried semiconductor layer and having an opposite second conductivity type, a deep trench isolation structure extending through the epitaxial layer, the buried semiconductor layer, and into the substrate, and a capacitor disposed over the substrate The capacitor interfaces with the deep trench isolation structure and is electrically coupled to the buried semiconductor layer.

A semiconductor device includes a passive device including a passive device including a first backside contact, a shallow trench isolation (STI) above the first backside contact and covering a top surface and an upper half of sidewalls of the first backside contact, and an interconnection layer covering a bottom surface of the first backside contact.