Structure and method for lead free solder electronic package interconnections

Abstract

An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join / assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn / Ag and Sn / Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join / assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

Description

RELATED APPLICATIONS [0001] This application is related to subject matter described and claimed in U.S. patent application Ser. No. 10 / 246,282 (attorney docket no. FIS9-2002-0017US1) entitled “Solder Hierarchy For Lead Free Solder Joint” by the inventors of the instant application.BACKGROUND OF THE INVENTION [0002] The present invention relates to a lead free solder structure for the assembly of electronic components, and more particularly, to a lead free solder hierarchy for use in the assembly of electronic components. [0003] Current controlled collapse chip connection (C4) or “flip chip” interconnection technology for joining chips to either ceramic or organic substrates typically employ a 97 / 3 Pb / Sn joining solder alloy as the ball-limiting metallurgy (BLM) on the chip side of the interconnect, and a suitable metallization, typically Ni / Au or Cr / Cu / Ni / Au, on the substrate side of the interconnect. This interconnect structure has to withstand temperature cycling. This temperature...

AI Technical Summary

Benefits of technology

[0053] An additional advantage of the present invention is that for chip on board applications, a small amount of eutectic Sn / Ag, Sn / Cu or Sn / Ag / Cu could be used, so that the chip join reflow cycle can be maintained with a peak reflow temperature of 250° C. or less. This would be applicable to the high temp / low temp Pb-free C4 solution for direct chip on organic package situations.

Problems solved by technology

A current problem now facing the industry is that lead elimination is a strategic requirement for all manufacturers.

An additional problem is that in manufacturing, joining the chip to a first level package, typically a ceramic or organic chip carrier, is the first step.

Using a Pb free, Sn rich alloy for both first level chip join and second level module to board join creates the problem of the chip BLM becoming molten during the second level attach processes and subsequent reflows such as may be required for rework.

Another problem is that when the first level SnAgCu solder interconnect becomes completely molten inside the underfill encapsulant, it produces large hydrostatic stresses on the walls of the encapsulant.

These forces create strains large enough to cause delamination, cracking, rupture and finally, catastrophic fail of the encapsulant regions.

This would likely cause shorting between the C4 solder connections, and potentially cause opens where the C4 solder connections may break away from their original as-joined position.

Whereas other alloy systems such as AuSn 80 / 20 may be employed to produce a solder temperature hierarchy, such solutions may not be widely applicable because of various manufacturing problems.

Examples include the cost of the materials, brittle metallurgical properties and solder interactions which cause stress on the chip.

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