146results about "Error correction/detection using interleaving techniques" patented technology

Disclosed herein are an FFT processor, an FFT computing method, a radar signal processing system-on-chip, an integrated circuit, and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT kernels, and the FFT processor has at least two operating modes among a large-point-number FFT mode, a pipeline mode and an independent parallel mode, wherein when the FFT processor is in the large-point-number FFT mode, the two FFT kernels are configured to decompose FFT of N points into two instances of FFT; when the FFT processor is in the pipeline mode, the former FFT kernel of the two cascaded FFT kernels is configured to perform distance FFT, and the latter FFT kernel of the two cascaded FFT kernels is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT kernels are configured to independently process data of different channels in parallel.

Polar codes for wireless communications are constructed to adapt to channel conditions. Input bits are encoded by a polar code to obtain a number of encoded bits, and a reduced number of the encoded bits are decoded to obtain decoded input bits. The polar code provides or includes bit indices for bit values, and the bit indices include a first set of bit indices for values of the input bits and a second set of bit indices for a predetermined bit value. Encoded bits in a subset, which includes fewer than all of the encoded bits and is for reducing the number of the encoded bits, are interleaved.

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

The invention discloses an RMFE-based distributed matrix multiplication implementation method. The method comprises the following steps: initializing parameters, constructing an RMFE function, splitting a to-be-processed matrix sequence into sequence vectors, sequentially carrying out phi function operation, obtaining a matrix distributed multiplication result through distributed matrix multiplication, and recovering through psi function operation to obtain a multiplication result of a to-be-processed matrix. According to the method, a distributed multiplication problem of a plurality of matrixes on a small domain / Galois ring is converted into a distributed multiplication problem of a single matrix on a large domain / Galois ring, and the calculation overhead on an expansion domain is allocated to the plurality of matrixes, so that the communication overhead required by distributed matrix multiplication is effectively reduced; the method has important application value for a high-speed communication system.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

A method and an apparatus for processing an Ethernet data stream, a computer system, a network system, and a computer-readable storage medium are disclosed. The method is applied to a receiver apparatus including a first forward error correction FEC decoder and a second FEC decoder. The method includes: obtaining transmission information of a first data stream; and if the transmission information meets a trigger condition, adjusting an error correction capability of the receiver apparatus. The data stream can be flexibly and effectively processed by using the method, the apparatus, the computer system, the network system, and the computer-readable storage medium.

Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.

Described herein are systems and methods for encoding digital data into oligonucleotides and decoding the oligonucleotides back to digital data. The encoding and decoding schemes include inner codecs for converting digital data to bases and bases to digital data. The encoding and decoding schemes also include outer codecs that include error correction schemes.

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

Embodiments of this application disclose an interleaving method supporting unequal modulation, a subcarrier mapping method supporting unequal modulation, and a related apparatus. An interleaver includes a first interleaver and a second interleaver, the interleaver is configured to determine an order of information bits carried in a subcarrier of a first RU and a subcarrier of a second RU, and a modulation scheme of the first RU is different from a modulation scheme of the second RU. The first interleaver is configured to input information bits by row. A quantity of columns of the first interleaver is M1+M2, a quantity of rows of the first interleaver is a larger value in N1 and N2, N1 and M1 are determined based on a quantity of subcarriers of the first RU, and N2 and M2 are determined based on a quantity of subcarriers of the second RU. The second interleaver is configured to receive the information bits that are output by the first interleaver by column, and perform interleaving mapping on the information bits. According to the interleaver provided in embodiments of this application, information bits of a plurality of RUs using different modulation and coding schemes can be interleaved, to simplify a hardware structure of a communication apparatus.

This communication device may: determine Co OCBs on the basis of Cd DCBs related to a transport block; determine Cp PCBs on the basis of channel coding for each of the Co OCBs; and perform transmission on the basis of the Cd DCBs and the Cp PCBs. Each of the Co OCBs may include Lo non-consecutive outer code symbol groups (OCSGs) from each of the Cd DCBs, where Lo is an integer greater than 1.

A data transmission method, an apparatus, and a system are provided. An optical device of a transmitter may select one inner-code processing mode from a plurality of inner-code processing modes based on a requirement, and indicate the inner-code processing mode to an optical module of a receiver. The selected inner-code processing mode may be indicated to the receiver by using a PAD sequence, without requiring an additional resource and without changing a baud rate of a data stream. The optical device of the receiver may also detect quality of a current link, to select an inner-code processing mode that matches the quality, and feed back the inner-code processing mode to the transmitter, so that the transmitter can switch the inner-code processing mode based on an indication.

The present disclosure relates to a 5G or 6G communication system for supporting higher data transfer rates than 4G communication systems such as LTE. The present invention relates to a method performed by a transmitter in a communication system, the method comprising the steps of: determining the number of input bits; determining a base matrix on the basis of the number of input bits; determining a lifting size (Z) on the basis of at least one of the number of input bits or the base matrix; determining a parity check matrix on the basis of at least one of the base matrix and the lifting size (Z); and performing encoding on the basis of the parity check matrix and the input bits, wherein the parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to first parity bits, three cyclic permutation matrices are included in a first column block of the second submatrix, the greatest common divisor of at least one of difference values of each exponent of the cyclic permutation matrices and the lifting size (Z) is 1 or the smallest number greater than 1 among divisors of the lifting size (Z), and the at least one of the difference values of each exponent of the cyclic permutation matrices is Z / 2' (0≤i≤L), where Z = p*2' (p is an odd number, 0≤i≤L).

This invention relates to a codeword bit interleaving scheme for multi-layer transmission in a wireless communication system. The codeword bit interleaving scheme involves dividing the columns of an interleaving matrix into at least two separate column groups based on the transmission quality (e.g., SNR) of the data transmission layer (e.g., MIMO layer). Then, starting with writing information bits into the column group corresponding to the high-quality data transmission layer, the column group is filled with codeword bits. Afterwards, all column groups are merged to restore the initial column arrangement of the interleaving matrix, and codeword bits are read row by row from the interleaving matrix and mapped to modulation symbols. The modulation symbols are then mapped to the data transmission layer itself. By doing so, the information bits of the codewords can be allocated to the high-quality data transmission layer, thereby improving decoding performance.

Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device may encode one or more information bits into a plurality of polarization code sub-block outputs, identify one or more shaped bits for a first polarization code sub-block output of the plurality of polarization code sub-block outputs, and transmitting a polarization coded codeword derived from at least the first polarization code sub-block output and the second polarization code sub-block output. In some aspects, a wireless communication device may identify one or more shaped bit sub-channels, identify one or more information bit sub-channels, and transmit one or more shaped bits in the one or more shaped bit sub-channels and one or more information bits in the one or more information bit sub-channels. Numerous other aspects are described.

The invention discloses a radar signal processing method, a filtering method, a filtering circuit, a radar signal processing device, an integrated circuit and an electromagnetic wave sensor. The radar signal processing method comprises the steps that after FIR filtering is carried out on a to-be-processed signal, DFT operation is carried out to acquire target characteristic parameter data; the target characteristic parameters comprise at least one of a distance, a speed, a horizontal angle and a pitch angle; wherein the FIR filtering is configured to suppress at least one of a truncation effect and a frequency leakage existing in the DFT operation.

The embodiment of the invention relates to an internal FEC coding system and method. The invention relates to a communication system and method. According to a particular embodiment, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and internal encoding are performed on the FEC data stream to generate an internal encoded data stream. A second stage interleaving process is performed to interleave the internally encoded data stream. Other embodiments are also provided.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may encode one or more information bits into a plurality of polar code sub-block outputs, identify one or more shaping bits for a first polar code sub-block output of the plurality of polar code sub-block outputs, and transmit a polar-coded codeword derived from at least the first polar code sub-block output and the second polar code sub-block output. In some aspects, a wireless communication device may identify one or more shaping bit subchannels, identify one or more information bit subchannels, and transmit one or more shaping bits in the one or more shaping bit subchannels and one or more information bits in the one or more information bit subchannels. Numerous other aspects are described.

The invention discloses a parallel stepped convolutional code space coupling coding and decoding (PSCBCC) method and device, belongs to the technical field of channel coding, and is suitable for a large-bandwidth communication scene. According to the method, a frame of data is divided into multiple groups of sub-data, parallel convolutional coding of three paths of input of current sub-data, interleaved previous sub-data and an interleaved previous check sequence is realized by utilizing a parallel coding unit, a current check sequence is generated, and the sub-data and the check sequence are respectively reserved to different subsequent moments to form asymmetric coupling; and during decoding, a parallel decoding unit is matched with a coding structure, and a plurality of groups of log-likelihood ratios are input to realize iterative updating. The throughput rate is improved through parallel processing, the bit error rate performance is enhanced through asymmetric coupling, multi-code-rate adaptation is supported, and the performance is superior to that of existing BCC and 4G / 5G standard codes.

The present application provides an information processing method based on a coupled code, and a communication apparatus. The method comprises: dividing first information bits into C first blocks, the C first blocks having the same length; and performing coupled encoding on the basis of the C first blocks to obtain a codeword sequence, wherein a parity bit corresponding to an i-th first block among the C first blocks is obtained on the basis of information bits of the i-th first block and information bits of a first blocks, i being an integer greater than or equal to 2, a being an integer greater than or equal to 1, and C being an integer greater than or equal to 2. In the method, coupled encoding is performed on the C first blocks obtained by dividing the first information bits, thereby filling the gap for the first information bits in a coupled encoding scheme; moreover, by using the characteristics of coupled encoding, the i-th first block and the a first blocks are encoded on the basis of a coupling relationship, thereby improving the encoding and decoding performance of each first block.

A turbo code designing method for designing a turbo encoding using a high-performance interleaver is provided. A turbo encoder is provided with a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder generates a first parity stream of input data by use of a predetermined RSC encoding. The interleaver swaps an order of series inside the input data based on a first rule to generate a swapped data. The second convolutional encoder es a second parity stream of the swapped data by use of the RSC encoder. The turbo code designing method includes selecting a polynomial that indicate the RSC encoding from a Galois field of polynomials and designing the first rule of the inter leaver based on the RSC encoding.

This application discloses a data processing method and a data processing apparatus. First data processing is performed on multiple first data streams encoded with a first FEC to obtain m second data streams. Each second data stream undergoes second FEC encoding, and each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. Second data processing is performed on each of the m second data streams to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment markers, where P = N × b. Third data processing is performed on the m third data streams to obtain Y modulation symbol streams, each modulation symbol stream being modulated, and the baud rate value of each modulation symbol stream being an integer multiple of the typical Ethernet reference clock frequency value.

An LDPC code-based communication method and a communication apparatus are provided. Through row grouping and column grouping, an LDPC base matrix may be divided into a plurality of units of a same scale. The plurality of units include three types: a first unit, a second unit, and a third unit. A column weight of each column of the first unit is 1. A column weight of at least one column of the second unit is 1, and a column weight of a remaining column is 0. A column weight of each column of the third unit is 0. None of the column weights of the columns of the first unit, the second unit, and the third unit is greater than 1. Therefore, a receiver device may perform parallel decoding of a plurality of QC blocks on a codeword sequence corresponding to each unit, and a case in which decoding cannot be performed does not occur. This helps improve decoding performance.

A system (100) includes a test transmitter (102) including a pseudorandom bit sequence (PRBS) generator and a signal generation circuit. The PRBS generator is configured to generate a PRBS. The signal generation circuit is configured to generate a test signal comprising a repetition of a truncated portion of the PRBS such that a period of the repetition is shorter than a period of the PRBS.

The embodiment of the present disclosure provides a decoder, a decoding method, a memory controller and a memory system. The decoder comprises a cache module and a flip indication module. The cache module is configured to cache soft data related to a to-be-decoded codeword. The flip indication module is configured to obtain the soft data from the cache module, and use the soft data to assist in determining the number of bits in the to-be-decoded codeword that do not satisfy a check when performing hard decision decoding on the to-be-decoded codeword for the first time.

The invention discloses a method and a device for realizing radar data processing, which adopt a parallel computing architecture, perform data throughput with multiple parallelism degrees, optimize a data access mode, further improve throughput rate, improve efficiency and flexibility of data access in a radar sliding window detection process, reduce cache overhead and improve data access efficiency. High-speed, parallel and clear-structure neighborhood data extraction operation is realized, and rapid and accurate data access support is provided for target detection.