409results about "Error correction/detection using interleaving techniques" patented technology

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

The invention discloses an anti-attack interleaving method and device for communication information. The method comprises the following steps: acquiring an information sequence to be transmitted; performing statistical analysis processing on the to-be-transmitted information sequence to obtain a statistical information set; carrying out detection modeling processing on the communication channel of the information sequence to be transmitted to obtain channel dimension information; and performing interleaving parameter calculation processing on the statistical information set and the channel dimension information to obtain an interleaving parameter information set. According to the invention, the problems of anti-interference effect and influence on the security of the communication system caused by fixed parameters of the interleaving method in the current communication system are solved.

The present invention relates to a multiple application QR code capable of storing information of a plurality of applications in such a way that a respective information can be retrieved for each application in a reliable and time-efficient manner. The information is encoded into encoded data including at least a header and a respective data container per application. The header can comprise at least a single identifier indicating a presence of the plurality of applications and a respective application identifier per application. The encoded data are distributedly stored in a plurality of data pixels distributed over an encoding region of the QR code, according to an allocation rule. A QR code reader can retrieve the information stored in the QR code by only accessing and processing the data pixels associated with the respective application of interest and by using an error correction which is specific to this respective application.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

The invention provides a dual-binary Turbo decoding method based on deep learning, and belongs to the technical field of wireless communication. Comprising the following steps: generating a binary random bit stream as original information, and generating a Turbo code sequence through two recursive system convolutional code component encoders; pre-processing the Turbo code sequence, and inputting the pre-processed Turbo code sequence into a bidirectional PNN model for processing to obtain an output feature vector; based on the output feature vector, standardization is carried out through a batch normalization layer, and a decoding result probability value is output by using a full connection layer and a Sigmoid activation function; and on the basis of the decoding result probability value, a Max-Log-MAP algorithm is cascaded with a component decoder of the bidirectional RNN to obtain a decoding result.

Disclosed herein are an FFT processor, an FFT computing method, a radar signal processing system-on-chip, an integrated circuit, and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT kernels, and the FFT processor has at least two operating modes among a large-point-number FFT mode, a pipeline mode and an independent parallel mode, wherein when the FFT processor is in the large-point-number FFT mode, the two FFT kernels are configured to decompose FFT of N points into two instances of FFT; when the FFT processor is in the pipeline mode, the former FFT kernel of the two cascaded FFT kernels is configured to perform distance FFT, and the latter FFT kernel of the two cascaded FFT kernels is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT kernels are configured to independently process data of different channels in parallel.

Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit / receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

The invention relates to a bit error rate reduction method for reconfigured GPS CNAV-2 navigation message, by using the ORC-POLAR channel coding method instead of BCH and LDPC as the channel coding method to capture and correct errors caused by ambient noise.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure discloses a method and an apparatus for error correction coding in a communication system, more specifically, to error correction coding integrated with transmission diversity.

Polar codes for wireless communications are constructed to adapt to channel conditions. Input bits are encoded by a polar code to obtain a number of encoded bits, and a reduced number of the encoded bits are decoded to obtain decoded input bits. The polar code provides or includes bit indices for bit values, and the bit indices include a first set of bit indices for values of the input bits and a second set of bit indices for a predetermined bit value. Encoded bits in a subset, which includes fewer than all of the encoded bits and is for reducing the number of the encoded bits, are interleaved.

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.

An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, aiming at 39 groups of Turbo interleaving parameters supported by 4G 802.16m protocol, the method uses grouped interleaving initial address table Itab_init and fixed interleaving step Istep at each level to realize simplified calculation of interleaving address; uses grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step Dstep at each level to realize simplified calculation of deinterleaving address; uses the mapping relationship between interleaving and deinterleaving to process the interleaver and deinterleaver of Turbo iterative decoding and replace the deinterleaving table and interleaving table between iteration of component decoders. The present application reduces the calculation complexity based on the simplified Turbo decoding interleaving and deinterleaving calculation method, and replaces the interleaving and deinterleaving tables between two component encoders to realize parallel processing of interleaving and deinterleaving processing and Turbo component decoder external information calculation, which reduces the interleaving and deinterleaving delay to equivalent only one processing time slot, is irrelevant to interleaving depth, and improves the decoding rate of Turbo decoding.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

The present disclosure relates to a technical solution that improves the reliability of communications over a wireless communication channel by replacing a conventional interleaver (e.g., random interleaver) with a Neural Network (NN)-generated interleaver. For this purpose, a well-trained NN is used, which is configured to receive a UE connection status and a channel status as input data and outputs the interleaver in the form of an orthogonal binary matrix. The NN is shared by a UE and a network node. The network node may use the interleaver to interleave a set of bits in a downlink control message before the downlink control message is encoded, e.g., with an error correcting code, such as a polar code. The UE may generate and transpose the interleaver to obtain a deinterleaver to be applied to the downlink control message after its decoding (e.g., polar decoding).

Various aspects of the present disclosure relate to receiving (1502) a polar codeword comprising a set of bits and generating (1504) a permuted vector based at least in part on the polar codeword and a permutation matrix. Aspects of the disclosure may relate to determining (1506) a plurality of polar subcodes based on the permuted vector, and identifying (1508), for each polar subcode of the plurality of polar subcodes, a set of kernels, where each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns. Aspects of the disclosure may relate to decoding (1510) the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder includes one or more fast decode modules to decode a corresponding kernel of the set of kernels.

A wireless transmit / receive unit (WTRU) may receive a constellation symbol that includes indications that each are associated with a respective WTRU of a plurality of WTRUs. The WTRU may determine that a first weight associated with a first indication of the indications is different than a second weight associated with a second indication of the indications. The indications may comprise indications of bits modulated at a multi-user constellation bit division multiple access modulator (MU-CBDMAM).

A method comprising: determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.

A method for wireless communication at a UE and related apparatus are provided. In the method, the UE generates one or more CRCs for a transmission including a control payload and a data payload. The number of the one or more CRCs is based on a total size of the control payload and the data payload. The UE further provides the transmission, including the one or more CRCs, to a receiving device.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

The invention discloses an RMFE-based distributed matrix multiplication implementation method. The method comprises the following steps: initializing parameters, constructing an RMFE function, splitting a to-be-processed matrix sequence into sequence vectors, sequentially carrying out phi function operation, obtaining a matrix distributed multiplication result through distributed matrix multiplication, and recovering through psi function operation to obtain a multiplication result of a to-be-processed matrix. According to the method, a distributed multiplication problem of a plurality of matrixes on a small domain / Galois ring is converted into a distributed multiplication problem of a single matrix on a large domain / Galois ring, and the calculation overhead on an expansion domain is allocated to the plurality of matrixes, so that the communication overhead required by distributed matrix multiplication is effectively reduced; the method has important application value for a high-speed communication system.

A data processing method, an apparatus, and a device. The data processing method may be performed by a first communication device, and the first communication device is a transmit end of encoded data. When simultaneously sending one or more data streams, the first communication device places information bits in a data stream in a specified order. A plurality of data streams may be arranged in a specified order, so that joint encoding without feeding back information can be implemented, and transmission close to a channel capacity can be implemented.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

The invention provides a data processing method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of data processing.The method comprises the steps that a first index of to-be-decoded data in an index set is determined; obtaining an initial interleaving address associated with the first index; and determining an interleaving code associated with the first index based on the initial interleaving address and a preset row and column operation rule. Therefore, the interleaving code associated with the first index is calculated through the first index and the row and column operation rule, the use condition of modular operation can be reduced through row and column operation, consumption of calculation resources is avoided, efficiency can be well improved under the condition of high speed or large data flow, and in some low-power-consumption or resource-limited environments, the interleaving code associated with the first index is calculated through the interleaving code associated with the first index. Power consumption and performance requirements can be balanced, and the reliability of a communication system is improved.

The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond 4G communication systems such as Long Term Evolution (LTE). A method performed by a transmitting node in a wireless communication system may include encoding a plurality of information bits using a plurality of cyclic redundancy check (CRC) bits, interleaving the plurality of information bits and the plurality of CRC bits using an interleaving pattern, generating a codeword by convolutional encoding and polarization encoding the interleaved plurality of information bits and the interleaved plurality of CRC bits, and transmitting the codeword to a receiving node. The interleaving pattern may correspond to a matrix generated based on a size of the plurality of information bits and a size of the plurality of CRC bits.