259results about "Error correction/detection using interleaving techniques" patented technology

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

Disclosed herein are an FFT processor, an FFT computing method, a radar signal processing system-on-chip, an integrated circuit, and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT kernels, and the FFT processor has at least two operating modes among a large-point-number FFT mode, a pipeline mode and an independent parallel mode, wherein when the FFT processor is in the large-point-number FFT mode, the two FFT kernels are configured to decompose FFT of N points into two instances of FFT; when the FFT processor is in the pipeline mode, the former FFT kernel of the two cascaded FFT kernels is configured to perform distance FFT, and the latter FFT kernel of the two cascaded FFT kernels is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT kernels are configured to independently process data of different channels in parallel.

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure discloses a method and an apparatus for error correction coding in a communication system, more specifically, to error correction coding integrated with transmission diversity.

Polar codes for wireless communications are constructed to adapt to channel conditions. Input bits are encoded by a polar code to obtain a number of encoded bits, and a reduced number of the encoded bits are decoded to obtain decoded input bits. The polar code provides or includes bit indices for bit values, and the bit indices include a first set of bit indices for values of the input bits and a second set of bit indices for a predetermined bit value. Encoded bits in a subset, which includes fewer than all of the encoded bits and is for reducing the number of the encoded bits, are interleaved.

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.

An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, aiming at 39 groups of Turbo interleaving parameters supported by 4G 802.16m protocol, the method uses grouped interleaving initial address table Itab_init and fixed interleaving step Istep at each level to realize simplified calculation of interleaving address; uses grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step Dstep at each level to realize simplified calculation of deinterleaving address; uses the mapping relationship between interleaving and deinterleaving to process the interleaver and deinterleaver of Turbo iterative decoding and replace the deinterleaving table and interleaving table between iteration of component decoders. The present application reduces the calculation complexity based on the simplified Turbo decoding interleaving and deinterleaving calculation method, and replaces the interleaving and deinterleaving tables between two component encoders to realize parallel processing of interleaving and deinterleaving processing and Turbo component decoder external information calculation, which reduces the interleaving and deinterleaving delay to equivalent only one processing time slot, is irrelevant to interleaving depth, and improves the decoding rate of Turbo decoding.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

The invention discloses an RMFE-based distributed matrix multiplication implementation method. The method comprises the following steps: initializing parameters, constructing an RMFE function, splitting a to-be-processed matrix sequence into sequence vectors, sequentially carrying out phi function operation, obtaining a matrix distributed multiplication result through distributed matrix multiplication, and recovering through psi function operation to obtain a multiplication result of a to-be-processed matrix. According to the method, a distributed multiplication problem of a plurality of matrixes on a small domain / Galois ring is converted into a distributed multiplication problem of a single matrix on a large domain / Galois ring, and the calculation overhead on an expansion domain is allocated to the plurality of matrixes, so that the communication overhead required by distributed matrix multiplication is effectively reduced; the method has important application value for a high-speed communication system.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

A method and an apparatus for processing an Ethernet data stream, a computer system, a network system, and a computer-readable storage medium are disclosed. The method is applied to a receiver apparatus including a first forward error correction FEC decoder and a second FEC decoder. The method includes: obtaining transmission information of a first data stream; and if the transmission information meets a trigger condition, adjusting an error correction capability of the receiver apparatus. The data stream can be flexibly and effectively processed by using the method, the apparatus, the computer system, the network system, and the computer-readable storage medium.

Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.

The invention provides an LDPC code bit interleaving method and system for relieving pilot interference, and the method comprises the steps: carrying out the LDPC coding of a bit sequence to be transmitted, and dividing the coded bit sequence into a plurality of sub-blocks; sorting the protection capability of each sub-block; calculating a residual pilot interference power expected value of each data symbol, and dividing bits after symbol de-mapping into different interference levels; and bit interleaving is completed according to the sequence of the protection capabilities of the sub-blocks and the classification result of the interference levels of the bits, and a receiving end recovers the interleaved bit sequence to the sequence of just coding through a de-interleaver before decoding and sends the bit sequence to a decoder for decoding. According to the invention, a bit interleaving technology is designed, different protections are provided for coding bits, the bits which are seriously influenced by pilot interference are fully protected, and the pilot interference is relieved while a guard interval is not needed.

Described herein are systems and methods for encoding digital data into oligonucleotides and decoding the oligonucleotides back to digital data. The encoding and decoding schemes include inner codecs for converting digital data to bases and bases to digital data. The encoding and decoding schemes also include outer codecs that include error correction schemes.

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

The embodiment of the present application discloses a data processing method and a data processing device. The method in the embodiment of the present application includes the following steps: separately performing convolutional interleaving on n lane data streams to obtain n first data streams, where n>1, and a first FEC encoding is performed on all of the n lane data streams. All a codewords obtained by the first FEC encoding are distributed into b lane data streams, where a≦b≦n and a≧1. Each z consecutive symbols of the first data stream are from z different codewords, where z>1. Then, all K first data streams of the n first data streams are multiplexed to obtain one second data stream, and a total of m second data streams are obtained. The n first data streams include G first data stream subsets, and the symbols in different first data stream subsets are from different codewords, where m=n / K, K>1, and G>1. The y consecutive symbols in each second data stream are from y different codewords, where y>z.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

Certain aspects of the present disclosure provide a technique for wireless communication by a wireless communication device. A method includes partitioning a first set of bits into a plurality of blocks of bits. The method further includes encoding each bit block of the plurality of bit blocks to generate a plurality of encoded bit blocks. The method further includes cascading the plurality of encoded blocks of bits to generate a second set of bits. The method further includes interleaving the second set of bits to generate a third set of bits. The method further includes modulating the carrier waveform with data based on the third set of bits. The method also includes transmitting the modulated carrier waveform.

This invention discloses an encoding and decoding method for data compression transmission, comprising: at the transmitting end, inputting data u of length B*q into a sparsifier and grouping it to obtain the total number of string types m; constructing a sparsification code table of size m based on the frequency of occurrence of string types; performing sparsification mapping on data u according to the code table to obtain a sequence v of length m; interleaving it and dividing it into L groups according to each group of k bits to obtain a sequence of length Lk. v The sequence v is divided into single or multiple paths for encoding to obtain a codeword sequence c of length N. At the receiving end, the received sequence y of length N is decoded to obtain a sequence of length Lk. After deinterleaving the sequence and removing the zero-padding bits, a sequence of length Lk is obtained. After inputting the sequence into the desparser, the present invention can avoid error propagation compared with existing variable-length coding compression transmission schemes, and achieve efficient data transmission while allowing a certain degree of bit error.

Embodiments of this application disclose an interleaving method supporting unequal modulation, a subcarrier mapping method supporting unequal modulation, and a related apparatus. An interleaver includes a first interleaver and a second interleaver, the interleaver is configured to determine an order of information bits carried in a subcarrier of a first RU and a subcarrier of a second RU, and a modulation scheme of the first RU is different from a modulation scheme of the second RU. The first interleaver is configured to input information bits by row. A quantity of columns of the first interleaver is M1+M2, a quantity of rows of the first interleaver is a larger value in N1 and N2, N1 and M1 are determined based on a quantity of subcarriers of the first RU, and N2 and M2 are determined based on a quantity of subcarriers of the second RU. The second interleaver is configured to receive the information bits that are output by the first interleaver by column, and perform interleaving mapping on the information bits. According to the interleaver provided in embodiments of this application, information bits of a plurality of RUs using different modulation and coding schemes can be interleaved, to simplify a hardware structure of a communication apparatus.

This communication device may: determine Co OCBs on the basis of Cd DCBs related to a transport block; determine Cp PCBs on the basis of channel coding for each of the Co OCBs; and perform transmission on the basis of the Cd DCBs and the Cp PCBs. Each of the Co OCBs may include Lo non-consecutive outer code symbol groups (OCSGs) from each of the Cd DCBs, where Lo is an integer greater than 1.

A data transmission method, an apparatus, and a system are provided. An optical device of a transmitter may select one inner-code processing mode from a plurality of inner-code processing modes based on a requirement, and indicate the inner-code processing mode to an optical module of a receiver. The selected inner-code processing mode may be indicated to the receiver by using a PAD sequence, without requiring an additional resource and without changing a baud rate of a data stream. The optical device of the receiver may also detect quality of a current link, to select an inner-code processing mode that matches the quality, and feed back the inner-code processing mode to the transmitter, so that the transmitter can switch the inner-code processing mode based on an indication.

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

Embodiments of this application disclose a data processing method and a data processing apparatus, so that good performance of a concatenated FEC-based solution can be achieved in a scenario with a low latency. For a concatenated FEC-based transmission solution, interleaving alignment needs to be first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. In other words, each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

A method for data transfer via a communication channel (11) is provided, comprising: determining, in a first data processing unit (10), a codeword from a message using a channel code and sending the codeword via the communication channel (11), wherein the channel code comprises an outer code concatenated with an inner code; the outer code is one of a Reed-Solomon code, a folded Reed-Solomon code, a twisted Reed-Solomon code, and a generalized Reed-Solomon code; the inner code is a neural network code comprising a neural encoder-decoder pair, which includes an encoding neural network (21) and a decoding neural network (23); a nonlinear channel and / or a noisy channel (22) is arranged between the encoding neural network (21) and the decoding neural network (23); and the neural encoder-decoder pair has been adapted such that the decoding neural network (23) provides an estimated outer codeword symbol for an input outer codeword symbol by training the neural encoder-decoder pair using a training data set which comprises a plurality of outer codewords determined from a plurality of input messages by an outer code encoder (31), wherein one or more outer codeword symbols of the plurality of outer codewords are used as an input to the encoding neural network (21). Moreover, a further method and systems for data transfer via a communication channel (11) are provided.

An embodiment of the present application provides a component decoding method for a TURBO code, a decoding method for a TURBO code, and related equipment, including: receiving and demodulating data to be decoded according to a scheduling configuration to obtain decoding input data; and calculating the code rate and modulation order of the decoding input data; calculating an adjustment value for the decoding input data and a bit width shift value of a decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoding input data; adjusting the numerical value of the decoding input data by the adjustment value to obtain first decoding input data; component decoding the first decoding input data to obtain a calculation result of the decoder internal posterior probability branch metric; and shifting the calculation result of the decoder internal posterior probability branch metric by the bit width shift value to obtain a component decoding output value. The method has the beneficial effect of improving decoding performance and is applicable to the technical field of TURBO code decoding.

The present disclosure relates to a 5G or 6G communication system for supporting higher data transfer rates than 4G communication systems such as LTE. The present invention relates to a method performed by a transmitter in a communication system, the method comprising the steps of: determining the number of input bits; determining a base matrix on the basis of the number of input bits; determining a lifting size (Z) on the basis of at least one of the number of input bits or the base matrix; determining a parity check matrix on the basis of at least one of the base matrix and the lifting size (Z); and performing encoding on the basis of the parity check matrix and the input bits, wherein the parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to first parity bits, three cyclic permutation matrices are included in a first column block of the second submatrix, the greatest common divisor of at least one of difference values of each exponent of the cyclic permutation matrices and the lifting size (Z) is 1 or the smallest number greater than 1 among divisors of the lifting size (Z), and the at least one of the difference values of each exponent of the cyclic permutation matrices is Z / 2' (0≤i≤L), where Z = p*2' (p is an odd number, 0≤i≤L).