203results about "Single error correction" patented technology

The present invention relates to a multiple application QR code capable of storing information of a plurality of applications in such a way that a respective information can be retrieved for each application in a reliable and time-efficient manner. The information is encoded into encoded data including at least a header and a respective data container per application. The header can comprise at least a single identifier indicating a presence of the plurality of applications and a respective application identifier per application. The encoded data are distributedly stored in a plurality of data pixels distributed over an encoding region of the QR code, according to an allocation rule. A QR code reader can retrieve the information stored in the QR code by only accessing and processing the data pixels associated with the respective application of interest and by using an error correction which is specific to this respective application.

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

This application discloses a decoding method applicable to multiple scenarios, including metropolitan area networks, backbone networks, and data center interconnections, to meet the needs of optical transmission. The method comprises: obtaining a syndrome corresponding to each of a plurality of codewords; grouping the obtained syndromes and prioritizing each syndrome group; and selecting a syndrome for decoding based on the priority ranking results of each syndrome group. Because this decoding method does not perform the same decoding process on every codeword, it avoids the problem of traditional static decoding schemes requiring the same number of decoding operations regardless of the correctness of the codeword itself. This method enables on-demand decoding, reducing the demand for decoding resources and power consumption.

Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

Certain aspects of the present disclosure provide techniques for soft combining of polar encoded transmissions. An example method, performed at a network node, generally includes obtaining multiple codeword permutations corresponding to different payloads, wherein the different payloads comprise first payload portions that are the same and second payload portions that differ in a deterministic manner, and each codeword permutation corresponds to one of the second payload portions, processing the multiple codeword permutations to obtain the second payload portions, obtaining the first payload portions after obtaining the second payload portions, and soft combining the first payload portions.

The present application relates to improved data reliability for extreme temperature usage conditions in data storage. Systems, methods, and apparatus are related to memory devices, such as solid-state drives. In one method, data (e.g., data to be written to an SSD) is received from a host system. The received data is encoded using a first error correction code to generate first parity data. A temperature at which a memory cell of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in a memory storage device that is prone to errors at a predicted higher temperature determined based on output from an artificial neural network using sensor inputs). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cell of the storage device.

An electronic device including a Bluetooth communication unit configured to perform Bluetooth communication, this unit including a memory module containing a memory controller and a memory element equipped with at least one page (P) including at least one encoded data (E) including a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the memory controller being configured to store a user data in this page (P) by performing error correction code (ECC) calculations on this user data for providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data, if this user data has a reference binary code of an erased word (W E), the erased redundancy code (RC E) having a binary value similar to that of the reference binary code.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The embodiments of the present disclosure relate to a method and device for encoding and decoding, and a system. The method provided herein includes: obtaining a generator matrix for encoding, where the generator matrix is ​​determined based on a target parity check matrix of a Hamming code for encoding, the target parity check matrix is ​​determined based on a target function for decoding, where the target function is used to determine an extended non-all-zero row vector based on the target parity check matrix, and the target function is one of a set of predefined functions; encoding information bits by using a generator matrix, obtaining an encoded data stream, and transmitting the encoded data stream. The double extended Hamming code designed in this way has lower encoding and decoding complexity and a smaller amount of minimum code weight, and can achieve good Hamming code performance and low bit error rate.

The invention discloses a data transmission method, a data transmission device and a data transmission system, which are used for reducing error correction processing time delay in a core particle interconnection system and improving data transmission efficiency. Before a sending end sends data, processing such as ECC coding, interleaving and PAM-N coding of single-bit error correction is carried out on original data, after a receiving end receives the data, processing such as PAM-N decoding, de-interleaving and ECC decoding of single-bit error correction is carried out on the data, and the original data is recovered. According to the invention, error correction can be carried out by using a single-bit error correction technology in the core particle interconnection system, and compared with a multi-bit error correction technology or a retransmission technology, lower time delay and smaller area power consumption can be realized.

An integrated circuit includes an ECC encoder circuit configured to operate an H matrix on transmission data, to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity to detect and correct an error in the reception data. A data portion of the H matrix is divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group. The group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted.

To achieve a further low latency of LLchs.SOLUTION: A transmitting device 1 includes: a null insertion unit 17 that generates null packets with payloads null-filled when no data packets are input, an LDPC coding unit 18 that performs LDPC coding on the data packets and the null packets to generate fixed-length blocks, and an OFDM frame composition unit 19 that assigns the blocks to low latency channel carriers and modulates them using a predetermined modulation scheme to form an OFDM frame. The null packets are shorter in a size than the data packets.SELECTED DRAWING: Figure 1

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

Disclosed is an encoding method for semantic channels. According to the encoding method, a semantic codebook and synonymous mapping relationships may be obtained at first. Then, a syntactic information sequence to be transmitted may be determined. Further, a syntactic codeword from the semantic codebook corresponding to the syntactic information sequence may be determined based on the synonymous mapping relationships. Finally, the syntactic codeword may be modulated to obtain a signal vector.

This application discloses a data encoding method, an electronic device, and a storage medium, which includes the steps of: writing information bits into at least two buffer blocks, in which check bits corresponding to the information bits are stored, and two adjacent bits of data of the check bits are stored in different buffer blocks (S110); and performing LDPC encoding based on the information bits in the buffer blocks and the check bits (S120).

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

The embodiment of the present application discloses a data processing method and a data processing device. The method in the embodiment of the present application includes the following steps: separately performing convolutional interleaving on n lane data streams to obtain n first data streams, where n>1, and a first FEC encoding is performed on all of the n lane data streams. All a codewords obtained by the first FEC encoding are distributed into b lane data streams, where a≦b≦n and a≧1. Each z consecutive symbols of the first data stream are from z different codewords, where z>1. Then, all K first data streams of the n first data streams are multiplexed to obtain one second data stream, and a total of m second data streams are obtained. The n first data streams include G first data stream subsets, and the symbols in different first data stream subsets are from different codewords, where m=n / K, K>1, and G>1. The y consecutive symbols in each second data stream are from y different codewords, where y>z.

This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.

The application provides a remote control decoding device based on a Hamming code, comprising: a shift register, configured to convert acquired serial data based on a clock signal; two code table storage units, respectively configured to store preset Hamming code tables; a count comparison module, configured to intercept corresponding comparison bits based on the clock signal; and a comparator, configured to compare the comparison bits intercepted by the count comparison module with comparison bits corresponding to the serial data, and perform decoding based on preset decoding control logic in the case that a comparison result meets a preset condition, and send a decoding result to a preset instruction processing unit. The remote control decoding device based on the Hamming code does not need to occupy more hardware resources in the case that a code distance requirement is met, and has good universality and expansibility.

To obtain SNRs needed for high MCSs.SOLUTION: This disclosure relates to performing a first encoding operation on data bits of a code block to shape the amplitudes of resultant symbols such that the amplitudes have a non-uniform distribution. In some aspects, the probabilities associated with the respective amplitudes generally increase with decreasing amplitude. For example, the non-uniform distribution of the amplitudes of the symbols may be approximately Gaussian. In some aspects, the first encoding operation is or includes a prefix encoding operation having an effective coding rate greater than 0.94 and less than 1. The first encoding operation is followed by a second encoding operation that also adds redundancy but does not alter data bits themselves. In some aspects, the second encoding operation is or includes a low-density parity-check (LDPC) encoding operation associated with a coding rate greater than 5 / 6.SELECTED DRAWING: Figure 12

A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.

Reduced numbers of encoded bits obtained by encoding input bits by a polar code are incrementally output, for transmission for example. The polar code comprises bit indices for placing bit values before encoding. The bit indices include a first set of bit indices for placing values of the input bits and a second set of bit indices for placing a predetermined bit value. A first reduced number of the encoded bits start from a first starting position, and a second reduced number of the encoded bits start from a second starting position different from the first starting position. The second reduced number of the encoded bits include one or more of the encoded bits not included in the first reduced number of the encoded bits. The reduced numbers of encoded bits may be output from continuous positions, in a circular buffer for example, or may include repeated bits.

Embodiments of the invention provide a method of screening for weak bits in a memory array, comprising: storing a first set of data in a first memory array of a memory array having a first set of memory cells; at least one of applying a first bake process to the first memory array or applying a first magnetic field to the first memory array; determining whether a portion of the first set of data stored in the first memory array is changed by the first bake process or the first magnetic field; and if a first memory cell of the first set of memory cells stores the changed data, tracking an address of at least the first memory cell of the first set of memory cells, and at least one of: (1) replacing the first memory cell of the first set of memory cells storing the changed data with a corresponding memory cell in a second memory array of the memory array, and (2) discarding the first memory cell of the first set of memory cells storing the changed data.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.