283results about "Single error correction" patented technology

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Novel tools and techniques are provided for implementing an encoder capable of performing a self-correction process, and more particularly methods, systems, and apparatuses are provided for implementing an encoder capable of performing a process to correct itself during operation of the encoder. In various embodiments, the encoder includes an exciter and a sensor capable of detecting a position of the exciter and generating a signal based on the position of the exciter. The encoder can then perform one or more steps to detect at least one of a first error in an offset of the signal, a second error in a gain of the signal, or a third error in a phase of the signal as the exciter is rotating and correct the signal from the sensor based on the detection of at least one of the first error, the second error, or the third error.

The present invention relates to a multiple application QR code capable of storing information of a plurality of applications in such a way that a respective information can be retrieved for each application in a reliable and time-efficient manner. The information is encoded into encoded data including at least a header and a respective data container per application. The header can comprise at least a single identifier indicating a presence of the plurality of applications and a respective application identifier per application. The encoded data are distributedly stored in a plurality of data pixels distributed over an encoding region of the QR code, according to an allocation rule. A QR code reader can retrieve the information stored in the QR code by only accessing and processing the data pixels associated with the respective application of interest and by using an error correction which is specific to this respective application.

The invention relates to automatic stabilization of an encoder. Novel tools and techniques are provided for implementing an encoder capable of performing a self-correcting process, and more particularly, methods, systems, and apparatus are provided for implementing the encoder capable of performing a process to correct itself during operation of the encoder. In various embodiments, the encoder includes an exciter and a sensor capable of detecting a position of the exciter and generating a signal based on the position of the exciter. The encoder can then perform one or more steps to detect at least one of a first error in an offset of the signal, a second error in a gain of the signal, or a third error in a phase of the signal as the exciter rotates, and correct the signal from the sensor based on the detection of at least one of the first error, the second error, or the third error.

A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.

The invention discloses an encoder, an encoding method and a chip, relates to the technical field of encoding, and aims to overcome the technical defect that a feedback loop in the encoder cannot converge in time sequence under the scene of large-bandwidth and high-parallelism input. The encoder comprises a feed-forward module which is used for receiving data to be encoded at the parallelism degree of n symbols per beat, and calculating a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received by the current beat. The feedback module is used for receiving the single-beat polynomial which is output by the feed-forward module and corresponds to the current beat, and performing calculation in a finite field according to the single-beat polynomial which corresponds to the current beat and a first polynomial which represents symbols received by historical beats to obtain a second polynomial, and the second polynomial is used for determining a target polynomial which represents data to be coded; the target polynomial is used for generating a check sequence of the to-be-coded data, so that code words obtained after the to-be-coded data is coded in a forward error correction coding mode are obtained.

The embodiment of the present application discloses a data processing method and a data processing device. The method of the embodiment of the present application includes the following steps. Convolution interleaving is performed on n channel data streams to obtain n first data streams. Wherein, n>1, and the n channel data streams are all subjected to the first FEC encoding. Each a codeword after the first FEC encoding is distributed in b channel data streams, a≤b≤n, a≥1. The continuous z symbols in each first data stream come from z different codewords, z>1. Afterwards, each K first data stream in the n first data streams is multiplexed to obtain 1 second data stream, so as to obtain a total of m second data streams. Wherein, the n first data streams include G first data stream subsets, and the symbols in different first data stream subsets come from different codewords, m=n / K, K>1, G>1. The continuous y symbols in each second data stream come from y different codewords, y>z.

Example systems and methods for using a multi-tier error correction code distributed among oligos for DNA data storage are described. A data unit may be encoded as a set of codewords where each codeword is distributed as symbols on different oligos. The codewords may include a set of first tier codewords that include CRC and ECC redundancy data and one or more additional tiers of codewords that include permuted data and corresponding ECC redundancy data. Decoding may include a sequence of decoding iterations between the first tier of codewords and additional tiers of codewords.

This document discloses techniques, apparatuses, and systems for secure multi-rail control for sparsely encoded signals. Integrated circuits (ICs) may transmit various signals to manage interactions between circuit components of the IC. These critical signals are common targets for malicious attacks because, when altered, they can cause the IC to perform differently than is intended, and in some cases, bypass security measures. While various strategies may be used to protect against these attacks, modern circuit synthesis tools may optimize away these security measures, leaving the IC vulnerable to manipulation. In contrast, the secure multi-rail control for sparsely encoded signals described herein utilizes multiple rails to transmit sparsely encoded critical signals. Each rail may be controlled by a separate finite state machine (FSM) to reduce vulnerabilities that may arise due to circuit synthesis, provide an adjustable solution that may be leveraged differently based on implementation, and provide comportability to different ICs.

Encoding devices, methods and programs that encode with high transmission efficiency by controlling a running disparity are disclosed. In one example, an encoding device includes a scrambling circuit that scrambles an input data string, a calculation circuit that calculates a first running disparity of the scrambled data string, a determination circuit that determines whether or not to invert the scrambled data string on the basis of a first running disparity calculated by the calculation circuit and a second running disparity calculated at a time point before the first running disparity, and an addition circuit that inverts or non-inverts the scrambled data string on the basis of a determination result by the determination circuit, adds a flag indicating the determination result, and outputs the data string. The technology can be applied to devices that perform SLVS-EC standard communication.

An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m<n-k.

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

This application discloses a decoding method applicable to multiple scenarios, including metropolitan area networks, backbone networks, and data center interconnections, to meet the needs of optical transmission. The method comprises: obtaining a syndrome corresponding to each of a plurality of codewords; grouping the obtained syndromes and prioritizing each syndrome group; and selecting a syndrome for decoding based on the priority ranking results of each syndrome group. Because this decoding method does not perform the same decoding process on every codeword, it avoids the problem of traditional static decoding schemes requiring the same number of decoding operations regardless of the correctness of the codeword itself. This method enables on-demand decoding, reducing the demand for decoding resources and power consumption.

Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

Certain aspects of the present disclosure provide techniques for soft combining of polar encoded transmissions. An example method, performed at a network node, generally includes obtaining multiple codeword permutations corresponding to different payloads, wherein the different payloads comprise first payload portions that are the same and second payload portions that differ in a deterministic manner, and each codeword permutation corresponds to one of the second payload portions, processing the multiple codeword permutations to obtain the second payload portions, obtaining the first payload portions after obtaining the second payload portions, and soft combining the first payload portions.

The invention provides a data processing method and device and a communication system, and belongs to the technical field of communication. The method comprises the steps that a data sequence is acquired, and the data sequence comprises a plurality of forward error correction (FEC) code words; performing FEC decoding on at least one FEC code word in the data sequence to obtain at least one decoded code word; and finding a preset sequence in the at least one decoded code word. The bit error rate of the decoded code word is low, so that the time consumed for searching the preset sequence in the at least one decoded code word of the data sequence is short, and the efficiency, precision and reliability of searching the preset sequence in the data sequence can be improved.

To secure favorable communication quality in data transmission using an LDPC code.SOLUTION: In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, to a case of performing LDPC code-based data transmission and the like.SELECTED DRAWING: Figure 185

The present application relates to improved data reliability for extreme temperature usage conditions in data storage. Systems, methods, and apparatus are related to memory devices, such as solid-state drives. In one method, data (e.g., data to be written to an SSD) is received from a host system. The received data is encoded using a first error correction code to generate first parity data. A temperature at which a memory cell of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in a memory storage device that is prone to errors at a predicted higher temperature determined based on output from an artificial neural network using sensor inputs). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cell of the storage device.

An electronic device including a Bluetooth communication unit configured to perform Bluetooth communication, this unit including a memory module containing a memory controller and a memory element equipped with at least one page (P) including at least one encoded data (E) including a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the memory controller being configured to store a user data in this page (P) by performing error correction code (ECC) calculations on this user data for providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data, if this user data has a reference binary code of an erased word (W E), the erased redundancy code (RC E) having a binary value similar to that of the reference binary code.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The embodiments of the present disclosure relate to a method and device for encoding and decoding, and a system. The method provided herein includes: obtaining a generator matrix for encoding, where the generator matrix is ​​determined based on a target parity check matrix of a Hamming code for encoding, the target parity check matrix is ​​determined based on a target function for decoding, where the target function is used to determine an extended non-all-zero row vector based on the target parity check matrix, and the target function is one of a set of predefined functions; encoding information bits by using a generator matrix, obtaining an encoded data stream, and transmitting the encoded data stream. The double extended Hamming code designed in this way has lower encoding and decoding complexity and a smaller amount of minimum code weight, and can achieve good Hamming code performance and low bit error rate.

The invention discloses a data transmission method, a data transmission device and a data transmission system, which are used for reducing error correction processing time delay in a core particle interconnection system and improving data transmission efficiency. Before a sending end sends data, processing such as ECC coding, interleaving and PAM-N coding of single-bit error correction is carried out on original data, after a receiving end receives the data, processing such as PAM-N decoding, de-interleaving and ECC decoding of single-bit error correction is carried out on the data, and the original data is recovered. According to the invention, error correction can be carried out by using a single-bit error correction technology in the core particle interconnection system, and compared with a multi-bit error correction technology or a retransmission technology, lower time delay and smaller area power consumption can be realized.

An integrated circuit includes an ECC encoder circuit configured to operate an H matrix on transmission data, to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity to detect and correct an error in the reception data. A data portion of the H matrix is divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group. The group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted.

To achieve a further low latency of LLchs.SOLUTION: A transmitting device 1 includes: a null insertion unit 17 that generates null packets with payloads null-filled when no data packets are input, an LDPC coding unit 18 that performs LDPC coding on the data packets and the null packets to generate fixed-length blocks, and an OFDM frame composition unit 19 that assigns the blocks to low latency channel carriers and modulates them using a predetermined modulation scheme to form an OFDM frame. The null packets are shorter in a size than the data packets.SELECTED DRAWING: Figure 1

To secure favorable communication quality in data transmission using an LDPC code.SOLUTION: In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, to a case of performing LDPC code-based data transmission and the like.SELECTED DRAWING: Figure 172