673results about "Single error correction" patented technology

A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols.

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

A method for low-density parity-check (LDPC) encoding of data comprises defining a first MxN parity check matrix; generating, based on the first parity check matrix, a second parity check matrix having an MxM triangular sub-matrix; and, mapping the data into an LDPC code word based on the second parity check matrix. The method is particularly useful for data communications applications, but may also be employed in other applications such as, for example, data storage.

Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages. The delay pipeline includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.

Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of these embodiments, the applied error correction schemes include the BCH algorithm and the Hamming algorithm.

An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.

A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

A method for mapping of coded bits using a low density parity check (LDPC) code, comprises encoding information bits by using the LDPC code to generate coded bits, sorting the coded bits in accordance with degrees of variable nodes represented by a parity check matrix of the LDPC code, dividing the sorted coded bits into a plurality of groups in accordance with a using modulation scheme, and mapping the coded bits to respective modulation signal points by considering an error resistance of each of the groups and an error resistance of a corresponding one of the modulation signal points.

A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2's complementing all soft values with 0 in their location. Creating the new soft value vector. Some embodiments include a system and method that organizes an encoded codeword. The encoded codeword has several codeword bits. The method receives the encoded codeword, assigns multiple codeword bits to at least one memory address in a plurality of memory addresses, and iteratively decodes the received codeword by utilizing the plurality of memory addresses in a predetermined order. The predetermined order is based on a dimension of the received codeword.

An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

This invention relates generally to a packet recovery algorithm for real-time (live) multi-media communication over packet-switched networks, such as the Internet. Such multi-media communication includes video, audio, data or any combination thereof. More specifically, the invention comprises a forward error correction (FEC) algorithm that addresses both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred. The transmitter calculates parity packets for the rows, columns and diagonals of a block of multi-media data packets using the exclusive or (XOR) operation and communicates the parity packets along with the multi-media data packets to the receiver. The receiver uses the parity packets to recover missing multi-media data packets in the block. The FEC algorithm is designed to be able to recover long bursts of consecutive missing data packets. If some parity packets are missing, they too can be recovered using an extra single parity packet, so that they can be used to recover other missing data packets. The invention applies to both one-way real-time streaming applications and two-way real-time interactive applications, and to both wired and wireless networks. The invention retains backwards compatibility with existing standards governing FEC for professional video over IP networks.

Various embodiments of the present invention provide systems and methods for processing information. For example, a decoding system is disclosed that includes a de-interleaver. The de-interleaver is operable to receive an interleaved codeword that includes two or more reduced codewords interleaved together. Further, the de-interleaver is operable to provide a representation of the two or more reduced codewords. The systems also include a decoder that is operable to decode the two or more reduced codewords. In some instances of the aforementioned embodiments, the decoder is an LDPC decoder that is tailored to the size of one or both of the two or more reduced codewords.

An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code.

A method and apparatus perform forward error correction in a wireless communication device in a wireless communication network. Application layer forward error correction (AL-FEC) capability information is transmitted during a capabilities exchange. A set of source packets are reshaped to k equal-sized source symbols. Systematic packets for the source symbols and at least one parity packet is encoded using a single parity check (SPC) AL-FEC code on the k source symbols. A header of each encoded packet includes a parity packet indicator. The encoded packets are processed in a media access control (MAC) layer and a physical (PHY) layer for transmission.

To address the requirements described above, the present invention discloses a method, apparatus, article of manufacture, and a locking structure for supporting parity protected RAID in a clustered environment. When updating parity, the parity is locked so that other nodes cannot access or modify the parity. Accordingly, the parity is locked, read, generated, written, and unlocked by a node. An enhanced protocol may combine the lock and read functions and the write and unlock functions. Further, the SCSI RESERVE and RELEASE commands may be utilized to lock/unlock the parity data. By locking the parity in this manner, overhead is minimized and does not increase as the number of nodes increases.

A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.

An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

The present invention is intended to provide an LDPC coding scheme which is capable of efficiently implementing a high-performance and high-speed encoder and decoder of an error correcting code suitable for the field of communications such as mobile communications. As to the configuration, a Tanner graph for representing codes with variable nodes and check nodes is used to classify the individual nodes into a plurality of categories. For calculating a probability propagation in iterative decoding, weighting previously determined for each category is performed on a log-likelihood ratio (LLR) subjected to propagation.