75results about "Single error correction" patented technology

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

To achieve a further low latency of LLchs.SOLUTION: A transmitting device 1 includes: a null insertion unit 17 that generates null packets with payloads null-filled when no data packets are input, an LDPC coding unit 18 that performs LDPC coding on the data packets and the null packets to generate fixed-length blocks, and an OFDM frame composition unit 19 that assigns the blocks to low latency channel carriers and modulates them using a predetermined modulation scheme to form an OFDM frame. The null packets are shorter in a size than the data packets.SELECTED DRAWING: Figure 1

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.

To obtain SNRs needed for high MCSs.SOLUTION: This disclosure relates to performing a first encoding operation on data bits of a code block to shape the amplitudes of resultant symbols such that the amplitudes have a non-uniform distribution. In some aspects, the probabilities associated with the respective amplitudes generally increase with decreasing amplitude. For example, the non-uniform distribution of the amplitudes of the symbols may be approximately Gaussian. In some aspects, the first encoding operation is or includes a prefix encoding operation having an effective coding rate greater than 0.94 and less than 1. The first encoding operation is followed by a second encoding operation that also adds redundancy but does not alter data bits themselves. In some aspects, the second encoding operation is or includes a low-density parity-check (LDPC) encoding operation associated with a coding rate greater than 5 / 6.SELECTED DRAWING: Figure 12

A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.

Reduced numbers of encoded bits obtained by encoding input bits by a polar code are incrementally output, for transmission for example. The polar code comprises bit indices for placing bit values before encoding. The bit indices include a first set of bit indices for placing values of the input bits and a second set of bit indices for placing a predetermined bit value. A first reduced number of the encoded bits start from a first starting position, and a second reduced number of the encoded bits start from a second starting position different from the first starting position. The second reduced number of the encoded bits include one or more of the encoded bits not included in the first reduced number of the encoded bits. The reduced numbers of encoded bits may be output from continuous positions, in a circular buffer for example, or may include repeated bits.

Embodiments of the invention provide a method of screening for weak bits in a memory array, comprising: storing a first set of data in a first memory array of a memory array having a first set of memory cells; at least one of applying a first bake process to the first memory array or applying a first magnetic field to the first memory array; determining whether a portion of the first set of data stored in the first memory array is changed by the first bake process or the first magnetic field; and if a first memory cell of the first set of memory cells stores the changed data, tracking an address of at least the first memory cell of the first set of memory cells, and at least one of: (1) replacing the first memory cell of the first set of memory cells storing the changed data with a corresponding memory cell in a second memory array of the memory array, and (2) discarding the first memory cell of the first set of memory cells storing the changed data.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

A data transmission method, an apparatus, and a system are provided. An optical device of a transmitter may select one inner-code processing mode from a plurality of inner-code processing modes based on a requirement, and indicate the inner-code processing mode to an optical module of a receiver. The selected inner-code processing mode may be indicated to the receiver by using a PAD sequence, without requiring an additional resource and without changing a baud rate of a data stream. The optical device of the receiver may also detect quality of a current link, to select an inner-code processing mode that matches the quality, and feed back the inner-code processing mode to the transmitter, so that the transmitter can switch the inner-code processing mode based on an indication.

Techniques are provided for an error resistant radiation hardened memory system based on spreading of data bits among multiple random access memories (RAMs). A memory system implementing the techniques according to an embodiment includes a first plurality of RAMs configured to store data bits written to the memory system, the data bits distributed over the first plurality of RAMs. The system also includes an error correction coding (ECC) circuit configured to generate ECC codes, each of the codes associated with a unique group of the data bits. The system further includes a second plurality of RAMs configured to store bits of the ECC codes such that the bits of each ECC code are distributed over the second plurality of RAMs. The system further includes a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory system.

The reduced number of encoded bits obtained by encoding the input bits by the polar code is incrementally output, for example for transmission. The polar code includes a bit index for placing bit values prior to encoding. The bit indices include a first set of bit indices for placing values of the input bits; a second set of bit indices for placing predetermined bit values. A first reduced number of the coded bits begins from a first starting position and a second reduced number of the coded bits begins from a second starting position different from the first starting position. The second reduced number of coded bits includes one or more of the coded bits not included in the first reduced number of coded bits. For example, the reduced number of encoded bits may be output from consecutive locations in a circular buffer, or may include duplicated bits.

This application belongs to the field of communication technologies, and provides a data processing method, an apparatus, and a communication system. The method includes: obtaining a data sequence, where the data sequence includes a plurality of forward error correction (forward error correction, FEC) codewords; performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; and finding a preset sequence in the at least one decoded codeword. Because a bit error ratio of the decoded codeword is low, time consumed in searching for the preset sequence in the at least one decoded codeword in the data sequence is short, so that efficiency, precision, and reliability of searching for the preset sequence in the data sequence can be improved.

The embodiment of the invention relates to an internal FEC coding system and method. The invention relates to a communication system and method. According to a particular embodiment, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and internal encoding are performed on the FEC data stream to generate an internal encoded data stream. A second stage interleaving process is performed to interleave the internally encoded data stream. Other embodiments are also provided.

This application discloses a data processing method and a data processing apparatus. First data processing is performed on multiple first data streams encoded with a first FEC to obtain m second data streams. Each second data stream undergoes second FEC encoding, and each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. Second data processing is performed on each of the m second data streams to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment markers, where P = N × b. Third data processing is performed on the m third data streams to obtain Y modulation symbol streams, each modulation symbol stream being modulated, and the baud rate value of each modulation symbol stream being an integer multiple of the typical Ethernet reference clock frequency value.

Disclosed is an encoding method for semantic channels. According to the encoding method, a semantic codebook and synonymous mapping relationships may be obtained at first. Then, a syntactic information sequence to be transmitted may be determined. Further, a syntactic codeword from the semantic codebook corresponding to the syntactic information sequence may be determined based on the synonymous mapping relationships. Finally, the syntactic codeword may be modulated to obtain a signal vector.

A Hamming code encoding and arranging method includes: dividing an original data into N groups of to-be-encoded data and performing Hamming code encoding on the N groups of to-be-encoded data to generate N groups of encoded data; for the N groups of encoded data, extracting p-bit encoded data in each group of encoded data for successive arrangement; when the number of bits remaining in each of the N groups of encoded data is greater than or equal to p, extracting p-bit encoded data in each group of encoded data for successive arrangement; and when there is no data remaining in each of the N groups of encoded data, generating rearranged encoded data according to the arrangement; or when there are q(<p) bits remaining in each group of encoded data, extracting q-bit encoded data in each group of encoded data for successive arrangement to generate rearranged encoded data.

Non-volatile storage device comprising: a control circuit configured to connect to a plurality of bit lines, each of which is connected to a corresponding plurality of memory cells, wherein the control circuit comprises the following: a plurality of sensing amplifiers (230), each configured to read data from the memory cells connected by one or more corresponding bit lines; a plurality of sets of internal data latches (340, 342, 344, 346), each set of internal data latches (340, 342, 344, 346) being configured to store data connected to a corresponding sensing amplifier (230); and an input / output interface configured to provide data for an external data bus (334), the control circuit is set up to: to perform a read operation through each of the sensing amplifiers (230) on a plurality of memory cells; to store the results of the reading operation by each of the sensing amplifiers (230) in the corresponding set of internal data latches (340, 342, 344, 346); to compress the results of the reading operation by each of the sensing amplifiers (230) within the corresponding set of internal data latches (340, 342, 344, 346); and to transfer the compressed results of the read operation via the input / output interface to the external data bus (334); and a cache buffer (1507) which has a plurality of sets of transfer data latches, each corresponding to one of the sets of internal data latches (340, 342, 344, 346), wherein, in order to transmit the compressed results of the reading operation via the input-output interface to the external data bus (334), the control circuit is further configured to: to transfer the compressed results of the read operation from each of the sets of internal data latches (340, 342, 344, 346) to a corresponding set of transfer data latches; to compress the results of the read operation from the sets of transfer data latches into a smaller number of sets of transfer latches; and to transfer the compressed results of the read operation to the input-output interface before transferring the compressed results of the read operation to the external data bus (334).

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

A buffer for error correction in memory modules is described. In one or more implementations, a memory module (e.g., a DIMM) configured for error correction code (ECC) includes a plurality of memory chips, wherein at least one memory chip includes memory die split between a first memory subchannel and a second memory subchannel. The memory module also includes a plurality of registered clock drivers (RCDs), wherein at least one RCD is configured to handle input addresses for both the first memory subchannel and the second memory subchannel. This configuration allows for efficient use of memory resources and flexibility in memory addressing, particularly for scenarios requiring ECC functionality or when dealing with memory chips of different capacities.

This application discloses a data transmission method, a communication device, and a storage medium in the field of communication technology that can solve the problem of low error correction performance. The method, applied to a first node, includes the steps of error correction encoding a first bit sequence to obtain a second bit sequence, bit selecting the second bit sequence to obtain a third bit sequence, interleaving the third bit sequence based on a target subsequence to obtain an interleaved fourth bit sequence, where the target subsequence is a subsequence within the first bit sequence or a subsequence within the second bit sequence, and the length of the target subsequence is an integer greater than 0, and transmitting the fourth bit sequence.

A memory system and a method for operating the memory system are disclosed. A memory controller is configured to: perform first error-correcting code (ECC) encoding on a plurality of first frames of data; generate a plurality of incremental check sub-units corresponding to the plurality of first frames of data respectively; generate incremental check codewords by performing second ECC encoding on the plurality of incremental check sub-units, wherein the incremental check codewords include one or more redundant data units; perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determine a second vector of bits such that the second vector of bits is added to the first vector of bits to form a combination vector of bits, wherein the combination vector of bits is an ECC codeword with an incremental check, the value of which is pre-fixed based on at least one of the one or more redundant data units.

To ensure good communication quality in data transmission using LDPC codes. [Solution] In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups, with the (i+1)th bit group from the beginning of the LDPC code being bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code being interleaved in a predetermined order. In group-wise deinterleaving, the arrangement of the LDPC code after group-wise interleaving is restored to its original order. This technology can be applied, for example, to data transmission using LDPC codes.

A data processing method includes, for a concatenated FEC-based transmission solution, interleaving alignment that is first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. Each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. One symbol is selected from each of the v first codewords to form a bit subset.

The present invention provides a data storage device that handles errors resulting from physical defects. [Solution] The error correction code (ECC) system of the data storage device utilizes an integrated decoding scheme to correct errors in a codeword when the decoding process using a first decoding scheme fails, and uses information derived from a second decoding scheme to generate soft bit information or reliability information associated with the failed portion of the codeword. The soft bit information derived from the second decoding scheme is provided to the first decoding scheme when the first decoding scheme attempts to correct or decode the failed codeword.

Example systems and methods for DNA data storage using multi-layer error correction codes distributed among oligonucleotides are described. The data unit may be encoded as a set of codewords, where each codeword is distributed as a symbol on a different oligonucleotide. The codeword may include: a first layer codeword set, the first layer codeword set including CRC and ECC redundant data; and one or more additional layer codewords, the one or more additional layer codewords including permutation data and corresponding ECC redundancy data. The decoding may include a series of decoding iterations between the first codeword layer and the additional codeword layer.