108results about "Reed-muller codes" patented technology

Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed.

Methods, apparatuses, and systems for encoding information symbols comprising loading information symbols into a data array with n(1) rows and n(2) columns, wherein each column has ki(1) information symbols, and wherein k(1) is an array that has at least two different values, encoding each column with a code Ci(1) from a family of nested codes C(1), wherein C(1) includes two different nested codes, and encoding each row with a code C(2).

A method decodes a soft-input cost function for an error-correcting code. First, the code is selected and its FSTFG representation is constructed. The representation is simplified, and an encoding method consistent with the representation is selected. A set of message-update and belief-update rules are selected. Messages are initialized according to a soft-input cost function. An iterative decoding cycle is then begun. The first step updates the messages according to the pre-selected message-update rules. The second step determines a trial code word from the messages, the pre-selected message-update rules, and the encoding method. The third step replaces a tentative output code word of the decoding method with the trial code word if the trial code word has lower cost. The decoding cycle terminates if a termination condition is true, and outputs the tentative code word.

A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the decoder. Each element in the active register can take three states, representing the two possible states of the corresponding bit in the word, and a third state representing uncertainty. Votes from parity checks to elements of the active register are determined from parity checks in the matrix, and the current state of the active register. A recommendation and strength of recommendation for each element in the active register is determined from the votes. The elements in the active register are then updated by comparing the recommendation and strength of recommendation with two thresholds, and the state of the corresponding bit in the received word. When termination conditions are satisfied, the decoder outputs the state of the active register. If the decoder outputs a state of the active register that does not correspond to a codeword, a new representation for the code using a parity check matrix with substantially more rows is chosen, and the decoding cycle is restarted.

A system that facilitates efficient code construction comprises a component that receives a first code and a transformation component that transforms the first code to a new code. The new code has essentially same length parameters as the first code but is hidden to a computationally bounded adversary. The first code can be designed in the noise model and appear random to a computationally bounded adversary upon transformation.

A method of encoding for optical transmission of information includes encoding information with a generalized low-density parity-check (GLDPC) code for providing coding gains, and constructing the GLDPC code with a Reed-Muller RM code as a component code, the component code being decodable using a maximum posterior probability (MAP) decoding. In a preferred embodiment, the GLDPC code includes a codeword length of substantially 4096, an information word length of substantially 3201, a lower-bound on minimum distance of substantially greater than or equal to 16, a code rate of substantially 0.78 and the RM component code includes an order of substantially 4 and an r parameter of substantially 6.

A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

Methods and systems for transmitting and receiving data include reverse concatenated encoding and decoding. Reverse concatenated decoding includes inner decoding the encoded stream with an inner decoder that uses a low-complexity linear-block code to produce an inner-decoder output stream, outer decoding the inner-decoder output stream with an outer decoder that uses a low-density parity-check code to produce an information stream, and iterating extrinsic bit reliabilities from the outer decoding for use in subsequent inner decoding to improve decoding performance.

An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P−(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.

A method of operating a wireless communication terminal includes receiving one or more downlink control messages that each contain scheduling information scheduling the wireless terminal to receive a downlink transmission on either a primary carrier or a secondary carrier. The method also includes determining, for each of the downlink control messages, whether that message includes scheduling information for the primary carrier or for a secondary carrier. Additionally, the method includes selecting a format for an uplink control message based on whether any of the downlink control messages includes scheduling information for a secondary carrier, generating an uplink control message based on the selected format, and transmitting the uplink control message to the base station.