58results about "Non-binary linear block codes" patented technology

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Error correcting codes of any distance (including codes of distance greater than four) use only exclusive OR (XOR) operations. Any code over a finite field of characteristic two are converted into a code whose encoding and correcting algorithms involve only XORs of words (and loading and storing of the data). Thus, the implementation of the encoding and correcting algorithms is more efficient, since it uses only XORs of words—an operation which is available on almost all microprocessors. An important code, the (3, 3) code of distance four, is also described.

The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M−2 of the array each have n–p data storage devices and p parity storage devices. Row M−1 of the array has n−(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.

A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the decoder. Each element in the active register can take three states, representing the two possible states of the corresponding bit in the word, and a third state representing uncertainty. Votes from parity checks to elements of the active register are determined from parity checks in the matrix, and the current state of the active register. A recommendation and strength of recommendation for each element in the active register is determined from the votes. The elements in the active register are then updated by comparing the recommendation and strength of recommendation with two thresholds, and the state of the corresponding bit in the received word. When termination conditions are satisfied, the decoder outputs the state of the active register. If the decoder outputs a state of the active register that does not correspond to a codeword, a new representation for the code using a parity check matrix with substantially more rows is chosen, and the decoding cycle is restarted.

Embodiments of the present invention include ECC-based encoding-and-decoding schemes that are well suited for correcting phased bursts of errors or erasures as well as additional symbol errors and bit errors. Each encoding-and-decoding scheme that represents an embodiment of the present invention is constructed from two or more component error-correcting codes and a mapping function ƒ(). The composite error-correcting codes that represent embodiments of the present invention can correct longer phased bursts or a greater number of erasures in addition to single-bit errors and symbol errors, respectively, than either of the component codes alone, and are more efficient than previously developed ECC-based encoding-and-decoding schemes for correcting phased bursts of symbol errors and erasures combined with additional bit errors and symbol errors.

Disclosed is an apparatus for recovering data in the case of single or double failures of N partial data blocks generated by dividing the data where N is a natural number greater than 1. The apparatus recovers the data on the basis of a Galois field product computation table including first and second search key data, and products of the first and second search key data. The first search key data includes possible symbol values. The second search key data includes a weighting value set and an inversed weighting value set. The weighting value set includes weighting values each assigned to one of the N partial data blocks and different from each other, and is closed under addition in the Galois field. The inversed weighting value set includes multiplicative inverses of the weighting values included in the weighting value set.

An apparatus for polar coding includes an encoder circuit that implements a transformation c=u1N-sBN-s{tilde over (M)}n, where u1N-s, BN-s, {tilde over (M)}n, and C are defined over a Galois field GF(2k), k>1, N=2k, s<N, u1N-s=(u1, . . . , uN-s) is an input vector of N-s symbols over GF(2k), BN-s is a permutation matrix, {tilde over (M)}n=((N−s) rows of Mn=), the matrix M1 is a pre-defined matrix of size q×q, 2<q, N=qn and n≥1, and C is a codeword vector of N-s symbols. A decoding complexity of C is proportional to a number of symbols in C. The apparatus further includes a transmitter circuit that transmits codeword C over a transmission channel.

The application relates to the technical field of communications, and discloses an encoding method and an encoding device for a Polar code for improving reliability calculating and ranking accuracy ofa polarization channel. The method comprises the steps of: acquiring a first sequence for encoding K bits to be coded, wherein the first sequence contains sequence numbers of N polarization channels,the sequence numbers of the N polarization channels are arranged based on the reliability of the N polarization channels in the first sequence, K is a positive integer, N is the mother code length ofthe Polar code and is a positive integer power of 2, and K is not greater than N; selecting sequence numbers of K polarization channels from the first sequence according to the order of reliability from high to low; placing the bits to be coded according to the selected K polarization channel numbers, and performing Polar code encoding on the bits to be coded.

An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number<n) and n2 subframes (n2 is a natural number which satisfies n1+n2=n), block-codes the n1 subframes for every m1 subframes (m1 is a factor of n1) so as to generate a first error correction code, and block-codes the n2 subframes for every m2 subframes (m2 is a factor of n2) so as to generate a second error correction code.

New capabilities will allow conventional broadcast transmission to be available to mobile devices. A method is described including the steps of receiving a packet of data having a data payload and a header, byte code encoding the data in the packet, and altering information in the header in response to the byte code encoding. An apparatus is described including an encoder receiving a packet of data and encoding the data using a byte code encoding process and a header modifier altering information in the header in response to the byte code encoding. A decoding apparatus is described including a packet identifier receiving a plurality of data packets, and identifying a data packet based on information in the header, a byte code decoder decoding the identified data packet using a byte code decoding process, and a Reed-Solomon decoder decoding at least the decoded identified data packet using a Reed-Solomon decoding process.

Embodiments of the present invention include ECC-based encoding-and-decoding schemes that are well suited for correcting phased bursts of errors or erasures as well as additional symbol errors and bit errors. Each encoding-and-decoding scheme that represents an embodiment of the present invention is constructed from two or more component error-correcting codes and a mapping function f (). The composite error-correcting codes that represent embodiments of the present invention can correct longer phased bursts or a greater number of erasures in addition to single-bit errors and symbol errors, respectively, than either of the component codes alone, and are more efficient than previously developed ECC-based encoding-and-decoding schemes for correcting phased bursts of symbol errors and erasures combined with additional bit errors and symbol errors.