238results about "Other decoding techniques" patented technology

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.

The invention relates to the technical field of wireless communication, and discloses an adaptive LDPC code coding method, system and device based on evaporation waveguide field intensity distribution, and a medium, and the method comprises the steps: obtaining the evaporation waveguide field intensity distribution in real time, and generating a field intensity distribution diagram; calculating a channel state parameter, and dynamically selecting a low-density parity check code rate according to the channel state parameter information; dynamic low-density parity check coding is adopted, and a sparse structure is adjusted through a check matrix, so that real-time switching of multi-code-rate low-density parity check codes is carried out; and a receiving end carries out decoding by adopting an NW-RBP decoding algorithm, defines a node updating rule, and dynamically schedules a node updating sequence through a residual error. According to the method, the bit error rate under a complex channel is reduced, and meanwhile, the reliable transmission efficiency of system data is improved.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

While the error correction capability can be altered by changing the redundancy level, requiring different error correction circuits to achieve this increases the circuit size. [Solution] The communication system according to the disclosed technology comprises a transmitting device having an error correction code generation unit and a receiving device having an error correction unit. The error correction code generation unit selects a k-bit data signal, generates an encoded signal by adding (mk) bits of fixed-value signals to the data signal, and generates an n-bit parity signal from the encoded signal. The transmitting device transmits the data signal and the parity signal to the receiving device. The receiving device receives a k-bit received data signal corresponding to the data signal and an n-bit received parity signal corresponding to the parity signal. The error correction unit performs error correction on the error-correction target signal, which consists of the received data signal, the (mk) bits of fixed-value signals, and the received parity signal.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The embodiment of the application discloses a kind of digital isolator and digital signal transmission method, the technical scheme of the embodiment of the application is by encoding circuit the rising edge and the falling edge of input digital signal are encoded into first pulse sequence and second pulse sequence respectively, by including multiple first pulse groups with time interval being first length characterizing first pulse sequence, multiple second pulse groups with time interval being second length characterizing second pulse sequence, so that more information is added in encoding signal, and the corresponding encoding information of rising edge and falling edge is transmitted through isolating element, while realizing the encoding and transmission of input digital signal, the anti-interference ability of encoding information and the anti-interference performance of digital isolator are improved.

This invention provides a Viterbi decoding method, apparatus, electronic device, and storage medium. The method includes: calculating the distance between a received codeword and a desired codeword at the same time to obtain a branch metric value at the current time; determining a surviving path metric value at the current time based on the branch metric value, thereby determining surviving path information; setting a deletion threshold; filtering the surviving path metric value at the current time based on the deletion threshold to obtain the minimum surviving path metric value; and, when the decoding time reaches the backtracking depth, starting from the state corresponding to the minimum surviving path metric value at the current decoding time, starting backtracking based on the surviving path information to output the corresponding decoding result. Thus, the setting of the deletion threshold achieves effective filtering of surviving paths, effectively reducing the computational load in the decoding process, and simultaneously achieving high-speed, low-power efficient decoding under any signal-to-noise ratio conditions.

The invention discloses a high-performance flexible multi-user parallel Viterbi decoder and a decoding method thereof, and the decoder comprises an input scheduler module which is used for receiving an input data stream and segmenting and scheduling the data stream to a plurality of parallel decoding cores; each decoding core adopts a bidirectional folding sliding block type structure and is used for independently executing Viterbi decoding operation, and the bidirectional folding sliding block type structure is used for synchronously pushing forward decoding operation and backward decoding operation in a single sliding window; the output collector module is used for collecting and recombining decoding results output by the decoding cores; wherein the plurality of decoding cores can be dynamically divided into one or more decoding groups, and each decoding group is used for independently processing one data stream, so that parallel accelerated decoding of a single high-speed data stream or concurrent decoding of multiple paths of independent data streams is realized. The method has the advantages of low delay, high throughput rate and high flexibility, and adapts to diversified communication protocol and data rate requirements.

A method for encoding data includes: selecting a sequence of pivot candidate positions from a sequence of g encoded vectors to encode blocks of g data symbols in a round of encoding by the following steps: providing a set of g pivot candidate positions; selecting pivot candidate positions for the sequence from the set of pivot candidate positions; removing the selected pivot candidate positions from the set of pivot candidate positions; and repeating until the set of pivot candidate positions is empty and the sequence of selected pivot candidate positions in the round is non-linear. A set of encoded vectors is generated based on the sequence of selected pivot candidate positions, each encoded vector including zero-valued coefficients at positions within the encoded vector preceding the pivot candidate positions and non-zero-valued coefficients at least at the pivot candidate positions.

Disclosed in the present application are a sphere decoding detection method and apparatus, and an electronic device and a readable storage medium. The method comprises: performing orthogonal triangular QR decomposition on a channel response matrix, so as to obtain a Q matrix and an R matrix, wherein columns in the Q matrix are arranged according to the magnitude of channel energy; according to the Q matrix and the R matrix, determining a target equalization signal; executing an ML path search process according to the target equalization signal, so as to select N branches with the minimum metric as survivor paths; performing an ML complement path search on the survivor paths, so as to obtain ML complement paths; and using the survivor path with the minimum metric as an ML path, and obtaining likelihood ratio information of each bit of each symbol of each layer according to the ML path and the ML complement paths.

A method and an apparatus for processing an Ethernet data stream, a computer system, a network system, and a computer-readable storage medium are disclosed. The method is applied to a receiver apparatus including a first forward error correction FEC decoder and a second FEC decoder. The method includes: obtaining transmission information of a first data stream; and if the transmission information meets a trigger condition, adjusting an error correction capability of the receiver apparatus. The data stream can be flexibly and effectively processed by using the method, the apparatus, the computer system, the network system, and the computer-readable storage medium.

Various aspects of the present disclosure generally relate to wireless communication, and to supporting physical broadcast channel (PBCH) scrambling and soft combining that supports larger synchronization signal block (SSB) periodicity. For example, a network node may transmit multiple SSBs in accordance with an SSB periodicity. The SSBs respectively include multiple PBCHs, and the PBCHs respectively include multiple master information blocks (MIBs) in accordance with an MIB periodicity. Each of the PBCHs includes a respective scrambled portion and a respective unscrambled portion. The unscrambled portions each include timing information in accordance with the SSB periodicity and the MIB periodicity. The UE decodes the PBCHs by soft combining the PBCHs in accordance with the timing information and descrambles resulting scrambled PBCH payloads in accordance with scrambling sequences associated with the unscrambled portions.

Acceleration of S-polarized ECC throughput by a scheduler is disclosed. A method of simplified successive cancellation list (SSCL) error decoding of an S-polar code includes representing an S-polar code as a perfect binary tree; providing a node v with a soft information vector from a parent node of v to compute a soft information vector for a left child node of v; providing v with a hard decision vector from the left child node and using it with to create a soft information vector and pass it to a right child node of v; providing v with a hard decision vector from its right child node and using it with to create a hard decision vector β v and pass it to its parent node; when v is an i-th leaf node of the perfect tree, updating two path metrics and selecting a path obtained by extending a current path by the lowest path metric.

A high-speed parallel GRAND-CRC decoding method for functional safety communication is presented. M A round-robin noise error mode allocation scheme for each memory cell, without affecting error correction performance, provides... N The system adds an all-zero error mode to the set E of noise error modes and allocates noise error modes to each memory unit in turn. A high-speed parallel decoder architecture design scheme for GRAND-CRC is proposed, including a distributed memory design strategy and the advantage of unrestricted parallelism. The parallelism can be easily set according to hardware resources, and the decoder throughput increases linearly with the parallelism. The system uses a corrector as the basis for logical judgment, and the corrector signal processing unit triggers the correct decoding output. Its features include different processing methods in three cases, especially when contention occurs, selecting the guessed sequence corresponding to the corrector with the smallest sequence number as the decoding output.

A multi-stage decoding algorithm for improving the decoding performance of bits encoded with a linear error-correcting block code of small or medium block length is provided. The algorithm comprises an input stage, at least two intermediate stages and an output stage. For each of the stages (except for the last intermediate stage and the output stage), a certain number of bit positions is selected and set to a maximum possible absolute LLR value. The output data of each stage is used to compute the input data of the next stage. Each of the intermediate stages executes a specified number of parallel decoding runs, and the input data for each of the intermediate stages is generated based on the output data of the previous intermediate stage and initial LLRs obtained after demodulation. The bit positions set to the maximum possible absolute LLR value in the previous stage cannot be used again in the next stage. At the output stage, only one decoding run is executed, for which input data are formed based on the initial LLRs and the LLRs obtained at the last intermediate stage.

The present application relates to multi-candidate successive cancellation list (SCL) decoding of polar codes. In an example, an apparatus processes multiple candidate codewords using a same SCL decoder. The SCL decoder may be cyclic redundancy code (CRC)-aided. The multiple candidate codewords may have different code configurations and / or different inputs. In an example, the multiple candidate codewords are packaged so that at most one of the candidate codewords in the package is valid.

Techniques are described herein for iterative decoding. An example method can include iteratively decoding a codeword by at least: determining soft channel reliability information values for bits of the codeword in a decoding iteration k, sorting the soft channel reliability information values, generating soft extrinsic information for the codeword based on a belief-propagation technique wherein the soft extrinsic information is based on the sorted channel reliability information values, and passing the soft extrinsic information to a decoding iteration k+1, such that soft channel reliability information for the decoding iteration k+1 is updated based on the soft extrinsic information for the codeword. The method can further include determining whether iteratively decoding the codeword is successful based on the updated soft channel reliability information, wherein the codeword was generated using a Reed-Muller encoding technique.

The syndrome calculation method disclosed in this invention includes: receiving two consecutive reference signal codewords; each reference signal codeword includes T data blocks, and the data bit width of each data block is divided into T×n corresponding data groups, each data group including symbol elements; performing a first calculation process on the multiple data groups with corresponding finite field elements to obtain multiple first calculation results, the multiple first calculation results corresponding one-to-one with the multiple data groups; taking the Tth data block of the previous reference signal codeword as the first termination position, obtaining a first set of syndromes based on the T×n first calculation results corresponding to the previous reference signal codeword; iteratively processing the first set of syndromes and the multiple first calculation results to obtain T×n sets of syndromes corresponding to the two reference signal codewords. This invention can accelerate the calculation of syndromes and reduce the search time.

An operating method of a modem chip includes receiving a first Euclidean distance (ED) set including an ED of first symbol vector candidates, comparing magnitudes of the EDs of the first ED set, calculating each of a first minimum ED corresponding to a bit value of a first bit being 1 and a second minimum ED corresponding to the bit value of the first bit being 0, the first bit being from among a plurality of bits of a plurality of layers of the transmission symbol, based on first index information including results of the comparing the magnitudes of the EDs of the first ED set, updating the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively, and detecting the transmission symbol based on the updated first minimum ED and the updated second minimum ED.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

Described herein are systems and methods for encoding digital data into oligonucleotides and decoding the oligonucleotides back to digital data. The encoding and decoding schemes include inner codecs for converting digital data to bases and bases to digital data. The encoding and decoding schemes also include outer codecs that include error correction schemes.

In an example, a decoder comprises a first processing circuit configured to: obtain a check expression and a check expression weight based on a codeword to be decoded in a current iteration and a check matrix; a second processing circuit configured to: obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration; a processor configured to: determine a flipping threshold in the current iteration based on a changing state of the check expression weight; and a bit flipping circuit configured to: output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

The application provides a cache-restricted LT code degree distribution optimization method based on reinforcement learning, comprising the following steps: S1, generating a source symbol sequence with a length of k; S2, constructing a reinforcement learning agent for determining a degree distribution of a transmitting end, the reinforcement learning agent is composed of a 2-node input layer, a 2k-node hidden layer and a k-node output layer; S3, updating a current degree value through the reinforcement learning agent, and performing LT coding on the degree value and the source symbol by an encoder to obtain a coded symbol and send the coded symbol to a receiving end decoder; S4, judging the degree value of the received coded symbol according to the currently recovered source symbol by the decoder, and performing a cache or decoding according to the degree value; S5, training the reinforcement learning agent by using the reinforcement learning environment in step S3, and finally obtaining a degree distribution that makes the reward tend to be maximum through iterative training. The application can obtain a degree distribution with smaller redundancy overhead required for full recovery under the condition of cache restriction.