705results about "Other decoding techniques" patented technology

An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

This application provides a rate matching method and a communication apparatus. A transmit end punctures an LDPC codeword based on a priority order of check bits of a mother code of an LDPC code. The priority order of the check bits of the mother code indicates a priority order of puncturing the check bits in a rate matching process, and the priority order is related to confidences of the check bits. The confidences of the check bits indicate degrees to which the check bits are affected by noise in a channel transmission process. In addition, puncturing the check bits can ensure restorability of a system variable node, and a check bit with a higher confidence is more likely to be correctly restored, so that more valid information can be provided for another system variable node during decoding iteration.

Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

Certain aspects of the present disclosure provide data compression and channel coding techniques for variable length payloads. A method performed at a wireless node may include obtaining a payload for transmission, compressing the payload using a variable length compression technique to obtain a compressed payload having compressed payload bits of a first length, adding padding bits to the compressed payload to obtain a padded compressed payload. The padded compressed payload comprises information bits including the compressed payload bits and the padding bits. The method further includes encoding the padded compressed payload and outputting the encoded padded compressed payload.

The invention provides an LDPC (Low Density Parity Check) decoding method based on a node reliability dynamic correction criterion. The LDPC decoding method comprises the following steps: step 1, initializing channel information; step 2, judging whether the maximum number of iterations is reached or not, if so, outputting a result, otherwise, entering step 3; 3, calculating extrinsic information from the check node to the variable node; 4, calculating extrinsic information from the variable node to the check node; 5, adjusting the correction factor according to the matching condition of the variable node symbol and the last iteration symbol; 6, if the correction factor exceeds the threshold value, limiting the correction factor to be the threshold value, otherwise, continuing the next step; 7, multiplying the correction factor by the variable node information, and adjusting the weight of the node information; 8, calculating full information of the variable nodes and performing hard decision; step 9, checking whether the judgment result meets the condition that the checksum is zero or not, if so, outputting a decoding result, otherwise, continuing iteration; and step 10, if the condition is not met, entering a next round of iteration, and updating check node information.

The invention provides a belief propagation LDPC decoding method and device based on deep learning, a medium and a program product. The method comprises the following steps: acquiring an LDPC code training sample set corresponding to a check matrix H; according to the check matrix H, determining a weight matrix and an activation function of each layer of a deep learning decoding model; based on the weight matrix and the activation function, using a belief propagation algorithm to establish a deep learning decoding model; training the deep learning decoding model by using the training sample set, and storing the trained deep learning decoding model as a decoder; and sending the LDPC code soft information which is corresponding to the check matrix H and needs to be decoded into the decoder to complete LDPC decoding. According to the method, iterative operation is completed by using deep learning in the error correction decoding process, the number of decoding iterations is reduced, and the sequence sent by the sending end is restored from the sequence containing noise and interference, so that the problem of decoding error codes caused by noise and other interference factors is solved.

An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.

There is described an improved method of ordered statistics decoding where a decoder generates a sparse matrix having a rank of r based on input stabilizer data and error probability weights. The sparse matrix includes a first sub-matrix defined as the r linearly independent columns of the sparse matrix. A transformation matrix, having the same size as the first sub-matrix, is initialized and updated with one or more linear transformations generated based on a transformation vector determined as a dot product of the transformation matrix and a non-zero column of the sparse matrix. An estimated error, which can be utilized to perform error correction, is determined based on the updated transformation matrix.

Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.

The disclosure relates to generating a polar code and also to encoding and decoding data using a polar code. A method of generating a polar code includes obtaining a first matrix as an m-fold Kronecker product of a 2x2 binary lower triangular matrix where m = log2(M / 2), M<N, and N is the length of a polar code to be generated. A second matrix may be obtained, where the inverse of the second matrix is a lower triangular band matrix. A transformation matrix may be generated for the polar code by calculating a Kronecker product of the second matrix with the first matrix. An information set I identifying reliable bit channels for the polar code may be determined. A polar codeword of length N may be obtained using the polar code that is decodable by iteratively applying a sliding decoding window of length M to the polar codeword, where M<N.

The invention discloses a soft decoding method and device, a medium and a product, and relates to the technical field of error correction coding, and the method is applied to a low-density parity check code, and comprises the steps: obtaining a target low-density parity check code with an information node and a check node containing an erasure bit; and allocating a preset non-zero log-likelihood ratio to the erasure bit on the check node, and executing first soft decoding. And if the first soft decoding fails, judging whether to carry out second soft decoding or not based on the weight of the syndrome generated by the first soft decoding and the number of the erasure bits on the information node. If it is judged that the second soft decoding needs to be carried out, a preset non-zero log likelihood ratio is distributed to the erasure bit located on the information node, and the second soft decoding is carried out. According to the method and the device, the erasing bits on different nodes are conditionally processed in stages, so that the success rate and the efficiency of decoding are effectively improved.

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

To provide an error correction method capable of suppressing an increase in processing delay and power consumption while maintaining correction capability.SOLUTION: An error correction method of the present invention extracts a predetermined number of correction candidate bits to be subject to error correction decoding based on likelihood information generated for each bit of encoded data before error correction, and performs error correction decoding processing on the extracted correction candidate bits. When the correction candidate bits are extracted, a plurality of low likelihood value data groups having different likelihood values that are equal to or less than a predetermined threshold are searched for, and the predetermined number of correction candidate bits are extracted.SELECTED DRAWING: Figure 6

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A quantum error correcting code with dynamically generated logical qubits is provided. When viewed as a subsystem code, the code has no logical qubits. Nevertheless, the measurement patterns generate logical qubits, allowing the code to act as a fault-tolerant quantum memory. Each measurement can be a two-qubit Pauli measurement.

A method according to one embodiment of the present specification comprises the steps of: generating a signal on the basis of a cyclic redundancy check (CRC); and transmitting the signal. The plurality of chips related to the signal include i) chips related to the CRC and ii) one or more chips related to padding.

Methods, systems, and devices for wireless communications are described. In some cases, a first wireless device may communicate, with a second wireless device, a control signal indicating a systematic polar code configuration, the systematic polar code configuration indicating for the first wireless device to perform systematic polar encoding on a first set of bits associated with a non-uniform bit distribution. As such, the first wireless device may apply a systematic polar code to the first set of bits to generate a systematic polar codeword based on the systematic polar code configuration. In such cases, the systematic polar codeword may include a set of parity bits and a set of systematic bits. Thus, the first wireless device may transmit at least the set of parity bits of the systematic polar code.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

At least one example embodiment provides a radio access network element comprising at least one processor and at least one memory. The at least one memory stores instructions that, when executed by the at least one processor, cause the radio access network element to: extract sign information from a plurality of log-likelihood ratio (LLR) sample values included in LLR data in a resource block group (RBG); convert negative LLR sample values, from among the plurality of LLR sample values, into positive integer values to obtain converted LLR data; generate compressed LLR data based on the converted LLR data; and output the compressed LLR data.

Methods and apparatus for replication of data in storage networks. In an embodiment, a processing module(s) of a computing device identifies a first storage set and a second storage set for replicated storage of data. The processing module(s) maintains a synchronization log for the first storage set and the second storage set. After initiating storage of a data object in the first storage set and the second storage set, the processing module(s) detects an unavailability of one or more storage units of the second storage set. In response to detecting a return to availability of the one or more storage units, the processing module(s) determines, based on the synchronization log, that the second storage set requires at least a portion of the data object to maintain synchronization with the first storage set, and facilitates storage of the at least a portion of the data object in the second storage set.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.

Methods and devices are provided in which a channel encoded with a polarization-adjusted convolutional (PAC) code is received. A decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input. A sub-tree of the node remains unprocessed.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Systems and methods for processing bit-interleaved coded modulation (BICM) signals from a BICM transmitter to generate information bit estimates of information in the BICM signals, including a decoder to generate the information bit estimates of the information in the received BICM signals and a symbol a posteriori probability (APP) generator to generate first symbol a posteriori probabilities (APPs) by processing the BICM signals based on Euclidean distances derived from the BICM signals, and further based on symbol probability log-likelihood ratios (SPLLRs) provided to the symbol APP generator by an extrinsic-information-based symbol probability log-likelihood ratio (SPLLR) generator. The SPLLR generator generates the SPLLRs directly from extrinsic information based on updated symbol APPs output from the decoder, without converting the extrinsic information into log-likelihoods (LLs), and the decoder generates the information bit estimates based on the first symbol APPs output from the symbol APP generator.

The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.

This application discloses a decoding method applicable to multiple scenarios, including metropolitan area networks, backbone networks, and data center interconnections, to meet the needs of optical transmission. The method comprises: obtaining a syndrome corresponding to each of a plurality of codewords; grouping the obtained syndromes and prioritizing each syndrome group; and selecting a syndrome for decoding based on the priority ranking results of each syndrome group. Because this decoding method does not perform the same decoding process on every codeword, it avoids the problem of traditional static decoding schemes requiring the same number of decoding operations regardless of the correctness of the codeword itself. This method enables on-demand decoding, reducing the demand for decoding resources and power consumption.

We disclose a soft-detection variant of Guessing Random Additive Noise Decoding (GRAND) called discretized soft-information for GRAND (DSGRAND) that can efficiently decode any moderate redundancy block-code in an algorithm that is suitable for highly parallelized implementation in hardware. DSGRAND provides near maximum likelihood decoding performance when provided with five or more bits of soft information per received bit, by discretizing the soft information into noise effect sequences and allocating those sequences into bins according to weight. The use of these bins provides a separate, simplified manner of sequencing noise guessing.