330results about "Other decoding techniques" patented technology

The invention belongs to the technical field of communication, and particularly relates to a multiplication active code decoding method based on an SO-ORBGRAND decoder. The SO-ORBGRAND decoder outputs soft information by calculating a correct posterior probability of a conjecture code word sequence, and high-performance decoding is realized through soft information exchange and optimization processing between the row decoder and the column decoder. In the iteration process, a method for judging the validity of the code word through the check matrix is designed by utilizing the polarization characteristic of the multiplication active code, so that the iteration is supported to jump out in advance to reduce the complexity. The invention provides a multiplication active code decoding algorithm based on an SO-ORBGRAND decoder, and compared with various non-system multiplication active code decoding algorithms and the performance of traditional long-code polarization codes, the method has remarkable advantages in error correction performance; a method for judging the validity of the code word through the check matrix by utilizing the polarization characteristic design of the multiplication positive code is provided, the complexity is reduced while the judgment success rate is improved, and the implementation overhead is reduced.

Certain aspects of the present disclosure provide data compression and channel coding techniques for variable length payloads. A method performed at a wireless node may include obtaining a payload for transmission, compressing the payload using a variable length compression technique to obtain a compressed payload having compressed payload bits of a first length, adding padding bits to the compressed payload to obtain a padded compressed payload. The padded compressed payload comprises information bits including the compressed payload bits and the padding bits. The method further includes encoding the padded compressed payload and outputting the encoded padded compressed payload.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A method according to one embodiment of the present specification comprises the steps of: generating a signal on the basis of a cyclic redundancy check (CRC); and transmitting the signal. The plurality of chips related to the signal include i) chips related to the CRC and ii) one or more chips related to padding.

Methods, systems, and devices for wireless communications are described. In some cases, a first wireless device may communicate, with a second wireless device, a control signal indicating a systematic polar code configuration, the systematic polar code configuration indicating for the first wireless device to perform systematic polar encoding on a first set of bits associated with a non-uniform bit distribution. As such, the first wireless device may apply a systematic polar code to the first set of bits to generate a systematic polar codeword based on the systematic polar code configuration. In such cases, the systematic polar codeword may include a set of parity bits and a set of systematic bits. Thus, the first wireless device may transmit at least the set of parity bits of the systematic polar code.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

This application discloses a decoding method applicable to multiple scenarios, including metropolitan area networks, backbone networks, and data center interconnections, to meet the needs of optical transmission. The method comprises: obtaining a syndrome corresponding to each of a plurality of codewords; grouping the obtained syndromes and prioritizing each syndrome group; and selecting a syndrome for decoding based on the priority ranking results of each syndrome group. Because this decoding method does not perform the same decoding process on every codeword, it avoids the problem of traditional static decoding schemes requiring the same number of decoding operations regardless of the correctness of the codeword itself. This method enables on-demand decoding, reducing the demand for decoding resources and power consumption.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

A power-imbalanced multi-level decoding method for sparse code multiple access includes: encoded bits of all users are mapped to multi-dimensional sparse codewords through predetermined codebooks; a factor graph matrix is constructed using the predetermined codebooks, all users are classified according to the factor graph matrix under predetermined constraints to determine Z levels; based on a predetermined total transmission power, a progressive multi-level power optimization algorithm is employed to perform power-imbalanced allocation for all users according to the Z levels, thereby determining a locally optimal power vector; transmission signals corresponding to the multi-dimensional sparse codewords are transmitted according to the locally optimal power vector; SCMA detection and power-oriented decoding are sequentially performed for users each level, and outputs decoded bit sequences for the L levels.

The invention relates to the technical field of wireless communication, and discloses an adaptive LDPC code coding method, system and device based on evaporation waveguide field intensity distribution, and a medium, and the method comprises the steps: obtaining the evaporation waveguide field intensity distribution in real time, and generating a field intensity distribution diagram; calculating a channel state parameter, and dynamically selecting a low-density parity check code rate according to the channel state parameter information; dynamic low-density parity check coding is adopted, and a sparse structure is adjusted through a check matrix, so that real-time switching of multi-code-rate low-density parity check codes is carried out; and a receiving end carries out decoding by adopting an NW-RBP decoding algorithm, defines a node updating rule, and dynamically schedules a node updating sequence through a residual error. According to the method, the bit error rate under a complex channel is reduced, and meanwhile, the reliable transmission efficiency of system data is improved.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

System and machine-readable medium for enhanced decoding of demultiplexed data streams received from multiple transmitters. A receiver utilizes erasure decoding (220) when it is determined at a decoder selection means (210) that the number of unknown bits such as dissimilar transmitted bits, i.e. 1 from one transmitter and 0 from another transmitter, is below a threshold which may be the Hamming distance minus one, D -1, of an error and erasure correcting code such as a Reed-Solomon code. Otherwise, if the number of dissimilar transmitted bits is above the threshold, list decoding (230) is utilized. If list decoding does not produce a single result, but instead produces multiple possible results, selection logic (240) may be employed. The selection logic may utilize an errors and erasures decoding of the possible results or a media decoding of the possible results.

While the error correction capability can be altered by changing the redundancy level, requiring different error correction circuits to achieve this increases the circuit size. [Solution] The communication system according to the disclosed technology comprises a transmitting device having an error correction code generation unit and a receiving device having an error correction unit. The error correction code generation unit selects a k-bit data signal, generates an encoded signal by adding (mk) bits of fixed-value signals to the data signal, and generates an n-bit parity signal from the encoded signal. The transmitting device transmits the data signal and the parity signal to the receiving device. The receiving device receives a k-bit received data signal corresponding to the data signal and an n-bit received parity signal corresponding to the parity signal. The error correction unit performs error correction on the error-correction target signal, which consists of the received data signal, the (mk) bits of fixed-value signals, and the received parity signal.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The invention relates to a method for frame synchronization for a digital receive signal, which is received at an output of a transmission channel as a consequence of a binary digital transmit signal supplied to an input of the transmission channel, wherein the binary digital transmit signal contains information to be transmitted in a data packet which has a predetermined number D of data symbols in a data section and a predetermined number S of synchronization symbols in an optional synchronization section, and wherein the binary digital transmit signal has a predetermined symbol rate, wherein the digital receive signal is represented by a sequence of digital samples and wherein a sampling frequency is used which is greater than or equal to the symbol rate.According to the invention, a sliding window is defined which has a temporal length corresponding to the temporal length of a data packet or a data segment of a data packet. At each position µ of the sliding window, a sample value is assigned to each symbol segment of the data segment and optionally to each symbol segment of the synchronization segment of the sliding window. For each position µ of the sliding window, a position value Λ is determined using a predefined metric. met[µ] is determined, using at least the sampled values ​​assigned to the symbol segments of the data segment. The metric is based on the use of a model for the transmission channel, which assumes a memory-free transmission channel and in which the digital received signal is described by a conditional probability density function for each of the possible binary values ​​of the transmitted signal. From the initial time of the sliding window in a position for which the position values ​​Λ met assume a maximum or for which the position value Λ met If a predetermined threshold is exceeded, a start time of a data packet in the digital received signal is determined. The invention further relates to a device and a computer program for implementing the method.

Disclosed in some examples are methods, systems, and machine-readable media for utilizing contextual information to create decoding feedback information to improve decoder accuracy and / or performance. In some examples, the context information is from a layer of the network stack above a layer in which the decoder is located. The context information may be or based on information about previously received and decoded data and / or information about the sender to provide decoding feedback information to the decoder that is both used to correct previous decoding errors, as well as to inform the decoder about which of the plurality of decoding selections is more likely to be correct. This may improve decoding performance by reducing errors, and in some examples, reduce the complexity of selection and thus improve decoder efficiency by excluding certain decoding possibilities.

The embodiment of the application discloses a kind of digital isolator and digital signal transmission method, the technical scheme of the embodiment of the application is by encoding circuit the rising edge and the falling edge of input digital signal are encoded into first pulse sequence and second pulse sequence respectively, by including multiple first pulse groups with time interval being first length characterizing first pulse sequence, multiple second pulse groups with time interval being second length characterizing second pulse sequence, so that more information is added in encoding signal, and the corresponding encoding information of rising edge and falling edge is transmitted through isolating element, while realizing the encoding and transmission of input digital signal, the anti-interference ability of encoding information and the anti-interference performance of digital isolator are improved.

A receiver (115) receives pulse trains (r0, r1) encoding a plurality of bits (b) using a convolutional code {3, 2, 5} whose systematic bit g0 and parity bit g1 are mapped into two binary trains (21, 22) depending respectively on g0^g1 and g1. Noting that the convolutional coding and the mapping lead to modulation (bz-1^b^b.z+1, bz-1^b.z+1, bz-1^b.z+1), a demodulator demodulates the pairs of received pulse trains (r0, r1) into respective pairs of LLR values ​​(b0, b1) and a Viterbi decoder built on a convolutional code {3, 7, 5} decodes each pair of LLR values ​​into a decoded bit (d). Optimal decoding is thus achieved, notably offering a gain estimated at 1.8 dB (in error rate) without additional complexity. See Figure 3 for the abbreviated version.

The present invention discloses a method for designing an alternating LT code degree distribution. The method comprises the following steps: Step 1) generating odd bits and k / R bits of an alternating degree distribution (AD) function based on a robust soliton distribution (RSD) function; Step 2) generating even bits of the alternating degree distribution function that are not k / R bits based on an improved binary exponential distribution (IBED) function; and Step 3) normalizing the alternating degree distribution function. Using this novel degree distribution for LT coding can effectively improve the error control performance of LT codes.

The present disclosure provides a method, apparatus, system, and device including a computer readable medium for managing error correction coding in a memory system. In one embodiment, a memory system includes a system controller configured to communicate with a host device and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code circuit (ECC circuit) configured to perform error correction coding on received data, the data received from at least one of the system controller or the at least one memory.

This invention provides a Viterbi decoding method, apparatus, electronic device, and storage medium. The method includes: calculating the distance between a received codeword and a desired codeword at the same time to obtain a branch metric value at the current time; determining a surviving path metric value at the current time based on the branch metric value, thereby determining surviving path information; setting a deletion threshold; filtering the surviving path metric value at the current time based on the deletion threshold to obtain the minimum surviving path metric value; and, when the decoding time reaches the backtracking depth, starting from the state corresponding to the minimum surviving path metric value at the current decoding time, starting backtracking based on the surviving path information to output the corresponding decoding result. Thus, the setting of the deletion threshold achieves effective filtering of surviving paths, effectively reducing the computational load in the decoding process, and simultaneously achieving high-speed, low-power efficient decoding under any signal-to-noise ratio conditions.

The invention discloses a high-performance flexible multi-user parallel Viterbi decoder and a decoding method thereof, and the decoder comprises an input scheduler module which is used for receiving an input data stream and segmenting and scheduling the data stream to a plurality of parallel decoding cores; each decoding core adopts a bidirectional folding sliding block type structure and is used for independently executing Viterbi decoding operation, and the bidirectional folding sliding block type structure is used for synchronously pushing forward decoding operation and backward decoding operation in a single sliding window; the output collector module is used for collecting and recombining decoding results output by the decoding cores; wherein the plurality of decoding cores can be dynamically divided into one or more decoding groups, and each decoding group is used for independently processing one data stream, so that parallel accelerated decoding of a single high-speed data stream or concurrent decoding of multiple paths of independent data streams is realized. The method has the advantages of low delay, high throughput rate and high flexibility, and adapts to diversified communication protocol and data rate requirements.

A method for encoding data includes: selecting a sequence of pivot candidate positions from a sequence of g encoded vectors to encode blocks of g data symbols in a round of encoding by the following steps: providing a set of g pivot candidate positions; selecting pivot candidate positions for the sequence from the set of pivot candidate positions; removing the selected pivot candidate positions from the set of pivot candidate positions; and repeating until the set of pivot candidate positions is empty and the sequence of selected pivot candidate positions in the round is non-linear. A set of encoded vectors is generated based on the sequence of selected pivot candidate positions, each encoded vector including zero-valued coefficients at positions within the encoded vector preceding the pivot candidate positions and non-zero-valued coefficients at least at the pivot candidate positions.

Disclosed in the present application are a sphere decoding detection method and apparatus, and an electronic device and a readable storage medium. The method comprises: performing orthogonal triangular QR decomposition on a channel response matrix, so as to obtain a Q matrix and an R matrix, wherein columns in the Q matrix are arranged according to the magnitude of channel energy; according to the Q matrix and the R matrix, determining a target equalization signal; executing an ML path search process according to the target equalization signal, so as to select N branches with the minimum metric as survivor paths; performing an ML complement path search on the survivor paths, so as to obtain ML complement paths; and using the survivor path with the minimum metric as an ML path, and obtaining likelihood ratio information of each bit of each symbol of each layer according to the ML path and the ML complement paths.