142results about How to "Reduce circuit" patented technology

A dimmer for a compact fluorescent lamp including a high-frequency switching circuit for generating PWM or other similar control signals and a filter with simple filtering elements. The dimmer circuitry is simple and can be built on a wall-mountable housing for retro-fitting even in an existing two-wire wall-socket.

A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.

A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in synchronization with an internal clock; and an output buffer circuit which includes L FIFO buffers each for latching each bit of the L bits input from the internal bus and extracts stored data from each of the L FIFO buffers in accordance with an input sequence in synchronization with an external clock so as to transfer the data serially to outside, wherein each of the L FIFO buffers includes an M-bit latch circuit and an N-bit latch circuit, and paths of the M-bit and N-bit latch circuits can be selectively switched.

A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

A compact spectrometer system comprising an improved detector is provided herein. The spectrometer system herein disclosed can comprises a filter, a Fourier transform optical element, and a detector. The detector can comprise a custom detector having a shape that corresponds to the pattern of light incident on the detector. The custom detector may comprise a plurality of separate detection areas, each area configured to detect a portion of the light pattern incident on the detector. The custom detector may comprise a material capable of detecting wavelengths in the short-wavelength infrared (SWIR) range. The custom detector may be configured to require a relatively low number of electrical connections such that it may be implemented using standard, low-cost electronic packaging techniques. An improved, custom detector as described herein can provide the functionality of a two-dimensional pixel array detector while being relatively simple and inexpensive to manufacture.