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3 results about "Physical Coding Sublayer" patented technology

The Physical Coding Sublayer (PCS) is a networking protocol sublayer in the Fast Ethernet, Gigabit Ethernet, and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, and lane block synchronization and deskew.

Carrier frames, transmission methods, electronic device, storage medium and program product

PCT designated stageWO2026114299A1Error preventionOverhead informationByte
Provided in the present application are carrier frames, transmission methods, an electronic device, a storage medium and a program product. A carrier frame consists of a plurality of bytes, and the plurality of bytes comprise: a preamble byte, used for carrying a preamble; an overhead byte, used for carrying overhead information of a service; and a time slot byte, used for carrying service content, the carrier frame being sent after being coded; or the carrier frame consists of a plurality of code groups, each code group having a length of 10 bits, and the plurality of code groups comprising: a control code group, the control code group being a start code group of the carrier frame; a first data code group, used for carrying overhead information of a service; and a second data code group, used for carrying service content, the carrier frame being used for transmission performed by means of a physical coding sublayer (PCS).
Owner:ZTE CORP

Challenge circuit for an ethernet system for vehicles

The invention provides an interrogator circuit in an automotive Ethernet network system, comprising a hybrid circuit configured to be coupled to a media-dependent interface circuit for data communication with a responder circuit; a transmit circuit coupled to the hybrid circuit and configured to generate and provide a transmit signal to the hybrid circuit; a receive circuit coupled to the hybrid circuit and configured to receive and parse a receive signal from the hybrid circuit to generate a data signal; a processing circuit coupled to the receive circuit and configured to process the data signal; a physical coding sublayer circuit coupled to the processing circuit and configured to control operation of the transmit circuit; and an echo cancellation circuit coupled between the transmit circuit and the receive circuit and configured to generate an echo cancellation signal.
Owner:REALTEK SEMICON CORP

PCIe high-speed parallel-serial conversion port station multi-split configuration structure

The application relates to the technical field of high-speed digital baseband transmission, and discloses a PCIe high-speed parallel-serial conversion port station multi-split configuration structure, which changes the structure of a fixed-width port that cannot be split, enables a high-speed port to be dynamically split into multiple independent channels to adapt to external devices of different widths, solves the problem of idle channels, and improves the utilization efficiency of physical channels and bus bandwidths; the application introduces a physical coding sublayer combination architecture and a dynamic selector, so that the same hardware structure can support the overall access of high-bandwidth devices and can also be reconstructed into multiple independent links to access multiple low-bandwidth devices; different application topologies can be adapted without modifying a physical layout, and the flexibility of chip configuration is improved.
Owner:HUNAN JIANGXIN MICROELECTRONICS CO LTD