13 results about "Physical Coding Sublayer" patented technology

The invention discloses an Ethernet data transmission method and device, equipment and a storage medium, and relates to the technical field of communication, the method is applied to a receiving end, and the method comprises the following steps: receiving code stream data obtained by inserting a protection frame code block into a coding code stream of a physical coding sub-layer by a sending end from a physical link; performing framing processing on the code stream data to obtain frame description information of the lossless protection frame; performing alignment processing on the lossless protection frames on different physical links based on the frame description information; and eliminating redundant frames from the aligned lossless protection frames according to frame serial numbers in the frame description information to obtain lossless protection frames with continuous frame serial numbers, and sending the lossless protection frames to the downstream. By sinking Ethernet service lossless protection from a data frame level to a code block level of a physical coding sub-layer, service protection overhead is allocated to a code stream with finer granularity, the effective bandwidth utilization rate of data transmission is remarkably improved, the processing frequency is reduced from a high frequency of the data frame level to a low frequency of the code block level, and the hardware implementation difficulty is reduced.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

A system includes a MAC layer and a PCS in communication with the MAC layer via a transmit data path. The transmit data path includes a data request signal transmitted from the PCS to the MAC layer and a data valid signal transmitted from the MAC layer to the PCS. A SYNC pipeline of the PCS generates a copy of the data valid signal that has a same timing as the data valid signal. When the data valid signal from the MAC layer to the PCS matches the copy of the data valid signal generated by the PCS, the PCS is in synchronization with the MAC layer. When the data valid signal from the MAC layer to the PCS does not match the copy of the data valid signal, the PCS ignores input data from the MAC layer and generates an idle symbol to a link partner.

Provided in the present application are carrier frames, transmission methods, an electronic device, a storage medium and a program product. A carrier frame consists of a plurality of bytes, and the plurality of bytes comprise: a preamble byte, used for carrying a preamble; an overhead byte, used for carrying overhead information of a service; and a time slot byte, used for carrying service content, the carrier frame being sent after being coded; or the carrier frame consists of a plurality of code groups, each code group having a length of 10 bits, and the plurality of code groups comprising: a control code group, the control code group being a start code group of the carrier frame; a first data code group, used for carrying overhead information of a service; and a second data code group, used for carrying service content, the carrier frame being used for transmission performed by means of a physical coding sublayer (PCS).

The application relates to the technical field of data communication interfaces, and discloses a disk pulling and chain dropping method and device based on a SAS / SATA protocol, computer equipment and a storage medium, the method being used for a target device and comprising the following steps: detecting the device type of the target device; when a physical coding sublayer of the target device is in a physical layer ready state, detecting the receiving state of an indication signal corresponding to the device type of the target device in real time; and when the receiving state of the indication signal corresponding to the device type of the target device meets a chain dropping condition of the device type, triggering the physical coding sublayer to drop from the physical layer ready state. The application realizes the disk pulling and chain dropping function based on the SAS / SATA protocol, solves the problem that the physical coding sublayer does not drop after the disk is pulled, and improves the reliability and stability of serial communication.

Systems, devices, products, and methods for precise timestamping of Ethernet frames are described. In some implementations, a device may include a network interface circuit element and a logic circuit element configured to execute an instruction (500) which causes the logic circuit element to determine a first delay introduced by a physical coding sublayer circuit element in a first time (502), adjust a first timestamp associated with and transmitted with a first transmission based on the first delay (504), determine a second delay introduced by a physical coding sublayer circuit element in a second time, which is different from the first delay (502), adjust a second timestamp associated with and transmitted with a second transmission based on the second delay (506) (504).

A method in a transmitter of a communications system, the transmitter comprising a physical coding sublayer, PCS, for transmitting data to a receiver, the method comprising: monitoring a digital data stream to identify PCS idle blocks in the digital data stream; generating substitute data blocks for transmitting to the receiver in place of the PCS idle blocks, the substitute data blocks comprising low transition blocks, LTBs, and one or more pattern information blocks.

The invention provides an interrogator circuit in an automotive Ethernet network system, comprising a hybrid circuit configured to be coupled to a media-dependent interface circuit for data communication with a responder circuit; a transmit circuit coupled to the hybrid circuit and configured to generate and provide a transmit signal to the hybrid circuit; a receive circuit coupled to the hybrid circuit and configured to receive and parse a receive signal from the hybrid circuit to generate a data signal; a processing circuit coupled to the receive circuit and configured to process the data signal; a physical coding sublayer circuit coupled to the processing circuit and configured to control operation of the transmit circuit; and an echo cancellation circuit coupled between the transmit circuit and the receive circuit and configured to generate an echo cancellation signal.

The invention relates to a data transmission method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a working mode matched with a receiving end; under the condition that the working mode is the optimization mode, sending a first data frame to a receiving end; the lead code of the first data frame comprises a start delimiter and a first number of idle characters; the first number is smaller than the number of idle characters in the standard mode; under the condition that the data frame transmission state meets the frame interval insertion condition, obtaining the accumulated number of the alignment marks inserted in the data code stream by the physical coding sub-layer; if the cumulative number is greater than or equal to a compensation number threshold value, determining a frame interval compensation amount based on the cumulative number after the transmission of the first data frame is completed, and sending a frame interval with a reduced byte number to a receiving end; the reduced number of bytes is used to compensate for bandwidth overhead introduced by the alignment mark. By adopting the method, the network bandwidth can be improved.

The present disclosure relates to a module for a first Ethernet node of a set of Ethernet nodes, the module comprising a Medium Access Control (MAC) interface, a Physical Coding Sublayer (PCS) interface and a Priority Manager (PM) interface, the module receiving and / or transmitting a sequence of cycles through the interfaces, each priority sequence consists of a sequence of predefined commit symbols and dedicated priority symbols, the dedicated priority symbols being assigned to the respective priority sequence and indicating the priority of Ethernet frames ready to be transmitted by one Ethernet node of a set of Ethernet nodes, the announcement sequence consists of a sequence of a start symbol, a predefined commit symbol, and a superior node symbol indicating one of the Ethernet nodes ready to transmit the Ethernet frame with the highest priority, and the data sequence includes the Ethernet frame with the highest priority. The present disclosure also relates to an Ethernet node comprising a module and a communication system comprising several Ethernet nodes.

The disclosure relates to a physical layer transceiver that reduces variations in packet latency. A method of reducing the effects of latency variations in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sub-layer circuitry having a first clock in a first clock domain and physical media connection circuitry having a second clock in a second clock domain, comprising the steps of determining a transmission delay value in a transmission direction from a first clock domain to a second clock domain during an initial training period of a link; determining a receiving delay value in a receiving direction from the second clock domain to the first clock domain separately from the determined transmission delay value during the initial training period of the link; and using the transmission delay value and the reception delay value to calculate a delay in data transfer between the first clock domain and the second clock domain after the initial training until before the subsequent training.

The present disclosure relates to a module for an Ethernet node of a group, the module including media access control (MAC), physical coding sublayer (PCS), and priority manager (PM) interfaces. The module is configured to receive or transmit sequences of a cycle over the interfaces. The cycle includes a start sequence, a series of priority sequences, an announcement sequence, and a data sequence. The start sequence includes a predefined start and advertisement symbols. Each priority sequence includes a predefined commit symbol and a dedicated priority symbol assigned to the respective priority sequence and indicating a priority of an Ethernet frame ready to be sent. The announcement sequence includes the start symbol, a predefined commit symbol and a winner node symbol indicating one of the Ethernet nodes being ready to send the Ethernet frame having the highest priority. The data sequence includes the Ethernet frame having the highest priority.

The application relates to the technical field of high-speed digital baseband transmission, and discloses a PCIe high-speed parallel-serial conversion port station multi-split configuration structure, which changes the structure of a fixed-width port that cannot be split, enables a high-speed port to be dynamically split into multiple independent channels to adapt to external devices of different widths, solves the problem of idle channels, and improves the utilization efficiency of physical channels and bus bandwidths; the application introduces a physical coding sublayer combination architecture and a dynamic selector, so that the same hardware structure can support the overall access of high-bandwidth devices and can also be reconstructed into multiple independent links to access multiple low-bandwidth devices; different application topologies can be adapted without modifying a physical layout, and the flexibility of chip configuration is improved.