43 results about "Physical Coding Sublayer" patented technology

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

The invention relates to a chip, a processing device and electronic equipment, relates to the technical field of chips, and provides a bare chip division mode in a chiplet. The chip comprises a first bare chip and a second bare chip; the first bare chip comprises a physical coding sublayer PCS circuit, and the second bare chip comprises a physical medium access sublayer PMA circuit and a physical medium related PMD circuit; the PCS circuit of the first bare chip is coupled with the PMA circuit of the second bare chip; the PMA circuit is coupled with the PMD circuit.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

The embodiment of the application provides an Ethernet device processing method and an Ethernet system. The Ethernet device processing method is applied to the Ethernet system. The Ethernet system comprises a first device and a second device. The first device and the second device perform data communication through Ethernet technology. The first device comprises a first medium access control chip and a first physical layer chip. The first physical layer chip comprises a first physical coding sublayer (PCS) and a first physical medium access sublayer (PMA). The Ethernet device processing method comprises the following steps: the first PMA receives a control signal sent by the first PCS; the first PMA generates a maintenance code stream and sends the maintenance code stream to the second device; the maintenance code stream is used for maintaining synchronization of link parameters between the first device and the second device; when there is no data transmission between the first device and the second device, the synchronization of the link parameters at both ends is maintained by transmitting the maintenance code stream at both ends; and when it is detected that data is to be transmitted, the first device is enabled to quickly enter a working state, so that the wake-up time is reduced.

Systems, apparatus, articles of manufacture, and methods for precisely timestamping Ethernet frames are described. In some embodiments, an apparatus may include network interface circuitry; logic circuitry configured to execute instructions (500) to cause the logic circuitry to: determine (502) a first delay introduced by the physical coding sublayer circuitry at a first time; adjusting (504) a first timestamp associated with a first transmission based on the first delay, the first timestamp being transmitted with the first transmission; determining (502) a second delay introduced by the physical coding sublayer circuitry at a second time, the second delay being different from the first delay; and adjusting (504) a second timestamp associated with a second transmission based on the second delay, the second timestamp being transmitted (506) with the second transmission.

The invention discloses an Ethernet data transmission method and device, equipment and a storage medium, and relates to the technical field of communication, the method is applied to a receiving end, and the method comprises the following steps: receiving code stream data obtained by inserting a protection frame code block into a coding code stream of a physical coding sub-layer by a sending end from a physical link; performing framing processing on the code stream data to obtain frame description information of the lossless protection frame; performing alignment processing on the lossless protection frames on different physical links based on the frame description information; and eliminating redundant frames from the aligned lossless protection frames according to frame serial numbers in the frame description information to obtain lossless protection frames with continuous frame serial numbers, and sending the lossless protection frames to the downstream. By sinking Ethernet service lossless protection from a data frame level to a code block level of a physical coding sub-layer, service protection overhead is allocated to a code stream with finer granularity, the effective bandwidth utilization rate of data transmission is remarkably improved, the processing frequency is reduced from a high frequency of the data frame level to a low frequency of the code block level, and the hardware implementation difficulty is reduced.

The present invention relates to the field of high-speed interface technology, and discloses a channel binding method, apparatus, device, medium, and program product. The method is applied to the receiving direction of an FPGA chip, and includes the following steps: obtaining a data transmission protocol and confirming the number of channels according to the data transmission protocol; confirming a primary channel and a secondary channel based on the number of channels; when the primary channel receives target data and confirms the target frame header of the target data, controlling the primary channel to send an alignment signal; and transmitting the alignment signal to the secondary channel via the entire Internet; when the secondary channel receives the alignment signal, adjusting the first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel; after the first-in-first-out queue read pointers corresponding to each secondary channel are adjusted, reading data from the first-in-first-out queue corresponding to the secondary channel and outputting it from the data port in the receiving direction of the physical coding sublayer. The method can adapt to the number of bound channels required by different protocols, greatly increasing the flexibility of channel binding.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

A system includes a MAC layer and a PCS in communication with the MAC layer via a transmit data path. The transmit data path includes a data request signal transmitted from the PCS to the MAC layer and a data valid signal transmitted from the MAC layer to the PCS. A SYNC pipeline of the PCS generates a copy of the data valid signal that has a same timing as the data valid signal. When the data valid signal from the MAC layer to the PCS matches the copy of the data valid signal generated by the PCS, the PCS is in synchronization with the MAC layer. When the data valid signal from the MAC layer to the PCS does not match the copy of the data valid signal, the PCS ignores input data from the MAC layer and generates an idle symbol to a link partner.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

The application provides a data transmission system, a data receiving method and a data sending method. The system comprises a physical layer unit, a physical coding sublayer unit, a link control layer unit and a port logic unit. The physical layer unit adopts an Ethernet physical layer unit structure to interact with the physical coding sublayer unit. The physical coding sublayer unit interacts with the physical layer unit and the link control layer unit. The link control layer unit comprises an interface adaptation module, an Ethernet MAC layer module, an IB link layer module, a data receiving buffer and a data sending buffer. The interface adaptation module interacts with the Ethernet MAC layer module or the IB link layer module. The Ethernet MAC layer module processes data in an Ethernet transmission mode. The IB link layer module processes data in an IB transmission mode. The port logic unit comprises an entry module and an exit module. The entry module sends out IB data. The exit module sends data to the link control layer unit.

A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.

Systems and methods for reducing the number of comparators used during alignment marker (AM) search are presented. The method comprises the step of enabling communication between a physical coding sublayer (PCS) and a physical media access (PMA) sublayer having a PCS transmitting side and a PCS receiving side at a first stage using a plurality of PCS lanes, wherein the plurality of PCS lanes receive data blocks from a plurality of PCS lanes - a PCS lane includes an alignment marker (AM) on the PCS transmitting side - and performs an AM search using a first AM search stage circuit, wherein in the first AM search stage circuit, all of the plurality of PCS lanes are searched sequentially using read components of the PCS receiving side until an AM is detected in all of the plurality of PCS lanes.

Provided in the present application are carrier frames, transmission methods, an electronic device, a storage medium and a program product. A carrier frame consists of a plurality of bytes, and the plurality of bytes comprise: a preamble byte, used for carrying a preamble; an overhead byte, used for carrying overhead information of a service; and a time slot byte, used for carrying service content, the carrier frame being sent after being coded; or the carrier frame consists of a plurality of code groups, each code group having a length of 10 bits, and the plurality of code groups comprising: a control code group, the control code group being a start code group of the carrier frame; a first data code group, used for carrying overhead information of a service; and a second data code group, used for carrying service content, the carrier frame being used for transmission performed by means of a physical coding sublayer (PCS).

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

The invention discloses Ethernet physical layer equipment, an Ethernet data transmission system and a related method, and belongs to the technical field of communication. The first Ethernet physical layer equipment comprises a physical coding sub-layer module and a physical medium adaptation module, the physical coding sub-layer module comprises a detection module, and the detection module is in communication connection with the physical medium adaptation module; wherein the physical medium adaptation module is used for receiving first data sent by second Ethernet physical layer equipment; the detection module is used for determining that an optical fiber transmission standard protocol used by the second Ethernet physical layer equipment is a first protocol; and under the condition that the optical fiber transmission standard protocol used by the first Ethernet physical layer equipment is a second protocol, controlling the first Ethernet physical layer equipment to be switched from the second protocol to the first protocol, and the first Ethernet physical layer equipment and the second Ethernet physical layer equipment are connected through the first protocol.

The application relates to the technical field of data communication interfaces, and discloses a disk pulling and chain dropping method and device based on a SAS / SATA protocol, computer equipment and a storage medium, the method being used for a target device and comprising the following steps: detecting the device type of the target device; when a physical coding sublayer of the target device is in a physical layer ready state, detecting the receiving state of an indication signal corresponding to the device type of the target device in real time; and when the receiving state of the indication signal corresponding to the device type of the target device meets a chain dropping condition of the device type, triggering the physical coding sublayer to drop from the physical layer ready state. The application realizes the disk pulling and chain dropping function based on the SAS / SATA protocol, solves the problem that the physical coding sublayer does not drop after the disk is pulled, and improves the reliability and stability of serial communication.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

The invention discloses a data transmission system, a chip and electronic equipment, and belongs to the technical field of integrated circuits, and the data transmission system comprises a medium access control layer, a physical coding sub-layer and a physical medium adaptation layer. In a data transmission system of a sending end, a physical coding sub-layer comprises a conversion module; the conversion module is used for performing bit width conversion and clock domain conversion on first sending data sent by the medium access control layer to obtain second sending data, and sending the second sending data to the physical medium adaptation layer; in a data transmission system of a receiving end, a physical coding sub-layer comprises a locking module and a processing module which are electrically connected; the locking module is used for performing data locking on first receiving data sent by the physical medium adaptation layer to obtain second receiving data, and sending the second receiving data to the processing module; and the processing module is used for processing the second receiving data into third receiving data and sending the third receiving data to the medium access control layer.

Systems, devices, products, and methods for precise timestamping of Ethernet frames are described. In some implementations, a device may include a network interface circuit element and a logic circuit element configured to execute an instruction (500) which causes the logic circuit element to determine a first delay introduced by a physical coding sublayer circuit element in a first time (502), adjust a first timestamp associated with and transmitted with a first transmission based on the first delay (504), determine a second delay introduced by a physical coding sublayer circuit element in a second time, which is different from the first delay (502), adjust a second timestamp associated with and transmitted with a second transmission based on the second delay (506) (504).

A method in a transmitter of a communications system, the transmitter comprising a physical coding sublayer, PCS, for transmitting data to a receiver, the method comprising: monitoring a digital data stream to identify PCS idle blocks in the digital data stream; generating substitute data blocks for transmitting to the receiver in place of the PCS idle blocks, the substitute data blocks comprising low transition blocks, LTBs, and one or more pattern information blocks.

The present application relates to the technical field of chips, relates to a chip, a processing apparatus and an electronic device, and provides a die division method in a chiplet. The chip comprises a first die and a second die, wherein the first die comprises a physical coding sublayer (PCS) circuit, and the second die comprises a physical medium attachment sublayer (PMA) circuit and a physical medium dependent sublayer (PMD) circuit; the PCS circuit of the first die is coupled with the PMA circuit of the second die; and the PMA circuit is coupled with the PMD circuit.

The invention provides an interrogator circuit in an automotive Ethernet network system, comprising a hybrid circuit configured to be coupled to a media-dependent interface circuit for data communication with a responder circuit; a transmit circuit coupled to the hybrid circuit and configured to generate and provide a transmit signal to the hybrid circuit; a receive circuit coupled to the hybrid circuit and configured to receive and parse a receive signal from the hybrid circuit to generate a data signal; a processing circuit coupled to the receive circuit and configured to process the data signal; a physical coding sublayer circuit coupled to the processing circuit and configured to control operation of the transmit circuit; and an echo cancellation circuit coupled between the transmit circuit and the receive circuit and configured to generate an echo cancellation signal.

The embodiment of the invention provides an Ethernet code stream processing method and device and network equipment, and relates to the technical field of communication, and the method comprises the steps: obtaining an Ethernet code stream and a first source port number of the Ethernet code stream; obtaining a destination port number of the Ethernet code stream from configuration information corresponding to the first source port number; if the sewer mark of the first FIFO corresponding to the destination port number is set, deleting idle code blocks included in the Ethernet code stream, and caching non-idle code blocks included in the Ethernet code stream to the first FIFO; and transmitting the Ethernet code stream in the first FIFO to a physical coding sublayer (PCS) corresponding to the destination port number. Packet loss caused by inconsistent clocks of a receiving channel and a sending channel can be avoided.

The invention relates to a data transmission method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a working mode matched with a receiving end; under the condition that the working mode is the optimization mode, sending a first data frame to a receiving end; the lead code of the first data frame comprises a start delimiter and a first number of idle characters; the first number is smaller than the number of idle characters in the standard mode; under the condition that the data frame transmission state meets the frame interval insertion condition, obtaining the accumulated number of the alignment marks inserted in the data code stream by the physical coding sub-layer; if the cumulative number is greater than or equal to a compensation number threshold value, determining a frame interval compensation amount based on the cumulative number after the transmission of the first data frame is completed, and sending a frame interval with a reduced byte number to a receiving end; the reduced number of bytes is used to compensate for bandwidth overhead introduced by the alignment mark. By adopting the method, the network bandwidth can be improved.

A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.

The invention discloses a delay measurement method of a physical coding sub-layer, an FPGA and an electronic device, and belongs to the technical field of integrated circuits, the method comprises the following steps: obtaining to-be-transmitted data, a first clock signal of the physical coding sub-layer and a second clock signal of the physical coding sub-layer, the first clock signal being used for data transmission of a first port, and the second clock signal being used for data transmission of a second port; the second clock signal is used for data transmission of the second port; when the to-be-transmitted data is to-be-sent data, a first moment when a first signal is transmitted to the first port is determined, and the first signal and the to-be-sent data are in channel-associated transmission; determining a second moment when the first adjusting module outputs a second signal and first delay information of the first adjusting module, wherein the edge of the second signal is aligned with the edge of the first clock signal; and determining a sending delay according to the first moment, the second moment and the first delay information. According to the invention, the number of interfaces used for measuring the delay of the PCS through the first signal is smaller, and the accuracy of the delay measurement of the physical coding sub-layer is improved.

This disclosure provides methods, devices, and systems for timestamping Ethernet packets. The present implementations more specifically relate to capturing timestamps in the same clock domain as a media-dependent interface (MDI). In some aspects, a physical layer (PHY) transceiver may generate a receive (RX) timestamp for a precision time protocol (PTP) packet based on a time at which a physical medium attachment (PMA) sublayer outputs, to a physical coding sublayer (PCS), one or more PHY frames carrying the PTP packet. In some other aspects, a PHY transceiver may generate a transmit (TX) timestamp for a PTP packet based on a time at which a PCS outputs a reference frame to a PMA sublayer, where the reference frame precedes one or more PHY frames carrying the PTP packet.

The invention discloses a physical layer chip link quality detection method and device and electronic equipment, and belongs to the technical field of computers. The method comprises the following steps: acquiring a physical coding sub-layer descrambling state, a real-time signal-to-noise ratio and a physical layer chip link state of a target physical layer chip; performing detection configuration on the physical coding sub-layer descrambling state, the real-time signal-to-noise ratio and the physical layer chip link state according to a set single detection condition; acquiring a first configuration condition aiming at the real-time signal-to-noise ratio, a second configuration condition aiming at the descrambling state of the physical coding sub-layer and a third configuration condition aiming at the link state of the physical layer chip; determining whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition and the third configuration condition; and under the condition that the link of the target physical layer chip is abnormal, determining an abnormity corresponding to a target configuration condition as a link abnormity reason of the target physical layer chip.

In a general aspect, a network interface capable of processing network traffic conforming to a Time Sensitive Network (TSN) standard and a Media Access Control layer security (MACsec) standard, comprises, within an ingress path, a Physical Coding Sublayer (PCS) connected to receive a traffic stream from a network link; a Media Access Control (MAC) unit configured to split the traffic stream into a preemptable packet stream and an express packet stream; and a MACsec unit connected between the PCS and the MAC unit, configured to operate on individual fragments of a preempted MACsec protected packet in the traffic stream to produce a traffic stream with unprotected fragments for the MAC unit.