398results about How to "Increase jitter" patented technology

A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a second switch triggered by a backward trigger signal, a first operational amplifier generating a first drive signal while the first and second switches are on, a first transistor switch triggered to be on by a first drive signal to provide a current source loop, a third switch triggered by a forward trigger signal, a fourth switch triggered by a backward trigger signal, a second operational amplifier generating a second drive signal while the third and fourth switches are on, and a second transistor switch triggered to be on by a second drive signal to provide a current sink loop.

A dynamic vision sensor (DVS) or change detection sensor reacts to changes in light intensity and in this way monitors how a scene changes. This disclosure covers both single pixel and array architectures. The DVS may contain one pixel or 2-dimensional or 1-dimensional array of pixels. The change of intensities registered by pixels are compared, and pixel addresses where the change is positive or negative are recorded and processed. Analyzing frames based on just three values for pixels, increase, decrease or unchanged, the proposed DVS can process visual information much faster than traditional computer vision systems, which correlate multi-bit color or gray level pixel values between successive frames.

The invention discloses a UTC high-precision time synchronization method based on an optical transmission network. In the invention, time base signals are transmitted by the optical transmission network between a primary station between a secondary station: firstly, the time base is transmitted to the secondary station by the primary station, and then time interval deviation is calculated by the secondary station based on time shown by a local clock of the secondary station and the time base; secondly, the local clock of the secondary station is corrected by the secondary station based on thetime interval deviation and a checked time base is returned to the primary station by the secondary station; and finally, the time base originally sent to the secondary station is corrected by the primary station based on the checked time base and the time shown by a local clock of the primary station and the corrected time base is sent to the secondary station again by the primary station. When the time base is transmitted between the primary station and the secondary station, two-way comparison is conducted between the primary station and the secondary station to precisely measure transmission delay asymmetry of a transmission loading network, accurately judge and standardize time and frequency synchronization scope of the secondary station, and provide 3G / 4G communication networks withthe high-precision time synchronization method based on the integration of time and frequency, thereby realizing higher-precision time and frequency synchronization.

The invention relates to a recycling method for treating ammonia nitrogen containing high-salt catalyst wastewater by adopting a membrane separation technology. The process flow of 'acid regulation, micro-filtration, membrane distillation, cooling and crystallization' is adopted in the method. By adopting the process flow, salts, ammonia nitrogen and metal ions in the wastewater can be effectively removed, and deep treatment and recycle of the ammonia nitrogen containing high-salt catalyst wastewater are realized. The process flow makes full use of the technical advantages of membrane distillation, solves the problem that the discharge of high salts, ammonia nitrogen and metal ions of the ammonia nitrogen containing high-salt catalyst wastewater does not reach the standards, and realizes recycle of the produced water. After the ammonia nitrogen containing high-salt catalyst wastewater is treated by the process flow, the reclamation rate of the wastewater is more than 90 percent, and high recycle of the ammonia nitrogen containing high-salt catalyst wastewater is realized; and the method accords with the development strategies of energy conservation and emission reduction, and has remarkable social benefit and economic benefit.

An on-board call access control method is characterized in that for access request, firstly judge the type of call: if a switching call, determine the switching call service is low-priority or high-priority, and implement the switching call request access process on the low-priority or the high-priority call service; if a new call, determine the new call service is low-priority or high-priority, and implement the new call request access process on the low-priority or the high-priority call service. Under the circumstances of ensuring the indexes of handoff failure probability of satellite systems, the new call-blocking probability, the link bandwidth utilization and so on, the invention fully considers the satisfaction of users and the influence of network-load changes on the system performances, effectively ensures the QOS requirement of mobile satellites, and improves comprehensive properties and robustness of satellite systems.

The invention relates to a double-arm transmission robot applied to a clean environment, which is used for the transmission and high-precision positioning placement of a large-diameter semiconductor silicon wafer in a high-cleanliness environment. The double-arm transmission robot is in the structural form of R-theta type and has the working principle of a space structure based on a cylindrical coordinate system and the characteristic of independent control of all motion shafts. The double-arm transmission robot mainly comprises an R-axis left arm mechanism, an R-axis right arm mechanism, a T-axis rotating mechanism, a Z-axis lifting mechanism, and the like and seals the pollution of a drive mechanism on an external environment by adopting a special seal device so as to be suitable for the high-cleanliness production environment requirement.

Source devices, softwares and methods are provided for predicting at a transmitting source how well a specific encoded frame, relative to other frames in a stream, would be reconstructed if it were not available for eventual playout at a receiving destination. If poorly, then the specific encoded frame is packetized and transmitted advantageously with respect to other packets in a stream. The transmitted stream will have higher jitter. Predicting is performed at the source by synthesizing a replicated frame, which emulates how the specific frame would be reconstructed at the destination. Then the replicated frame is compared with the decoded specific frame. The eventual playout will have a higher fidelity to the original, since reconstructed from more critical frames. Receiving devices, softwares and methods are provided for receiving in a jitter buffer a stream of packets containing encoded data frames, determining that they have been packetized differently from each other, and setting a playout delay of the jitter buffer responsive to the determination, regardless of high jitter.

After a playback RF signal 3 detected from an optical disc medium 1 is waveform-shaped, it is converted into a digital RF signal 6 with a sampling clock 8 having a cycle twice as long as a channel clock. Thereafter, a first offset correction circuit 9 corrects an offset fluctuation in a high frequency band, and a digital adaptive equalizer 23 performs adaptive equalization, and then a second offset correction circuit 27 corrects an offset component that remains after the offset correction by the first offset correction circuit 9, thereby demodulating a digital binary signal 37. Therefore, even when high-speed playback is carried out and an asymmetry depending on the recording quality is large, a reduction in power consumption can be realized while maintaining high-performance playback. Consequently, it is possible to provide an optical disc playback apparatus which can realize sufficient playback performance at low power consumption.

An information recording medium for high-density recording and reproduction that is low-cost and that has good rewrite characteristics. The information recording medium, in which recording is performed as an atomic arrangement is changed by optical irradiation, is capable of a number of rewrites. The information recording medium comprises a substrate on which a first protective layer with a thickness in the range from 18 to 65 nm, a recording film, a second protective layer, and a reflective layer are disposed in the mentioned order as seen from a light-incident side. Not less than 97 atomic % of the composition of the recording film is accounted for by Ge, Bi, and Te.

The invention provides a tank gun control servo control method based on an auto-disturbance rejection control technology, which can improve the dynamic firing accuracy and the weapon stabilization accuracy of a fire control system. The tank gun control servo control method comprises the following steps: step 1, establishing a large-caliber gun turret control model; step 2, designing a tracking differential controller in a horizontal stabilizer based on the auto-disturbance rejection control technology according to the control model established in the step 1; step 3, designing a third-order extended state observer (ESO) according to the large-caliber gun turret control model put forward in the step 1 to estimate the disturbance of the system and compensate in real time; step 4, obtaining a differentiation between an error e1 and an error e2 according to the obtained large-caliber gun turret control model; and step 5, obtaining a system control law according to an auto-disturbance rejection control principle after a nonlinear feedback law is designed.

A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

A system and method are provided for frequency lock detection using a digital phase error. A lock detection module accepts a digital phase error (pherr) message proportional to an error in phase between a reference clock and a (synthesizer clock*Nf). Also accepted is a unitless frequency error tolerance value (Δf). The lock detection module periodically supplies a lock detect signal, indicating whether the synthesizer clock frequency is within the frequency error tolerance value of the reference clock frequency.

A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.

A novel method for driving a display device includes the steps of receiving video data of a first type, converting the video data to data of a second type, dithering the data of the second type to form dithered pixel data, and outputting the dithered pixel data. The step of converting the video data to data of a second type includes inserting dither bits indicative of a particular dithering scheme into the data of the second type. An example display driver circuit includes an input for receiving video data, a data converter coupled to receive the video data and operative to convert the video data into pixel data to be written to pixels of a display, and a ditherer operative to receive the pixel data and to dither the pixel data to generate dithered pixel data. The video data is data of a first type, and the pixel data is data of a second type, different from the first type. In the disclosed example, the first type of data includes a binary data word, and the second type of data includes a compound data word. The compound data word includes a first set of binary weighted bits, a second set of arbitrarily weighted bits, and dither bits.

The method includes the follows: calculating out discretization probability table; adjusting maximum discarding probability value as per message type, processing message arrived to the equipment at t times; calculating message arrival speed rate in between time t' and time t, average queue length of idle queue at time t, integrated average idle queue length; calculating out index value of table item for discarding probability to obtain message transmission probability P(t) in the period; comparing probability p(t) with random number P generated currently to decide whether the message is discarded or is retransmitted.

A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

The invention relates to a full-automatic high-altitude window cleaning intelligent robot. The robot comprises a self-stabilizing travelling device with good fixation performance and stability performance. The condition of jittering in the wiping process is eliminated, and the working efficiency is improved. A detachable fixing device is mounted in the middle of the upper end face of the self-stabilizing travelling device and can be disassembled and assembled conveniently. When the robot is damaged and needs to be maintained, the robot can be manually disassembled through the detachable fixing device, only the damaged part needs to be taken out and maintained, and operation is easy and convenient. An orientable conversion device is mounted at the upper end of the detachable fixing device, and the wiping angle of the orientable conversion device is adjustable, so that the robot is applicable to high-altitude glass of different angles, and the application range is wide. A window cleaning manipulator is mounted on the upper end face of the orientable conversion device. The full-automatic high-altitude window cleaning intelligent robot can achieve the full-automatic cleaning function of high-altitude glass, and a new way to full-automatic cleaning of high-altitude glass is provided.

The invention discloses a device and a method for synchronizing system frequency in a packet transport network, and relates to a packet transport network in optical communication. The system frequency synchronizing device comprises a microcomputer processor, a field programmable gate array (FPGA) processing module, a clock integrated circuit, a packet transport network service disk, a synchronous state byte extracting module, a synchronous state byte generating module, a phase locked loop circuit, an external clock input circuit, a high stable crystal oscillator, a clock distributing circuit, a HDB3 coding module and an external clock output circuit, wherein the FPGA processing module comprises a preceding stage preselector, a priority level control module, a first selector, a second selector and a third selector. By the device and method, the system frequency in the whole packet transport network can be synchronized rapidly, data business package transmission and smooth transition can be carried out rapidly and hierarchically, and the device is flexible and has high reliability.

The invention relates to the field of sewage treatment, in particular to sewage treatment equipment convenient for oil-water separation. The sewage treatment equipment comprises a box body, conveyingmechanisms, an oil scraping mechanism, a transmission mechanism, a stirring mechanism, a filtering mechanism, a blocking mechanism, a collecting mechanism and a locking mechanism. Sewage can be fullypurified in the box body through the conveying mechanisms at two sides of the box body; after the sewage enters the oil scraping mechanism, oil and water can be classified and circulated through separation and scraping of the oil scraping mechanism; when the sewage subjected to oil stain removal enters the filtering mechanism in the box body, impurities in the sewage are filtered out through the filtering mechanism; in a process that separated oil stains are scraped, the transmission mechanism is driven to drive the stirring mechanism to stir the impurities in the filtering mechanism, so thatthe impurities in the sewage are more uniformly contained by the filtering mechanism; and meanwhile, the stirring mechanism shakes the filtering mechanism, so that particles in the filtering mechanismsink to the collecting mechanism at the bottom of the box body and are collected.

The invention discloses a self-shaking falling-off cleaning type filtering device for waste gas and dust treatment, and belongs to the technical field of waste gas and dust treatment.The self-shakingfalling-off cleaning type filtering device is provided with a pressed pushing body which moves downwards in a pressed mode along with high air pressure, and when a filtering net reaches certain adsorption saturation, a magnetic shielding body is pulled to move downwards and disengage from a magnetic ball; and the magnetic shielding effect on the magnetic ball is weakened to a certain extent, at the moment, the magnetic shielding body repels a magnetic repulsion body, the magnetic repulsion body and the filter net expand outwards together, filter holes of the filter net are enlarged, a small amount of dust is shaken off in the expanding process, the filter net has the refiltering capacity, and the air pressure in the filter net is gradually reduced. The magnetic shielding body is reset upwards under the stretching action of the elastic stretching rope to magnetically shield the magnetic repulsion body, the filter net is reset inwards under the elastic action of a compression spring, dust is shaken in the reset rebounding process, meanwhile, a piston type water pressing mechanism is extruded to spray water when the filter net moves inwards, and the flocculation and dust falling effects on the dust are achieved. Agglomerated dust falls into a dust receiving barrel to be collected.

A method for implementing the integrated queue scheduling to support multiple services is disclosed. When predefined first priority message is added to queue, the speed at which the message in different class comes the queue relative to the first priority transmitted group is limited by the predefined first speed. If its speed is lower than or equal to the predefined first speed, it can come in the queue. If it is not it is rejected. When predefined first and second priority messages go out of the queue and the message in default queue is detected, their speed is limited by a predefined second speed. If their speed is lower than or equal to the predefined second speed, they can be transmitted. Or the predefined third message is transmitted.

The invention discloses an SDN (Software Defined Network) core network QoS (Quality of Service) routing optimization algorithm based on reinforcement learning. The SDN core network QoS routing optimization algorithm comprises the following steps: acquiring network topology and real-time node information and link information through an SDN controller; according to the obtained network topology and real-time node information and link information, calculating a reward matrix by using a QoS network routing optimization model; initializing and updating the Q table; and obtaining a required optimal forwarding path according to the Q table which is iteratively updated. According to the method, multiple QoS intentions such as low delay, low jitter, large bandwidth, preferential use of private lines and service levels can be met, the shortest forwarding path meeting the QoS requirement can be found for each service flow, the link utilization rate is high, network congestion can be effectively prevented and reduced, and the network resource utilization rate is improved.

A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

The invention discloses a model-free control method for an aerodynamic heat superhelix nonlinear fractional order sliding mode, and the method comprises the steps: building a mathematical model between the input electric energy and the output temperature of an aerodynamic heat ground simulation system of a hypersonic aircraft based on the law of conservation of energy, and converting the mathematical model into a model-free control superlocal model; constructing a nonlinear fractional order sliding mode surface according to the defined output tracking error, the nonlinear function and the fractional order calculus; and in combination with the nonlinear fractional order sliding mode surface, the super-spiral approaching rate, the super-local model and a time delay observer, a model-free controller of the super-spiral nonlinear fractional order sliding mode is built, and buffeting in the control process is suppressed. According to the design of the nonlinear fractional order sliding mode surface, the stability of control is ensured, the convergence speed is high, the steady-state error and the saturation error are reduced, and the shaking problem of the sliding mode surface is improved through the combination of the super-spiral approaching rate.

The invention discloses a gravel multi-stage screening device for building construction. The gravel multi-stage screening device for building construction structurally comprises a bottom plate, a shell, a vibration device, a vibration cavity, a supporting column, a conveying belt, a guide plate, a first hopper, a first through hole, an opening and closing device, a stone outlet, a discharging plate, a sand aggregate outlet, a discharging trolley, a second hopper, a first supporting plate, a partition plate, a second supporting plate, a second through hole, a discharging opening, a third through hole and a sliding groove; the bottom plate is vertically mounted at the bottom of the shell through a welding connection manner. According to the gravel multi-stage screening device for building construction, the vibration device is arranged on a left side plate of a screening frame, a motor in the vibration device moves at the high speed, the rack is driven to do reciprocated motion, under theeffect of the rack, the screening frame does the left and right reciprocating motion, shaking between gravel on a screen net can be accelerated, separation between the gravel can be accelerated, stone and sand aggregate are discharged from different outlets, the separation manner is efficient, operation is easy and convenient.

Disclosed herein are a Bluetooth signal receiving device and a Bluetooth Smart receiving method. The Bluetooth signal receiving device includes a frequency shift demodulator circuit, a sampler circuit, a training bit pattern discriminator circuit, and a symbol timing offset compensation circuit. The frequency shift demodulator circuit generates a baseband signal by performing frequency shift modulation on a received signal. The sampler circuit samples the baseband signal based on a symbol timing, and generates a plurality of series of bit streams based on sampled values. The training bit pattern discriminator circuit determines whether the plurality of series of bit streams generated by the sampler circuit satisfies a training bit pattern condition. The symbol timing offset compensation circuit compensates the symbol timing of the baseband signal based on a measured error metric as an effective error metric if the plurality of series of bit streams satisfies the training bit pattern condition.

The invention discloses a laser trigger vacuum switch and a trigger system apparatus thereof. The laser trigger vacuum switch comprises a closed housing, a first electrode main member and a second electrode main member. The first electrode main member comprises an arcing electrode, a first electrode flange, a first electrode platform and a focusing mirror. The second electrode main member comprises an arcing electrode, a second electrode flange, a second electrode platform and a target electrode. The trigger system apparatus mainly comprises a computer, a converter, a switch circuit board, a laser and the laser trigger vacuum switch. The laser trigger vacuum switch has a working voltage as high as 30 kV and a working current as high as 500 kA. The problems of difficult trigger high voltage isolation, trigger stability, short service life and the like by use of electric pulses in the prior art are solved, the laser trigger energy can be effectively reduced, and the time delay and jittering of a switch device are improved. The laser of the trigger system apparatus realizes miniaturization completely, a matched laser system is greatly simplified, and a special power supply device, a special water cooling machine and a special laser collimation system are unnecessary.

The invention discloses an easily cleaned outdoor deinsectization lamp which comprises a deinsectization mechanism and a solar panel, wherein the deinsectization mechanism sequentially comprises a hanging part, a swinging part, a phototatic electric shock part and an accommodating part from top to bottom; the phototatic electric shock part comprises a top cover and a phototatic lamp; a circle of vertical high-voltage electric shock net is arranged at the external part of the phototatic lamp and around the periphery of the phototatic lamp; a circle of insulation ring is connected onto the high-voltage electric shock net in a sleeving manner; an extension spring is arranged between the top end of the insulation ring and the top cover; two doctor bars are oppositely arranged on the bottom end face of the insulation ring; an electric net gap is reserved between the two doctor bars. The solar panel is simple in structure and low in cost, can fulfill the purpose that the volume is automatically increased along with increase of injurious insects, realizes an accommodating structure with a variable volume, reduces the replacement times of the accommodating structure, and is rainproof; the swinging part automatically vibrates with wind, is large in vibration amplitude, and can shake off injurious insects adhered to the electric net; the deinsectization efficiency of the easily cleaned outdoor deinsectization lamp is affected if too many injurious insects are adhered to the electric net.

The invention provides a synchronous control method for multiple TDI CMOS imaging systems, relates to an aerospace application-based synchronous control method for multiple TDI CMOS imaging systems, and aims at solving the problem that when existing imaging systems are subjected to imaging control, the sampling metastate exists. According to the method, a single low-frequency crystal oscillator passes through a clock divider, then is fed into external clock frequency multipliers and jitter clearers and finally is fed into various imaging units; and by testing the metastate area of sampling andadjusting the rising edge of a clock frequency divider reset signal, the robustness of control signal sampling is guaranteed; by conducting dejitter and frequency multiplication on low-frequency clock signals near imaging controllers, increase of amplitude attenuation and jitter of high-frequency clocks is avoided, and then stable and reliable receiving of high-speed serial data is guaranteed; and by testing the metastate area of sampling and adjusting the rising edge of the clock frequency divider reset signal, the robustness of control signal sampling is guaranteed, and a detector can always stably work under various temperature conditions.