The invention belongs to the field of digital communications and digital storage, and discloses a delay-adjustable encoding method. The method comprises the following steps: I, configuring a delay parameter B, wherein B is a positive integer; II, taking an information sequence underlined-u<(t)> of which a length is BK, and blocking the sequence into underlined-u<(t)>=(underlined-u<0><(t)>, underlined-u<1><(t)>, . . ., underlined-u<B-1><(t)>), wherein a length of underlined-u<(t)> (0<=i>=(B-1)) is a positive integer K; III, encoding the information sequence underlined-u<(t)> into a code word underlined-v<(t)> through a linear block code encoder to obtain a symbol sequence underlined-v<(t)>=(underlined-v<0><(t)>, underlined-v<1><(t)>, . . ., underlined-v<B-1><(t)>) of which a total length is BN, and storing the symbol sequence in a register I, wherein a length of underlined-v<(t)> (0<=i>=(B-1)) is a positive integer N; and IV, setting underlined-c<(t)>=underlined-v<(t)> xor pi(underlined-v<(t-1)>), wherein pi(underlined-v<(t-1)>) is a code word obtained after symbol interleaving through an interleaver pi, storing the pi(underlined-v<(t-1)> in a register II, inputting the underlined-v<(t)>=(underlined-v<0><(t)>, underlined-v<1><(t)>, . . ., underlined-v<B-1><(t)>) into the interleaver pi to perform interleaving, and writing an interleaved sequence into the register II. The method is simple in steps, convenient to implement, and low in complexity. Different delays can be met under the situation of ensuring a fixed code rate through simple configuration without changing a basic encoding and decoding hardware module for linear block codes, so that a compromise between delay and performance can be realized.