86results about "Codes simulation/testing" patented technology

The invention relates to the technical field of computers, and discloses an information source coding matrix data processing method based on a modified conjugate gradient algorithm. According to the method, sparsity constraint and a fixed-point quantization mechanism are fused in iterative optimization, and a sparse fixed-point coding matrix meeting hardware deployment requirements is directly generated through gradient shielding, correction conjugate parameter calculation and Armijo criterion line search and synchronous execution of hard threshold sparseness and fixed-point quantization after each update. According to the method, the sparsity constraint and the fixed-point quantization mechanism are embedded in the iteration process of the modified conjugate gradient algorithm, so that end-to-end alignment of coding matrix optimization and hardware deployment requirements is realized.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

The invention provides a decoding method of a low-density parity check code, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a processor model of a user terminal, and matching system computing power information corresponding to the processor model; obtaining a first case decoding time corresponding to a low density parity check (LDPC) decoding test case; and obtaining the maximum number of iterations according to the system computing power information and the first case decoding time, and performing LDPC decoding based on the maximum number of iterations when the to-be-decoded data is received. According to the LDPC decoding method and device, the maximum number of iterations is cooperatively determined in combination with the two aspects of system computing power information and use case decoding time, LDPC decoding is carried out through the maximum number of iterations, the requirement of a communication system for communication performance is met, the error rate of LDPC decoding is reduced to a certain extent, and therefore the number of retransmission times of data is reduced.

The invention provides a confusion matrix scoring method and device based on entropy coding, and relates to the technical field of machine learning. The method comprises the following steps: acquiring an original confusion matrix; setting an element in a main diagonal line of the original confusion matrix to be zero to obtain an error matrix; binary entropy coding is carried out on terms of the error matrix in an entropy coding mode, and a coding matrix is obtained; calculating the code length of each code in the coding matrix according to the coding matrix to obtain a code length matrix; multiplying each item of the code length matrix by each item of the error matrix to obtain an average code length matrix; summing each item of the average code length matrix to obtain a total average code length; and the value of the total average code length is used as a scoring index. According to the invention, the error rate and the dispersity of error conditions can be reflected.

The invention relates to an eight-ring QC-LDPC (Quasi-Cyclic Low Density Parity Check) code construction method based on a subtraction construction search algorithm. According to the method, a first row is fixed by using a Golomb Ruler sequence, the last two rows are obtained by using a search algorithm constructed based on subtraction to form an index matrix meeting a condition without 4 and 6 rings, and finally, the index matrix is correspondingly expanded to obtain a parity check matrix of the index matrix, so that four rings and six rings do not exist in a Tanner graph of the check matrix, the required storage space is small, and hardware implementation is easy. A simulation result shows that compared with an SS-QC-LDPC code, a DDS-QC-LDPC code, a GR-QC-LDPC code, an LETS-QC-LDPC code and a GRS-QC-LDPC code which have the same code rate and code length, the SC-QC-LDPC code constructed by the method has the advantages that the net coding gain is improved to a certain degree, and the constructed SC-QC-LDPC code has better waterfall region performance in a high signal-to-noise ratio region and has no obvious error leveling phenomenon.

The present invention provides a method and device for high-speed LDPC decoding of broadband signals with low computing power requirements, relating to the field of radio monitoring. This method addresses the issues of long processing time, high resource consumption, and difficulty in engineering implementation of current LDPC code decoders. The method comprises: buffering data frames and serially reading and processing adjacent codewords in the data frames to be decoded after configuration; determining long codewords and designing control logic timing; and achieving multi-path concurrent processing of long codewords under low computing power requirements through soft switching of parallelism parameters. The method also includes designing a concurrent decoding processing path and iteratively updating variable nodes and check nodes based on an improved NMSA decoding algorithm. After satisfying the iterative stopping strategy, a decoded bit sequence for the long codeword is obtained, forming a decoding result under low computing power requirements. The present invention has the characteristics of low processing latency, low resource consumption, and is suitable for practical use environments. It can effectively improve the decoding processing rate and decoding data throughput of satellite signal monitoring.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

The application relates to the field of signal processing and discloses a unified probability graph computing architecture power consumption optimization method, system, medium and equipment, which comprises the following steps: a unified probability graph for multiple tasks is used to perform sparse optimization on message passing data flow by dynamically regulating the message passing data flow in a probability iteration calculation process; and based on the optimized message passing data flow, the activation state of a memory-computing integrated array node is dynamically selected by a computing circuit of a memory-computing integrated characteristic device to improve the adaptability of the computing architecture and hardware resources. The application reduces the calculation-storage scale by deleting probability messages with low reasoning contribution and dynamically regulating the message passing data flow in the probability iteration calculation process, and the adaptability of the computing architecture and hardware resources is improved by dynamically selecting the activation state of the memory-computing integrated array node, so that the power consumption is further reduced.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

This invention relates to the field of computer technology and discloses a method for processing source coding matrix data based on a modified conjugate gradient algorithm. This method integrates sparsity constraints and fixed-point quantization mechanisms in iterative optimization. Through gradient masking, modified conjugate parameter calculation, and Armijo criterion line search, and by synchronously performing hard-threshold sparsification and fixed-point quantization after each update, it directly generates a sparse fixed-point coding matrix that meets hardware deployment requirements. This invention achieves end-to-end alignment between coding matrix optimization and hardware deployment requirements by embedding sparsity constraints and fixed-point quantization mechanisms within the iterative process of the modified conjugate gradient algorithm.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

When a state machine of the time sequence circuit is influenced by a single event upset (SEU) effect, a state code of the state machine is very easy to change, so that the state machine is in an invalid or error state and cannot be recovered, and the function of the time sequence circuit is failed. Aiming at a state machine based on Hamming distance-3 coding, the invention provides the low-overhead error detection circuit for the Hamming distance-3 five-bit state code, and the resource overhead in the error detection process is greatly reduced by simplifying the judgment logic of a detection unit.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

The application discloses a decoding reliability analysis method and device, an electronic device and a storage medium. The analysis method comprises the following steps: obtaining the number of bits of a decoding result, performing extension processing on a preset matrix array in a target encoding matrix based on the number of bits, determining a decoding output matrix based on the preset matrix array after the extension processing and an input decoding matrix, performing decoding decision on the decoding output matrix to obtain a decision output result, and analyzing the reliability of the decoding result based on the decision output result and decoding noise power. The application solves the technical problem that the decoding processing mode used in the related art is not accurate in judging the reliability of the decoding result.

The present application takes the position closed structure and the orthogonal component difference as the core, converts the information to be processed into the residual structure representation under the background reference state constraint, the background reference state is constructed by the receiving and transmitting parties according to the consistent generation rule, and can be used as the structural key or the key derivation reference in the safe scene, so that the transmission and storage load can be concentrated on the residual field and the necessary auxiliary field. The framework uniformly carries the encoding, compression, encryption, inversion, decoding and structured domain calculation and topological consistency reasoning, realizes the integration of compression and encryption, storage and calculation. The system improves the equivalent storage density and energy efficiency performance through structured aggregation, and provides consistent logical pointing and calculation basis for reconstruction and reasoning.

A method to build a lookup decoder for mapping error syndromes based on quantum-stabilizer code to corresponding error corrections comprises (A) enumerating a subset of error syndromes up to a maximum error weight based on the quantum-stabilizer code; (B) iterating through the subset of error syndromes to compute an error state of highest probability for each error syndrome of the subset, where the error state defines error in a qubit register of a quantum computer; and (C) for each error syndrome of the subset of error syndromes, storing in classical computer memory an error correction based on the error state of highest probability and mapped to that error syndrome.

A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

The invention discloses an analog circuit implementation method and device based on a unified probability graph computing architecture, equipment and a medium, and the method comprises the steps: building a unified signal model based on the common characteristics of a baseband signal processing task; representing the unified signal model as a unified probability graph model; obtaining an initialization probability of a variable node state value in the unified probability graph model; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, and node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; a driving vector is obtained based on the initialization probability to serve as input of the initial input array, the iterative calculation array is used for completing iterative calculation of mutual message passing of variable nodes and check nodes in the unified probability graph model, and when an iteration stop condition is met, the result output array outputs a processing result to complete a baseband signal processing task.

Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

The present disclosure relates to a method for designing a base graph of a low-density parity-check code in a communication system, said base graph, and an encoding / decoding method and apparatus therefor. A communication device for performing encoding by using an LDPC code in a communication system, according to an embodiment of the present disclosure, may: identify a base graph to be used among a first base graph and a second base graph of the LDPC code, on the basis of the length and a code rate of information to be transmitted; and when the identified base graph is the second base graph, identify a plurality of index values constituting a parity check matrix on the basis of the second base graph. The plurality of index values are identified on the basis of row indices and column indices of a matrix corresponding to the second base graph, and lifting set indices for lifting of the base graph, and index values corresponding to at least one column index mapped to a specific row index among the row indices may be further used for the encoding.

Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

The application belongs to the technical field of integrated circuits, and discloses a cracking method of an integrated circuit encryption circuit state machine, which comprises the following steps: 1, applying excitation to a netlist to extract information; 2, regarding the process of solving a key as a process of state machine reconstruction, and converting the problem into a constraint programming problem; 3, if the number of keys solved by the CP-SAT solver is 1, the attack is ended, and the unique correct key is obtained, otherwise, timing equivalence checking is performed by using Synopsys VC Formal SEQ Application, and further incorrect keys are excluded in combination with Oracles until the unique correct key or multiple equivalent keys are obtained. The attack duration of the application mainly depends on the size of the state machine and the inherent jump relationship in the state machine, and the attack time is short and the efficiency is high.

An estimation apparatus including a controller that reads information from a storage that stores a set of code and parameter used for communication and information indicating performance requested to achieve predetermined communication quality in communication using the code and parameter in association with each other, and estimates an SNR to be requested in an MLC (Multilevel Coding) using the code and parameter indicated by the inputted information.

A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

The embodiment of the invention provides a binary linear code decoding method and device and a storage medium, and the method comprises the steps: receiving channel soft information, obtaining a check matrix, carrying out the hard decision of the channel soft information, obtaining a receiving sequence and a syndrome, and carrying out the decoding of a binary linear code if the value of the syndrome is not a zero vector. And sorting the receiving sequence and the check matrix according to the reliability of the channel soft information to obtain the sorted receiving sequence and check matrix. Performing XOR operation on column elements of the sorted check matrix corresponding to the test error mode generated according to the logic weight and the syndromes to obtain test error mode syndromes, and if the values of the test error mode syndromes are all not zero vectors, disturbing channel soft information by using disturbance noise, and if the values of the test error mode syndromes are not zero vectors, disturbing channel soft information; and repeatedly performing hard decision on the channel soft information to obtain a receiving sequence, a syndrome and a subsequent process. The decoding method provided by the invention is relatively low in overall decoding complexity, does not depend on the structure of a linear code, and has good universality.

Systems, methods, apparatuses, and computer program products for error probability feedback are provided. A method may include: sending a configuration for protocol data unit error probability calculation and reporting to at least one user equipment. The method may further include receiving feedback related to the protocol data unit error probability from at least one user equipment.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.