942 results about "Check digit" patented technology

A method for securing financial transactions involving payment cards includes associating a sixteen-digit personal account number (PAN) with a particular payment card and user, wherein are included fields for a system number, a bank/product number, a user account number, and a check digit. A four-digit expiration date (MMYY) associated with the PAN. A magnetic stripe on the payment card is encoded with the PAN for periodic reading by a magnetic card reader during a financial transaction. A table of cryptographic values associated with the PAN and the MMYY is stored on each user's payment card during personalization by an issuing bank. A next financial transaction being commenced with the payment card is sensed. A cryptographic value from the table of cryptographic values is selected for inclusion as a dynamic portion of the user account number with the PAN when a next financial transaction is sensed. Any cryptographic value from the table of cryptographic values will not be used again in another financial transaction after being used once. The issuing bank authorizes the next financial transaction only if the PAN includes a correct cryptographic value in the user account number field.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

The invention discloses a polarization code and multi-bit even parity check code cascaded error correction coding method. The method comprises the steps: a transmitting end encoder utilizes a multi-bit even parity check code as an outer code, and utilizes a polarization code as an inner code; a receiving end decoder decodes by utilizing a modified successive cancellation list (SCL) decoding algorithm. On the aspect of error correction performance, comparing with the prior art utilizing middle-short code length non-cascaded polarization codes of the SCL decoding algorithm, the polarization code and multi-bit even parity check code cascaded error correction coding method has the advantages that frame error rate performance of a system can be remarkably improved, and a maximum likelihood bound (ML Bound), which cannot be broken through by the SCL decoding algorithm, can be remarkably broken through. On the aspect of engineering realization, according to the polarization code and multi-bit even parity check code cascaded error correction coding method, the outer code utilizes the multi-bit even parity check code, which is simple to code; the modified SCL decoding algorithm is utilized to decode, bit decision and even parity check are combined to be carried out in a decoding process, and compared with the original SCL decoding algorithm, the method provided by the invention does not increase the decoding complexity, and facilitates the engineering realization.

Provided are a transmitting apparatus, a receiving apparatus and methods of puncturing and depuncturing of parity bits. The transmitting apparatus includes: a zero padder configured to pad at least one zero bit to input bits; an encoder configured to generate a Low Density Parity Check (LDPC) codeword by performing LDPC encoding with respect to the bits to which the at least one zero bit is padded; a parity interleaver configured to interleave LDPC parity bits constituting the LDPC codeword; and a puncturer configured to puncture at least a part of the interleaved LDPC parity bits based on a pre-set puncturing pattern.

An information processing device regarding which access to data held by the information processing device itself, in multiple regions, is requested from another information processing device, includes: an authenticating unit to perform authenticating processing of the other information processing device; a receiving unit to receive an access license ticket including an access code and a check digit; an access license ticket generating key generating unit to generate an access license ticket generating key, which is key information for computing a check digit using data held beforehand, a root key, an access control key, and other key information which is key information to manage data of a region other than the predetermined region, corresponding to an access code; check digit computing unit to compute a check digit corresponding to the access code described in the access license ticket; and access license ticket validating unit to validate the access license ticket.

The invention relates to the technical filed of the error correction and coding of communication and information systems and discloses a method for generating a quasi-cyclic low density parity check code. The method comprises the following steps: according to the requirements on code rate and code length of the low density parity check code to be designed and system requirements, determining a degree distribution sequence which is selected by adopting a density evolution method; setting the column weight of each column of a basic matrix according to the selected degree distribution sequence; setting the positions and values of non-zero elements in each column in the basic matrix according to the column weights of the basic matrix to obtain the basic matrix; and expanding the obtained basic matrix into a check matrix. At the same time, the invention also discloses a method for coding the quasi-cyclic low density parity check code and provides corresponding devices. The methods and the devices provided by the embodiment of the invention enable finally obtained code words to effectively reduce influences of cycle overlapping.

A packet including data and a cyclic redundancy check code is encoded by using a selectable one of N scrambling codes (N>1). The encoded packet is transmitted and received, then decoded N times by using the N scrambling codes. The cyclic redundancy check code is used to decide which one of the N scrambling codes enabled the encoded packet to be decoded correctly, and the correctly decoded data are used. Packets with different formats, in particular with headers of different lengths, can be distinguished by the use of different scrambling codes, so that different formats can be employed without the need to transmit extra data to indicate which format has been used.

The invention is suitable for the memory field, and provides an NAND flash memory as well as a data checking method and device thereof. The method comprises the following steps: checking the row and the column of each 256-byte datum written to an NAND flash memory file to generate a first check code; checking the row and the column of each 256-byte datum read from the NAND flash memory file to generate a second check code; and processing the first check code and the second check code by XOR treatment, and determining whether the datum in the NAND flash memory has a fault according to the XOR treatment result. According to the embodiment of the invention, the method can check the data in the NAND flash memory in the software form, and is suitable for any platform.

The invention discloses a laminated and partitioned irregular low density parity check (LDPC) code decoder and a decoding method in the technical field of communication. An external information storage unit outputs a soft value transmitted to an information node by a last iterated check node to a decoding processing module. A cyclic shift register transmits a posterior probability likelihood ratio update value of the information node to the decoding processing module. The decoding processing module transmits the check update value in the iteration to the external information storage unit, andsimultaneously transmits the posterior probability likelihood ratio update value of the information node to the cyclic shift register through a decoding processing module interweaving network. The decoder is suitable for decoding all quality control (QC) LDPC codes, and all the partitioned LDPC code words support decoding; the decoder has no stream competition conflict, and has better throughput performance and relatively simple working time sequence; and the consumption of the interweaving network of huge resources is not needed, many hardware resources are saved, and the resource consumption of the whole decoder is relatively low. The decoding supporting parallelism degree can be flexibly changed.

The invention relates to an on-line error correcting device for faults by parity check codes and a method thereof, belonging to the field of on-line test. The invention solves the problem of huge redundant cost when traditional error correcting codes are used for the on-line test for an embedded memory. The on-line error correcting device for faults comprises two processes of error detection and error correction, wherein the error detection comprises the following steps of: detecting whether new addresses are input or read-write signals are changed; calculating check codes for data; reading the data and comparing the data with memorized check codes; writing a compared result in a fault flag bit memory; and respectively writing fault addresses and the error correcting codes in corresponding memories. The process of the error correction comprises the following steps of: detecting whether the new addresses are input or the read-write signals are changed; judging fault flag bits; and searching the error correcting codes. By using the invention, the on-line test is carried out for the embedded memory under the condition that the memories are not changed to memorize data and the normal read-write operation of the memories is not influenced, and all the faults of odd numbers are detected.

The invention discloses a method for storing real-time data, which comprises the following steps: the data of a storage sensor is collected by a collector in real time; the summary information of a main index is accessed, checked and compared; the latest indicator of the main index content is extracted; the latest storage indicator of the data is accessed; data content and a check code are stored; new index content and the check code are calculated; the main index content and the check code are stored; main index summary is updated and stored; backup index content and the check code are stored; backup index summary is stored; the backup index summary is accessed and then checked and compared; the latest indicator of the backup index is acquired; the latest storage indicator of the data content is accessed; and storage information is reestablished. Double indexes and multiple checks are adopted for protecting the data in a storage unit, thus guaranteeing the complete content of the data stored in the collector. Cycling coverage is adopted for realizing the continuous storage of data content under fixed storage capacity, improving the reliability and completeness of important parameter record during the industrial process and promoting the operation efficiency of process monitoring and work safety.

The invention discloses an encrypted domain lossless reversible information concealing method based on a carrier image check code. The method comprises the steps of (1) dividing an original carrier image into a first carrier sub-image and a second carrier sub-image, encoding the first carrier sub-image, embedding a check code corresponding to the first carrier sub-image into the second carrier sub-image, encrypting the carrier image containing the check code, and obtaining a encrypted ciphertext carrier image containing the check code; (2) dividing the encrypted ciphertext carrier image containing the check code, carrying out different overturn computing on negative three bits of an first encrypted carrier sub-image according to secret data to be embedded, embedding the secret data, and obtaining a ciphertext carrier image containing the secrete data; (3) decoding a plaintext domain carrier image containing the secret data, abstracting the secret data in the decrypted plaintext domain carrier image, and recovering an original carrier image. According to the method, the secrete data are embedded in the ciphertext carrier image, and the method ensures that the original carrier image is recovered in a lossless mode while the secret data are subjected to plaintext abstraction.

The present invention relates to a high-capacity FLASH solid-memory controller, and comprises a data cache unit, a checking code cache unit, a checking code generating and correcting unit, a bad block auto-processing unit and a dual cache control unit. The checking code generating and correcting unit is used for receiving the data transmitted from an external microcontroller through the microcontroller interface, generating the checking code according to the received data, and transmitting the data and the checking code to the dual cache control unit. The data transmitted from the dual cache control unit are corrected and are transmitted to the external microcontroller through the microcontroller interface. The bad block auto-processing unit is used for automatically identifying the bad memory block in an external FLASH memory, and distributing the replacement block, so as to guarantee the regular reading and writing of the external FLASH memory. The high-capacity FLASH solid-memory controller can be operated without the user. The dual cache control unit is communicated with the microcontroller interface, the FLASH interface or the bad block auto-processing unit, so as to realize the data writing or reading of the data cache unit and the checking code cache unit.

The invention discloses a decoding early termination method for low-density parity check codes. The method is characterized in that for a decoder utilizing belief propagation decoding algorithms, every time an iterative computation of side information which variable nodes transmit to check nodes is performed, firstly computed coding hard decision bits of every variable node is carried to the front of the most significant bit or the back of the least significant bit of the side information transmitted from the variable nodes to the check nodes which are connected with the variable nodes on bipartite graphs, accordingly combined information is formed and transmitted to the check nodes; and while information transmitted from the check nodes to the variable nodes is computed, every check node extracts the coding hard decision bits from the combined information transmitted from the variable nodes which are connected with the check nodes on the bipartite graphs and performs syndrome computation: if all syndromes are zero, the iterative decoding is terminated early. The decoding early termination method for the low-density parity check codes can guarantee the accuracy of decoding and simultaneously reduce the working time delay of the decoder as much as possible, thereby improving the working efficiency.

The invention relates to a quasi-cyclic low-density parity-check (QC-LDPC) code and a correcting and linear coding method thereof. The variable nodes of the LDPC code, the dimensionality of which is greater than 2, are informational nodes; and the variable nodes the dimensionality of which is 2 form a big end-to-end ring on a bipartite graph. The correcting method comprises the following implementation steps: randomly selecting one edge on the big ring the dimensionality of which is 2, cutting off the edge, and filling 0 in the corresponding position of a low-density check matrix, thereby acquiring a corrected structure of the code. The linear coding method of the corrected code comprises the following implementation steps: firstly, multiplying an input information vector s and a part of the check matrix the load of which is greater than 2 as a vector by a matrix to acquire an intermediate vector u; directly intercepting the corresponding position of the intermediate vector u to acquire a coding vector the variable node dimensionality of which is 1; computing bit by bit from a start bit according to the characteristics of the big ring on the bipartite graph to acquire a coding vector the variable node dimensionality of which is 2; and combining the two coding vectors to finally form a coding vector.