71 results about "Check digit" patented technology

The application discloses an encryption method fusing quantum key and post-quantum cryptographic algorithm, and belongs to the technical field of data encryption. The original quantum key is generated by a BB84 protocol QKD device, and a post-quantum key generation seed, a lattice noise scaling factor and a quantum enhanced session base key are obtained through hash derivation; quantum derived mask is generated by combining the original quantum key and the operation data characteristics of the water and power terminal; the quantum mask protection data is obtained by performing XOR preprocessing on the data to be encrypted; based on the post-quantum encryption algorithm, the two-part basic ciphertext is generated by using the above-mentioned seed, parameters and protection data; the original quantum key is divided into pieces to obtain quantum enhanced encryption values, and the two-part ciphertext is subjected to secondary disturbance encryption and XOR processing, thereby forming enhanced ciphertext; and finally, the enhanced ciphertext and the check code are spliced and transmitted to the central control room. Through multi-level encryption and key enhancement, the security and attack resistance of data transmission in the water and power terminal and the like are significantly improved.

The application provides a recognition method and device of a recognition code, the method comprising: recognizing an ID code point in a data area of the recognition code and a check code point of a check area on the recognition code, obtaining first pixel coordinates of the ID code point and second pixel coordinates of the check code point; obtaining third pixel coordinates of the check code point corresponding to the ID code point according to the first pixel coordinates; and determining that the recognition code is recognized in the case that the second pixel coordinates are the same as the third pixel coordinates, solving the problem of low recognition accuracy of the recognition code in the related art, and improving the recognition accuracy of the recognition code by recognizing the recognition code through the ID code point of the data area and the check code point of the check area.

The present application provides a data storage device and a method for generating a check code, wherein the data storage device comprises a controller and a non-volatile memory, the non-volatile memory is used to store a plurality of instructions, and the controller is used to execute the plurality of instructions to implement the method for generating a check code, which comprises: judging a minimum unit of the non-volatile memory using a check code; dividing the minimum unit into at least two sub-units; and respectively performing error correction code encoding operations on the at least two sub-units to generate sub-check codes. In this way, data storage devices with different capacities have the same decoding capability.

The disclosure provides a database consistency verification method and device, electronic equipment and computer readable storage medium, and relates to the field of databases. The database consistency verification method comprises: in response to a verification instruction, performing a verification operation on a first backup library and a second backup library based on a checksum algorithm, wherein a reference code is generated based on the verification operation for the first backup library, and a verification code is generated based on the verification operation for the second backup library; determining the consistency between the first backup library and the second backup library based on the comparison result of the reference code and the verification code; and determining the consistency between the master library and the backup library based on the consistency between the first backup library and the second backup library. Through the technical scheme of the disclosure, the consistency verification can be performed while ensuring the normal operation of the master library, which is conducive to reducing the probability of intrusion into the database, thereby ensuring the high availability and strong consistency of the database.

The application discloses a CXL module, an error correction method and a medium, and relates to the technical field of data access, wherein the CXL module comprises a controller and a memory bank connected with the controller, and a plurality of memory particles are arranged on the memory bank; wherein the controller is configured to perform ECC encoding on 512-bit data to be written, generate a check code smaller than or equal to 32 bits, write the 512-bit data to be written and the check code into the memory bank through one burst, read out the 512-bit data to be written and the check code from the memory bank through one burst, and perform error correction processing on the 512-bit data to be written based on the check code; wherein the check code can correct errors of more than 2 bits. The CXL module has higher error correction capability under the premise of paying a smaller capacity cost.

This invention discloses an attack tracing method and system for end-to-end data transmission in optical communication, belonging to the field of optical fiber communication technology. The method includes: processing an initial key value using a hash function and DNA encoding to generate a DNA sequence; concatenating the DNA sequence to generate a session key and calculating its hash value; calculating a single-byte XOR checksum of the original data to generate extended data, generating ciphertext based on the extended data, and calculating a digest of the ciphertext; decrypting the ciphertext and performing XOR checksum consistency verification to obtain an event digest; calculating a root hash based on the key digest, parameter digest, ciphertext digest, and event digest, storing the root hash in the block header, and performing attack tracing on the block header to obtain the attack tracing result. This invention introduces four-dimensional chaos and DNA encoding to generate a high-entropy key, dynamically storing and updating the key through blockchain, while simultaneously achieving single-root verifiable attack tracing and quickly locating problematic nodes.

The application provides a decoding method, an encoding method, a device, a chip and a computing device. The method comprises the following steps: a decoding device acquires a first matrix, and then decodes a first code word vector according to the first matrix to obtain a decoding result. The first matrix is a 0-1 matrix representing elements in a second matrix on a polynomial ring. The second matrix is a check matrix on a finite field 2q, and the number of rows is r and the number of columns is n. A first polynomial corresponding to the polynomial ring is a q-th irreducible polynomial on a binary field. The number of 1s in the first matrix is less than the number of 1s in the 0-1 matrix representation of the second matrix. The first code word vector comprises k information code elements and r check code elements, and n=k+r. Each code element comprises q data units, and each data unit comprises at least one bit. The scheme can effectively reduce the hardware implementation complexity and cost of RS encoding and decoding.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This specification discloses a method for air-to-ground transmission of flight record data with high temporal integrity, comprising: encapsulating target data to obtain a data assembly containing a header information portion, a data content portion, and a tail information portion; enabling the ground subject to perform data verification operations based on the header information portion and / or the tail information portion after receiving the data assembly; comprising: decomposing the target data into data packets; calculating the feature value of any data packet and determining the flag bit of the data packet for each data packet; setting the header information portion of the first data packet to preset information for the first data packet; using the feature value and flag bit of the previous data packet as the header information portion for any non-first data packet; generating a check code corresponding to the combination of the header information portion and the data content portion as the tail information portion; and forming a data assembly containing the header information portion, the data content portion, and the tail information portion.

A decoder (30) for decoding low-density parity-check (LDPC) codewords. The decoder includes at least one core (10) and a memory (20) in which a number NC of predefined configurations are stored. The core is suitable for being dynamically configured with any one of the predefined configurations stored in the memory to decode an LDPC codeword using this configuration. The predefined configurations form a sub-group, in the strict sense, of 5G LDPC configurations defined in the 3GPP TS 38.212 standard. Each configuration corresponds to a triplet of three parameters {K, R, Z}, and to a parity matrix constructed according to at least a portion of these parameters. K is a message size encoded by the LDPC code, Z is an expansion factor of the parity matrix, and R is a code rate of the LDPC code.

The present disclosure relates to a data transmission method, device, electronic equipment, computer readable storage medium and system on chip, comprising: a local corelet adaptation layer encapsulates first to-be-sent data into first fixed-length data packets; the first fixed-length data packets are encrypted to obtain first encrypted data packets; the first encrypted data packets are sent to the adaptation layer of a remote corelet; the adaptation layer of the remote corelet decrypts the first encrypted data packets to obtain first decrypted data packets; a first error detection check code is obtained from the first decrypted data packets; the first error detection check code is checked; in the case that the first error detection check code is correct, the adaptation layer of the remote corelet confirms to correctly receive the first to-be-sent data. The present disclosure can be compatible with UCIe protocol and can protect the data information transmitted on the data link, can prevent external theft of the effective content of the transmission information between corelets, and is helpful to improve the security of the transmission information between corelets.

A method and system for decoding low density parity check (LDPC) codes. A method includes performing block parallel processing that initiates processing all non-zero block columns of a plurality (M) of rows of a layer of an LDPC matrix in each clock cycle, where M≤p, and p is a total number of rows in a layer of the LDPC matrix; and updating a P message responsive to determination of a final state for each row of the LDPC matrix. The LDPC matrix includes layers, each comprising a plurality (M) of rows that are processed per clock cycle. Each of the plurality of rows of each of the layers is datawise independent of the rows processed during a previous NP_MAX clock cycles and at least one row in each layer is datawise dependent on a row of an immediately preceding layer, and NP_MAX is greater than one.

The application discloses a kind of transformer assembly state traceability system, it is related to transformer production assembly technical field.The product identity mark module of the present application generates unique product identity code and establishes digital archives;Data acquisition terminal collects each process assembly process data;Quality determination module carries out quality score to assembly process by improved CNN-LSTM algorithm, and outputs qualification determination and score;Logic correlation processing module binds product identity code with quality score in real time, and generates process state data package with time stamp and check code;Time series traceability chain construction module forms full-process traceability chain by double-checking mechanism, and data package is connected in chain hash structure to realize traceability chain update synchronization and tamper-proofing;Data storage module hangs traceability chain to corresponding digital archives, using hot and cold separation storage strategy, provide bidirectional traceability query interface.The present application realizes the full life cycle traceability of transformer assembly state, and has wide application value.

The application provides a cloud database built-in system account anti-tampering protection system, an anti-tampering protection method, an electronic device and a storage medium, and relates to the technical field of database information, and comprises a trigger code generator module for automatically generating trigger code and calculating a first check code; a metadata management module for managing system account information and storing the first check code; a trigger code check module for calculating a second check code and comparing the second check code with the first check code; a trigger code recovery module for regenerating trigger code and covering the tampered trigger code; and an account recovery module for recovering the tampered system account and the corresponding permissions. The application prevents the trigger code from being tampered by using the trigger check code, and has the functions of trigger code automatic recovery, system account tampering behavior interception, system account automatic recovery and the like, so that the multiple anti-tampering and automatic recovery mechanisms of the built-in account of the cloud native database are realized.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This invention discloses a checksum update method, apparatus, electronic device, storage medium, and product, relating to the field of data storage technology. The checksum update method includes: determining a checksum pair of data to be updated, a data identifier, and the current checksum of the disk; splitting the current checksum according to a preset bit width to obtain split checksum components, and splitting the checksum pair to obtain data checksum components; and incrementally updating the checksum components based on the checksum components, the data checksum components, and the data identifier to obtain a new checksum for the disk. This invention enables incremental checksum updates, eliminating the need to reread all data on the disk, significantly reducing data read / write operations and computational overhead, and improving checksum update efficiency in storage scenarios.

The application discloses a transceiving system with a multiplexing FIFO, which comprises a multiplexing FIFO, a sending buffer control module and a receiving buffer control module. The sending buffer control module is used for controlling the conversion of the to-be-sent message data into corresponding symbol codes according to a first preset data coding format and buffering the symbol codes in the multiplexing FIFO; the sending buffer control module is also used for calculating a check code, controlling the conversion of the check code into corresponding symbol codes according to the first preset data coding format, controlling the BMC coding of the symbol codes and the corresponding symbol codes of the check code buffered in the multiplexing FIFO, and sending the coding result to a CC line. The receiving buffer control module is used for receiving the coding result from the CC line and performing BMC decoding to obtain corresponding symbol codes; the receiving buffer control module is also used for converting the to-be-received data packet into the second preset data coding format and buffering the to-be-received data packet in the multiplexing FIFO; and the receiving buffer control module is also used for reading the to-be-received data packet from the multiplexing FIFO and performing a check, and saving the to-be-received data packet to outside of the multiplexing FIFO when the to-be-received data packet is error-free.

The application discloses an NCCL migration method based on a resource pool, relates to the technical field of high-performance computing communication optimization, and comprises the following steps: obtaining thread identification records, synchronization timestamp markers and thread state information from the resource pool by scanning the multithread running environment of the NCCL communication program based on the resource pool at a source end; generating a thread state snapshot in combination with data packet transmission progress, constructing a data transmission state file containing transmission interruption recovery points and synchronization signal priorities, and determining an initialized synchronization marker data set; transmitting the thread state snapshot and a data check code value to a target end according to the initialized synchronization marker data set, decoding the synchronization marker by using an inheritance marker analysis rule, generating a control module state cache of the target end, and obtaining a preliminary synchronization marker inheritance result; and the NCCL migration method based on the resource pool significantly improves the migration efficiency, data link continuity and overall running stability of the NCCL communication program in a high-load scene.

One or more systems, devices, computer program products and / or computer-implemented methods of use provided herein relate to decoding quantum low-density parity check (qLDPC) codes. For example, a system can comprise a memory that can store computer executable components and a processor that can execute the computer executable components stored in the memory. The computer executable components can comprise an error correction component that corrects, via a decoder, qubit errors for qLDPC code, wherein correcting qubit errors for the qLDPC code via the decoder can comprise: obtaining a set of local defect networks in a syndrome by matching defects on symmetries of the qLDPC code, wherein the symmetries comprise a subset of checks of the qLDPC code such that each qubit error creates an even number of defects; and locally correcting one or more of the set of local defect networks.

This invention relates to the field of storage technology and discloses a method for storing verification data in a cache device. The method includes: receiving a write request for a target logical address; performing feature extraction operations on the target logical address to generate a rotation displacement factor; traversing multiple candidate data paths within the cache group and calculating the physical index value of the corresponding candidate verification path using its physical index value and the rotation displacement factor; detecting the occupancy status of the candidate data paths and their corresponding candidate verification path physical index values; determining the target data path and the target verification path based on the occupancy status; and writing the data and the generated checksum into the target data path and the target verification path, respectively. This invention establishes a strong mapping between the verification storage location and the logical address, forcibly triggering verification failure when the address addressing is incorrect, preventing silent errors, and improving the storage security of verification data in the cache device.

The application discloses a data error correction method of a cache medium and a solid state disk. The data error correction method comprises the following steps: in a first data operation state, performing a restart operation according to a check code of real-time use data in the cache medium after judging that a bit flip error occurs in the real-time use data, wherein the real-time use data comprises write data and an L2P mapping table; in a second data operation state, reading write data from a memory according to mapping table address data in mapping table management data in the cache medium, wherein the mapping table address data represents a storage position of the L2P mapping table, and performing error correction by flipping a plurality of bit positions of the mapping table address data one by one after judging that a bit flip error occurs in the mapping table address data according to a reading result. The data error correction method of the cache medium can detect different types of protected data in real time, discover running errors in time and correct the errors, prevent firmware from becoming a brick, respond to command requests of a host in time and protect data security.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The present application relates to a kind of starting verification method, device, electronic equipment, readable storage medium and vehicle, can be configured by one reference table for each operating partition in two operating partitions, when the software of current flash zone is written, the reference table corresponding to current flash zone is updated, when needing to carry out software starting verification, then from the corresponding reference table of current flash zone, the new check code is obtained, when new check code is successfully acquired, then the software program of the latest write in this partition is verified based on new check code.When new check code is not obtained from the reference table in current flash zone, the software program in the operating partition cannot be successfully started, then the latest check code in the reference table of current operating partition is verified, and the software program in current operating partition is started to run.Deter the situation that software verification fails and function cannot be used occurs.

This invention relates to the field of data security technology, and particularly to a communication data encryption method, apparatus, and electronic device based on the DES encryption algorithm. The method includes: constructing an environmental dynamic disturbance seed based on monitoring information, and dynamically adjusting the initial DES permutation table based on the environmental dynamic disturbance seed; determining the cyclic left shift bit for each iteration based on the instantaneous pressure in the pipeline and the node coordinates of the monitoring node, and generating a subkey for each iteration based on the cyclic left shift bit; acquiring the monitoring information of the previous transmission cycle to determine the S-box output rotation factor, and outputting the S-box output sequence; performing DES dynamic encryption based on the dynamic permutation table, the cyclic left shift bit, and the S-box output sequence to obtain encrypted ciphertext, generating a message checksum, and then concatenating the encrypted ciphertext and the message checksum into encrypted information before sending it to the scheduling center. This invention effectively improves the efficiency of data encryption within IoT nodes.

The application discloses a color-coated product anti-counterfeiting system and a double-layer encryption and decryption method thereof, and specifically comprises the following steps: in the encryption process, the first layer uses the SM4 national encryption algorithm to encrypt plaintext; the second layer derives a key based on the PBKDF2, and performs three rounds of confusion encryption on the first layer ciphertext, including character replacement and position replacement, to generate second layer ciphertext; finally, a check code is generated based on the derived key, and the last character of the second layer ciphertext is replaced to form the final ciphertext; in the decryption process, which is the reverse process of the encryption process, the same derived key is generated and the check code is verified, and the first layer ciphertext is obtained through reverse confusion processing, and then the plaintext is restored by using the SM4 decryption. The application constructs a double-layer encryption system of the national encryption algorithm and a self-defined confusion structure, meets the national encryption regulation requirements, greatly improves the randomness and anti-cracking ability of the anti-counterfeiting code through multiple rounds of confusion and integrity check, effectively prevents data forgery and tampering, and the ciphertext length is suitable for two-dimensional code coding.