Data error correction method for cache medium and solid state disk

Abstract

The application discloses a data error correction method of a cache medium and a solid state disk. The data error correction method comprises the following steps: in a first data operation state, performing a restart operation according to a check code of real-time use data in the cache medium after judging that a bit flip error occurs in the real-time use data, wherein the real-time use data comprises write data and an L2P mapping table; in a second data operation state, reading write data from a memory according to mapping table address data in mapping table management data in the cache medium, wherein the mapping table address data represents a storage position of the L2P mapping table, and performing error correction by flipping a plurality of bit positions of the mapping table address data one by one after judging that a bit flip error occurs in the mapping table address data according to a reading result. The data error correction method of the cache medium can detect different types of protected data in real time, discover running errors in time and correct the errors, prevent firmware from becoming a brick, respond to command requests of a host in time and protect data security.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a data error correction method for a cache medium and a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made with solid-state electronic storage chips, primarily composed of a controller, memory, and cache media. SSDs typically use flash memory (such as NAND flash memory) to store write data, while using static random access memory (SRAM) as the cache media to store large amounts of data necessary for program execution. If a single bit in the data stored in SRAM experiences a flip due to environmental factors such as electromagnetic radiation, voltage fluctuations, or cosmic rays, it can interfere with running programs, potentially bricking the firmware and, in more serious cases, affecting user data.

[0003] A single-bit flip occurs when the value of a single bit in data changes from "0" to "1" or vice versa. For example, if a string of data is "10110011", a single-bit flip would change it to "10100011", causing an error when reading or using the data. Electronic bit flips, on the other hand, can cause data anomalies. Even a single bit flip can lead to overall data inconsistency, affecting the correct execution of host read / write commands, causing hard drive data corruption, and resulting in unrecoverable user data. If the data is critical, such an error can lead to a major firmware disaster. Currently, methods exist that use external storage devices to store backup data for verification and error correction of data in SRAM. However, this increases hardware costs, is verbose, and has unsatisfactory results. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a data error correction method for a cache medium and a solid-state drive (SSD), which can monitor and correct data that has undergone single-bit flips during SSD operation without increasing hardware costs, thereby protecting the secure operation of firmware and the security of user data, and solving the problems of the prior art.

[0005] According to one aspect of the present invention, a data error correction method for a cache medium is provided, the cache medium being located in a solid-state drive (SSD), the SSD further comprising a memory, wherein the data error correction method for the cache medium comprises: in a first data operation state, determining whether a bit-flip error has occurred in the real-time usage data based on a checksum of the real-time usage data in the cache medium; performing a restart operation after detecting that a bit-flip error has occurred in the real-time usage data; in a second data operation state, obtaining corresponding mapping table address data from mapping table management data in the cache medium and performing write data reads on the memory to determine whether a bit-flip error has occurred in the mapping table address data; and correcting the error by flipping multiple bits of the mapping table address data bit by bit after detecting that a bit-flip error has occurred in the mapping table address data, wherein the real-time usage data includes write data and an L2P mapping table, and the mapping table management data includes multiple mapping table address data entries representing the storage location of the L2P mapping table.

[0006] Optionally, the first data operation state includes a standby state and a state that receives a non-read data operation command from the host; the second data operation state includes a state that receives a read / write data operation command from the host and a state in which the solid-state drive traverses and checks all mapping table management data when powered on, wherein the non-read data operation command includes data writing, data updating, data transfer, and data deletion.

[0007] Optionally, in the first data operation state, the step of determining whether a bit-flip error has occurred in the real-time used data based on the checksum of the real-time used data in the cache medium includes: in the first data operation state, calculating the real-time checksum of the real-time used data; reading the pre-stored checksum of the real-time used data that has been stored in the cache medium; comparing the real-time checksum with the pre-stored checksum; if the two are consistent, no bit-flip error has occurred; if the two are inconsistent, a bit-flip error has occurred.

[0008] Optionally, the verification code is the value of the least significant bit of the count value where each data point in the real-time data is XORed sequentially.

[0009] Optionally, the mapping table address data includes flag bits and data bits, the data bits include high-word data and low-byte data, and the flag bits represent the type of the mapping table address data; when the mapping table address data represents the storage location of the L2P mapping table in the memory, it is a first type of data, and when the mapping table address data represents the storage location of the L2P mapping table in the mapping table cache area in the cache medium, it is a second type of data.

[0010] Optionally, when the mapping table address data is of the first type, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: sequentially flipping all data bits in the mapping table address data to obtain a new address; searching for write data in the memory each time based on the L2P mapping table obtained from the new address; when the reserved information of the found write data is consistent with the reserved information in the mapping table address data, overwriting the erroneous data with the new address after error correction.

[0011] Optionally, when the mapping table address data is of the first type, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: sequentially flipping all data bits in the mapping table address data to obtain a new address; searching for write data in the memory each time based on the L2P mapping table obtained from the new address; when the reserved information of the found write data matches the reserved information in the mapping table address data, recording the timestamp corresponding to the data; updating the mapping table address data to the mapping table address data corresponding to the data with the longest timestamp; reading write data from the memory using the updated new address, to determine whether the correct write data has been read based on the reserved information, and overwriting the erroneous data with the corrected new address after a correct read.

[0012] Optionally, when the mapping table address data is second type data, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: first, flipping all bits of the low byte data bit by bit to obtain a new address; each time, searching for write data from the memory based on the L2P mapping table obtained from the new address; determining whether the reserved information of the found write data is consistent with the reserved information in the mapping table address data, and if they are consistent, using the corrected new address to overwrite the erroneous data.

[0013] Optionally, when the mapping table address data is of the second type, the high word data of the mapping table address data is the ID of the mapping table cache.

[0014] Optionally, when it is determined that the reserved information of the found write data is inconsistent with the reserved information in the mapping table address data, the data error correction method of the cache medium further includes: if the error correction is still unsuccessful after all the low-byte data has been flipped, then the high-word data is flipped bit by bit to obtain a new address; the length of the table entry information in the mapping table cache area indicated by the ID contained in the new address is obtained; the ID of the mapping table cache area with the longest table entry information is updated to the high-word data; the write data is read from the memory using the updated new address to determine whether the correct write data has been read, and the erroneous data is overwritten using the error-corrected new address after the correct reading.

[0015] Optionally, if the error correction still fails after all data bits of the mapping table address data have been flipped, the data error correction method of the cache medium further includes: using the new address obtained after flipping the flag bits to search for write data in the memory; determining whether the reserved information of the found write data is consistent with the reserved information in the mapping table address data, and if they are consistent, using the new address after error correction to overwrite the erroneous data.

[0016] Optionally, after detecting a bit flip error in the mapping table address data and correcting the error by flipping multiple bits of the mapping table address data bit by bit, the method further includes: performing a restart operation if the error correction of the mapping table address data fails.

[0017] Optionally, in the second data operation state, the step of obtaining the corresponding mapping table address data from the mapping table management data in the cache medium to write data to the memory and determine whether the mapping table address data has a bit flip error includes: writing data to the memory according to the L2P mapping table obtained from the mapping table address data; if no valid write data is read, or if the reserved information of the write data is inconsistent with the reserved information in the mapping table address data, it is determined that the mapping table address data has a bit flip error.

[0018] According to another aspect of the present invention, a solid-state drive is provided, comprising: a cache medium for storing real-time usage data and mapping table management data; a processor for receiving data, commands, and requests from a host, and for executing the data error correction method of the cache medium; and a memory connected to the processor for storing write data and an L2P mapping table according to the control of the processor.

[0019] The data error correction method for cache media provided in this application applies different verification and error correction methods to different types of data in the cache media. For real-time data that can be accessed in real time, such as write data and L2P mapping tables stored in the cache media, in the first data operation state, the data checksum is used to verify whether a bit flip has occurred. If a single bit flip error occurs, a power-on restart is initiated. This prevents the writing and updating of erroneous data and allows for timely correction of the erroneous data, quickly completing the power-on restart table creation and recovery process, rapidly responding to host requests, and ensuring correct data operation. For mapping table management data, which manages the L2P mapping table, in the second data operation state, the write data is read from memory based on the mapping table address data to verify whether a single bit flip has occurred. When a single bit flip occurs in the mapping table address data, multiple bits are flipped sequentially to correct the error, avoiding frequent restarts that could affect mapping table access and data reading. This allows for rapid error correction, rapid response to host read operation requests, seamless error correction, and timely protection of data in memory. The data error correction method for solid-state drives and cache media in this invention can achieve real-time detection and error correction with relatively low hardware costs, respond promptly to host commands, and achieve good error correction results.

[0020] Furthermore, the mapping table address data in the mapping table management data can be divided into two data types. The L2P mapping table it represents is stored as type 1 data in memory and as type 2 data in the cache medium. For type 1 data, all data bits need to be flipped bit by bit before reading and writing data to determine whether error correction was successful. For type 2 data, the least significant byte data needs to be flipped bit by bit before reading and writing data to determine whether error correction was successful. This simplifies the error correction process and ensures response speed while guaranteeing correct data operation. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram illustrating the data distribution in SRAM and NAND memory in a solid-state drive according to an embodiment of the present invention is shown;

[0023] Figure 2 A flowchart of a data error correction method for a cache medium according to an embodiment of the present invention is shown;

[0024] Figure 3 A schematic diagram illustrating the real-time usage data verification code generation process according to an embodiment of the present invention is shown.

[0025] Figure 4A schematic diagram illustrating the components of the data bits of the mapping table address data according to an embodiment of the present invention is shown;

[0026] Figure 5 A schematic flowchart illustrating the process of correcting a second type of data in a data error correction method for a cache medium according to an embodiment of the present invention is shown.

[0027] Figure 6 This diagram illustrates a data change process in a data error correction method for a cache medium according to an embodiment of the present invention, where bits are flipped bit by bit.

[0028] Figure 7 A schematic flowchart illustrating error correction of a first type of data in a data error correction method for a cache medium according to an embodiment of the present invention is shown.

[0029] Figure 8 Another schematic flowchart of the data error correction method for a cache medium according to an embodiment of the present invention is shown;

[0030] Figure 9 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown. Detailed Implementation

[0031] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0032] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0033] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0034] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0035] Figure 1A schematic diagram of the data distribution in SRAM and NAND memory in a solid-state drive according to an embodiment of the present invention is shown.

[0036] Solid-state drives (SSDs) typically consist of a controller, a cache medium, and memory. The memory is usually flash memory, such as NAND flash memory, while the cache medium is, for example, SRAM. SSDs communicate with the host, receiving data and commands. For instance, when receiving a write command from the host, the SSD stores the write data in the NAND flash. This process generates a mapping between the logical and physical addresses of the write data in memory. These mappings are stored in the SRAM, forming an L2P (logic-to-physical) mapping table. When the number of L2P mapping tables stored in the SRAM becomes large, these tables are written in batches to the NAND flash to free up storage space in the SRAM.

[0037] like Figure 1 As shown, the L2P mapping table is stored in SRAM as multiple CMTs (cache manage tables). When one or more CMT areas are full, the corresponding L2P mapping table is written to NAND flash memory as a DBMT (Data Block Manage Table), which serves as the first-level mapping table. Each DBMT stores a set number of L2P mapping tables for different CMT areas. During this process, mapping table management data is also generated, forming a TBMT (Table Block Manage Table) in SRAM, which serves as the second-level mapping table. The correspondence between CMTs, DBMTs, and TBMTs is as follows: Figure 1 Since it is already maturely used in solid-state drives (SSDs), it will only be briefly introduced here. Of course, SRAM can also store multiple write data entries. Therefore, SRAM can contain at least two parts of protection data: one part is real-time usage data, which includes write data and L2P mapping tables, for example, stored in the CMT area; the other part is mapping table management data, for example, stored in the TBMT area, which can exist in the form of mapping table address data. The mapping table address data represents the storage location of the L2P mapping table, which will be discussed below. Figures 2-7 This paper introduces different detection and error correction methods for the two types of data.

[0038] Figure 2 A flowchart of a data error correction method for a cache medium according to an embodiment of the present invention is shown.

[0039] like Figure 2 As shown, the data error correction method for the cache medium in this embodiment specifically includes the following steps:

[0040] In step S101, under the first data operation state, it is determined whether a bit flip error has occurred in the real-time used data based on the checksum of the real-time used data in the cache medium. In this step, a checksum is used to determine whether a single bit flip has occurred in the real-time used data in the cache medium. The real-time used data includes, for example, the write data and L2P mapping table stored in the CMT area mentioned above. The first data operation state includes standby state and the state of receiving a non-read data operation command from the host. Non-read data operation commands include data write, data update, data transfer, and data deletion commands. That is, when the solid-state drive is in standby state for a long time, or when it receives a command from the host to perform update operations on the real-time used data stored in SRAM during normal operation, a check for single bit flips will be performed on this real-time used data. This is mainly done by comparing checksums. The checksum is, for example, the lowest bit value of the count of bits that are 1 after XORing each piece of data in the real-time used data.

[0041] Figure 3 A schematic diagram illustrating the real-time data verification code generation process according to an embodiment of the present invention is shown. Figure 3 As shown, for example, with 7 data points, first, perform an XOR operation on each of the 7 data points (Entry1-Entry7) to obtain a result value Entry8. Then, count the number of 1s in the binary digits of Entry8, which is counted as Entry9. The least significant bit of this count is then used as the checksum. For example, if Entry8 is "10101011", then Entry9 is "00000101", and the checksum is 1. This ensures that the checksum is as simple as possible, reduces the probability of bit flips in the checksum, and prevents the checksum itself from being abnormal.

[0042] Further, step S101 specifically includes: in the first data operation state, calculating the real-time checksum of the real-time used data; reading the pre-stored checksum of the real-time used data already stored in the cache medium; comparing the real-time checksum with the pre-stored checksum; if they match, no bit-flip error has occurred; if they do not match, a bit-flip error has occurred. That is, when storing data in SRAM, the checksum is also stored simultaneously. When an error is detected based on the checksum, it prevents further data writing or updating.

[0043] See also Figure 2In step S102, a restart operation is performed after a bit-flip error is detected in the real-time data. In this step, upon detecting a bit-flip error in the real-time data, the host's operation commands are not executed; a power-on restart is performed first. During the power-on restart, the table is rebuilt and the data is restored to its correct state. Then, the commands issued by the host are executed. Therefore, before each data change, a checksum is used for verification; if an error is detected, a power-on restart is performed to ensure data security. When the data is verified as correct using the checksum, the host's operation commands are executed to update the data, and then the checksum is updated. Before writing data to the NAND flash memory or when the firmware backend task is in sleep mode, a checksum is also used for verification; if an error is detected, a power-on restart is performed to correct the error. This ensures data correctness. In some embodiments, if a single bit-flip error still exists after a power-on restart, the erroneous data can be corrected by flipping the bits one by one.

[0044] In step S103, under the second data operation state, the corresponding mapping table address data is obtained from the mapping table management data in the cache medium to write data to the memory, in order to determine whether a bit flip error has occurred in the mapping table address data. The second data operation state includes the state of receiving an operation command from the host to read and write data from the NAND flash memory, and the state of the solid-state drive traversing and checking all mapping table management data after power-on. In this step, when receiving the operation command to read and write data from the host, the L2P mapping table needs to be obtained before data can be read and written from the NAND flash memory. This requires first obtaining the corresponding mapping table address data from the mapping table management data, obtaining the storage location of the L2P mapping table based on the mapping table address data, and then reading the L2P mapping table. When traversing and checking all mapping table management data after power-on, it is also necessary to read and write data from the memory based on the obtained L2P mapping table for verification. Therefore, it is necessary to first verify whether a single bit flip has occurred in the mapping table address data to determine whether the correct L2P mapping table can be obtained.

[0045] This step specifically includes: reading and writing data to the memory based on the L2P mapping table obtained from the mapping table address data; if valid write data cannot be read, or if the reserved information of the write data is inconsistent with the reserved information in the mapping table address data, it is determined that a bit flip error has occurred in the mapping table address data. In a more detailed embodiment, when the solid-state drive traverses and checks all mapping table management data after power-on, if an error in an abnormal bit is found after the table is built, the bit is directly corrected according to the functional logic. Data that cannot be corrected is considered erroneous data belonging to the valid mapping table address data; therefore, the memory is read and written to determine whether a single bit flip error has occurred in the mapping table address.

[0046] In step S104, after detecting a bit-flipping error in the mapping table address data, error correction is performed by flipping multiple bits of the mapping table address data bit by bit. In this step, multiple bits of the mapping table address data are flipped bit by bit, and then the data is read and written, and compared with the reserved information to ensure that the data is restored correctly.

[0047] Furthermore, in this embodiment, before step S201, the method may further include: obtaining the current data operation state of the cache medium to determine whether the solid-state drive is currently in a first data operation state or a second data operation state, thereby performing different actions. Steps S101-S102 are executed in the first data operation state, while steps S103-S104 are executed in the second data operation state.

[0048] Figure 4 A schematic diagram illustrating the components of the data bits of the mapping table address data according to an embodiment of the present invention is shown.

[0049] like Figure 4 As shown, the L2P mapping table address data (Table faa) consists of flag bits and data bits. The flag bit (type) is typically 1 bit, while the data bits usually include multiple bits, such as 24 bits, where the first 8 bits are the low byte data and the last 16 bits are the high word data. The mapping table address data indicates the location where the L2P mapping table is stored. The low byte data is generally related to the TBMT and is relatively fixed, while the high word data is related to the data type. The flag bits are used to indicate the data type, indicating the storage location of the L2P mapping table, i.e., whether it is stored in the DBMT or the CMT. When the mapping table address data indicates that the L2P mapping table is stored in memory (the DBMT of NAND), it is type 1 data; when the mapping table address data indicates that the L2P mapping table is stored in the mapping table cache area (CMT) in the cache medium, it is type 2 data. Therefore, the flag bits can be used to determine which type of mapping table address data it is, whether it is type 1 or type 2 data. Furthermore, when the mapping table address data is of type two, the high-order word of the mapping table address data is the ID of the mapping table cache, that is, the ID of the CMT is used as the high-order word. When a bit-flipping error is detected in the mapping table address data, error correction is performed by sequentially flipping multiple bits of the data portion of the mapping table address data. Different error correction methods correspond to type one and type two data, which will be discussed below. Figures 5-7 Detailed introduction.

[0050] When the mapping table address data is determined to be type 2 data based on the flag bit, step S104 specifically includes: first, sequentially flipping all bits of the low byte data of the mapping table address data to obtain a new address; each time, searching for write data in the memory based on the L2P mapping table obtained from the new address; when the reserved information of the found write data matches the reserved information in the mapping table address data, it indicates that the new address is a correct address, and it is used to overwrite the erroneous data. See details below. Figure 5 .

[0051] Figure 5 A schematic diagram of the process for correcting a second type of data in a data error correction method for a cache medium according to an embodiment of the present invention is shown.

[0052] Since the data in the CMT (including the CMT ID) has been protected by a checksum, its integrity is very high. Therefore, for the single-bit flip error in the table faa of the second type of data, we first need to flip its low byte bit by bit to match the correct mapping address. For example... Figure 5 The steps S201-S204 are shown.

[0053] In step S201, the low-byte data is flipped one bit at a time to obtain a new address. In step S202, the write data is retrieved from the memory based on the new address. In step S203, it is determined whether the data match is correct. If yes, step S212 is executed, and the erroneous data is overwritten with the corrected new address; otherwise, step S204 is executed. In step S204, it is determined whether the low-byte data flipping is complete. If yes, step S205 is executed, and the high-byte data is flipped; otherwise, step S201 is returned. That is, steps S201-S204 are continuously executed in a loop until the correct write data is found or all low-byte data flipping is completed. After each bit flip to obtain a new address, write data is read from the NAND flash memory based on the new address to check if the DBMT information in the reserved information is consistent. If the DBMT information is consistent, it is considered that the correct data has been read. That is, it determines whether the reserved information of the found write data is consistent with the reserved information in the address data of the mapping table. If they are consistent, it is considered that the correct write data has been read from the memory, that is, the data is correctly matched and the error correction is successful; otherwise, the error correction operation continues.

[0054] Figure 6 This diagram illustrates a data change process in a data error correction method for a cache medium according to an embodiment of the present invention, where bits are flipped bit by bit.

[0055] like Figure 6As shown, the target data (e.g., 01010101) is erroneous data that has undergone a single-bit flip, requiring bit-by-bit flipping correction. First, the first bit is flipped, resulting in 01010100. This data is then read from the NAND flash memory and compared for verification. If the correction fails, the second bit is flipped, for example, to 01010111, and the NAND flash memory is read and compared again. This process continues until the last bit is flipped, resulting in the data 11010101. By flipping each bit of the erroneous data and attempting to compare it with existing data in the NAND flash memory to recover the correct data, data error correction and recovery can be performed in real-time when the firmware detects data anomalies, preventing abnormal data reads by the user.

[0056] If error correction is still unsuccessful after all the low-byte data has been flipped, it indicates that the high-byte data may have undergone bit flipping. In this case, it is necessary to flip the high-byte data of the mapping table address data bit by bit to obtain a new address; obtain the length of the table entry information in the mapping table cache area indicated by the ID contained in the new address; update the ID of the mapping table cache area with the longest table entry information to the high-byte data to complete the error correction operation. See details. Figure 5 Steps S205-S212.

[0057] In step S204, if it is determined that the low-byte data flipping is complete and error correction is unsuccessful, step S205 is executed. In step S205, the high-word data is flipped one bit sequentially to obtain a new address. In step S206, the length of the table entry information in the mapping table cache area indicated by the ID contained in the new address is obtained. In step S207, it is determined whether the table entry information is the longest; if so, step S208 is executed; otherwise, step S209 is executed. In step S208, the ID of the mapping table cache area with the longest table entry information is updated to the high-word data, and then step S209 is executed. In step S209, it is determined whether the high-word data flipping is complete; if so, step S210 is executed, and the obtained new address is used to read and write data; otherwise, step S205 is returned. In step S210, the updated new address is used to read and write data from the memory. In step S211, it is determined whether the correct write data has been read. If so, step S212 is executed, that is, the erroneous data is overwritten with the new address after error correction; otherwise, step S213 is executed. In step S212, the mapping table address data after error correction is obtained. In step S211, it is still possible to determine whether the correct write data has been read by checking whether the reserved information of the found write data is consistent with the reserved information in the mapping table address data.

[0058] In this embodiment, since the high-word data of the second type of data is the CMT ID, the corresponding CMT can first be found based on the ID. When the ID undergoes a bit flip, the stored table entry information (CMT list) may be lost. Therefore, it is necessary to find the longest table entry information to ensure the correctness and integrity of the data. Thus, it is necessary to continuously verify the table entry length, find the longest corresponding CMT ID to update the high-word data, and form a new mapping table address data. Then, data is read from the NAND flash memory based on the new address for verification and comparison. Successful verification indicates successful data error correction.

[0059] If error correction fails even after sequentially flipping the high-order data bit by bit, it indicates a possible bit flip in the flag bit. When a flag bit flip error occurs, even if the data bits in the mapping table address are correct, it will lead to incorrect type determination of the first and second types of data. That is, treating DBMT type data as CMT type data to retrieve the mapping table will cause the search to instead use the high-order data (obtained as an ID) and its corresponding CMT high-order data, along with its own low-order data, instead of directly searching the mapping table using the high-order data. This will also result in the inability to find the correct write data. Therefore, if error correction still fails after the above steps, the flag bit needs to be flipped. That is, after data matching fails in step S211, steps S213-S215 are executed.

[0060] Specifically, in step S213, the new address obtained after flipping the flag bit is used to search for write data. In this step, the flag bit is first flipped to obtain a new address, and then the new mapping table address data is used to read the write data from the memory. In step S214, it is determined whether the data match is correct. If it is, step S212 is executed, and the erroneous data is overwritten with the new address after error correction; otherwise, step S215 is executed, in which a power-on restart is performed. That is, if the above mapping table address data error correction process still fails after all the above processes have been completed, a restart operation is performed to restore the data by restarting the table creation process.

[0061] Further, see also Figure 2 When the mapping table address data is of the first type, step S104 specifically includes: sequentially flipping all bits of the mapping table address data to obtain a new address; searching for write data in memory each time based on the L2P mapping table obtained from the new address; when the reserved information of the found write data matches the reserved information in the mapping table address data, the erroneous data is overwritten with the new address after error correction, and the error correction operation is completed. See [link to details] for further steps. Figure 7 .

[0062] Figure 7A schematic flowchart illustrating the correction of a first type of data in a data correction method for a cache medium according to an embodiment of the present invention is shown.

[0063] Figure 7 and Figure 5 The flipping process is similar, except... Figure 7 This requires bit-by-bit error correction of all data bits in the mapping table address data. Specifically, Figure 7 The process includes the following steps: In step S301, the mapping table address data is sequentially flipped one bit to obtain a new address. In step S302, the write data is searched for in memory based on the new address. In step S303, it is determined whether the data match is correct. If yes, step S307 is executed, and the erroneous data is overwritten with the new address after error correction, completing the error correction; otherwise, step S304 is executed. In step S304, it is determined whether all data bits have been flipped. If yes, it indicates that there may be a bit flipping error in the flag bit, and step S305 is executed; otherwise, step S301 is returned. By cyclically executing steps S301-S304, the data bits are flipped bit by bit for error correction, and it is determined whether the correct write data can be read. If all data bits have been flipped but error correction is still unsuccessful, the flag bit needs to be flipped. Then, in step S305, the write data is searched for using the new address obtained after flipping the flag bit. In step S306, it is determined whether the data match is correct. If yes, step S307 is executed; otherwise, step S308 is executed. In step S307, the erroneous data is overwritten with the corrected new address. In step S308, a power-on restart is performed. That is, if the mapping table address data still fails to correct errors after executing the above steps S301-S306, a restart operation is performed.

[0064] When using DBMT type mapping table address data to read reserved information for write data, there may be multiple different mapping table addresses corresponding to the same reserved information, for example, data with a new / old relationship. Therefore, during the error correction process, there may be multiple matching data sets with potentially identical reserved information corresponding to different mapping table addresses. Thus, it's necessary to record the timestamps of these matching data sets, and the mapping table address data corresponding to the data with the largest timestamp is the data we need to recover. The following combines... Figure 8 Another embodiment of a method for error correction of the first type of data is introduced.

[0065] Figure 8 Another schematic flowchart illustrating the correction of a first type of data in a data correction method for a cache medium according to an embodiment of the present invention is shown.

[0066] Figure 8 and Figure 7 The process is roughly the same, in Figure 7The main additions are steps S404-S406. See details below. Figure 8 In step S401, the mapping table address data is sequentially flipped by one bit to obtain a new address. In step S402, the write data is retrieved from memory based on the new address. In step S403, it is determined whether the data match is correct; if yes, proceed to step S404; otherwise, proceed to step S407. In step S404, the timestamp corresponding to the data is recorded; here, the timestamp corresponding to the data with a correct match is recorded. In step S405, it is determined whether the timestamp is the longest or the largest; if yes, proceed to step S406; otherwise, proceed to step S407. In step S406, the mapping table address data is updated to the mapping table address data corresponding to the data with the longest timestamp; that is, only the mapping table address data corresponding to the most recently stored data is retained, or in other words, only the table faa of the data with the largest timestamp is retained. Then, in step S407, it is determined whether all data bits have been flipped; if yes, proceed to step S408; otherwise, return to step S401. In step S408, it is determined whether the correct write data has been read from the memory. If so, step S411 is executed, indicating successful error correction; otherwise, step S409 is executed, meaning that if error correction still fails after all data bits have been flipped, the flag bit needs to be flipped. In step S409, the new address obtained after flipping the flag bit is used to search for the write data. In step S410, it is determined whether the data match is correct. If so, step S411 is executed; otherwise, step S412 is executed. In step S411, the erroneous data is overwritten using the new address after error correction. In step S412, power is turned on and the system restarts. That is, if error correction still fails after executing steps S401-S411, a restart operation is performed.

[0067] Figure 9 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown.

[0068] like Figure 9 As shown, the computer system 100 includes a host 110 and a solid-state drive (SSD). The SSD is a memory hard drive made of solid-state electronic storage chips. The SSD includes a controller 120 and a memory 130. The memory 130 is, for example, a flash memory. The controller 120 is connected to the host 110 and is used to exchange write data with the host 110, receive data, commands, and requests issued by the host, and perform the aforementioned operations. Figures 2-8 The described method for correcting data errors in the cache medium. The controller 120 is also used to control the operation of the memory 130.

[0069] The controller 120 includes, for example, a host interface 121, a processor 123, a cache medium 124, and a memory controller 128. The host interface 121 of the control system 120 is connected to the host 110 to transmit write data and commands. The processor 123 is connected to the host interface 121, the cache medium 124, and the memory controller 128. The processor 123 is used, for example, to execute the data error correction method of the cache medium. The cache medium 124 is, for example, SRAM, which stores a mapping table or index table corresponding to the write data. The memory controller 128 controls the transmission and storage of write data. The processor 123 is also used to implement the core software layer for memory control, namely the FTL (flash translation layer), enabling the operating system and file system to access the memory like a hard drive. This FTL also has features such as supporting bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0070] The memory 130 includes a flash memory chip array comprising multiple physical blocks for storing write data, mapping tables, or index tables. The physical block storing write data is called user physical block 132, while the physical block storing the mapping table is called mapping physical block 131, which includes a DBMT. To improve data read / write performance, the memory controller 128 of the controller 120 can read and write to the flash memory chips of the memory 130 via multiple channels (e.g., CH0 and CH2). Each channel connects to a group of flash memory chips, storing the write data in user physical block 132.

[0071] It should be understood that the above method can be applied not only to solid-state drives (SSDs), but also to other storage hard drives or storage devices that have controllers, cache media, and memory, and the data error correction method of the cache media can be implemented by the controller.

[0072] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A data error correction method for a cache medium, wherein the cache medium is located in a solid-state drive (SSD), and the SSD further includes a memory, wherein... The data error correction method for the cache medium includes: In the first data operation state, it is determined whether a bit flip error has occurred in the real-time used data based on the checksum of the real-time used data in the cache medium; A restart operation is performed after a bit flip error is detected in the real-time data being used. In the second data operation state, the corresponding mapping table address data is obtained from the mapping table management data in the cache medium to write data to the memory, so as to determine whether the mapping table address data has a bit flip error; After detecting a bit-flipping error in the mapping table address data, error correction is performed by flipping multiple bits of the mapping table address data bit by bit. The real-time usage data includes write data and L2P mapping tables, and the mapping table management data includes multiple mapping table address data that characterize the storage location of the L2P mapping table.

2. The data error correction method for the cache medium according to claim 1, wherein, The first data operation state includes standby state and state of receiving non-read data operation commands issued by the host; the second data operation state includes state of receiving read / write data operation commands issued by the host and state of the solid-state drive traversing and checking all mapping table management data after power-on, wherein the non-read data operation commands include data writing, data updating, data transfer, and data deletion.

3. The data error correction method for the cache medium according to claim 1, wherein, In the first data operation state, the step of determining whether a bit-flip error has occurred in the real-time used data based on the checksum of the real-time used data in the cache medium includes: In the first data operation state, calculate the real-time checksum of the real-time used data; Read the pre-stored verification code of the real-time usage data that has been stored in the cache medium; The real-time check code is compared with the pre-stored check code. If they match, no bit-flip error has occurred; otherwise, a bit-flip error has occurred.

4. The data error correction method for the cache medium according to claim 1, wherein, The checksum is the value of the least significant bit of the count value that is 1 among the XOR operations performed sequentially on each data in the real-time usage data.

5. The data error correction method for the cache medium according to claim 1, wherein, The mapping table address data includes flag bits and data bits, the data bits include high-word data and low-byte data, and the flag bits represent the type of the mapping table address data; When the mapping table address data indicates that the L2P mapping table is stored in the memory, it is of the first type of data; when the mapping table address data indicates that the L2P mapping table is stored in the mapping table cache area in the cache medium, it is of the second type of data.

6. The data error correction method for the cache medium according to claim 5, wherein, When the mapping table address data is of the first type, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: The new address is obtained by sequentially flipping all the data bits in the address data of the mapping table; Each time, data is searched for in the memory based on the L2P mapping table obtained from the new address; When the reserved information for the found write data matches the reserved information in the address data of the mapping table, the erroneous data is overwritten using the new address after error correction.

7. The data error correction method for the cache medium according to claim 5, wherein, When the mapping table address data is of the first type, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: The new address is obtained by sequentially flipping all the data bits in the address data of the mapping table; Each time, data is searched for in the memory based on the L2P mapping table obtained from the new address; When the reserved information for the found write data matches the reserved information in the mapping table address data, record the timestamp corresponding to the data; Update the mapping table address data to the mapping table address data corresponding to the data with the longest timestamp; The updated address is used to read write data from memory. The system determines whether the correct write data has been read based on the reserved information. If the data is read correctly, the erroneous data is overwritten using the corrected address.

8. The data error correction method for the cache medium according to claim 5, wherein, When the mapping table address data is of the second type, after detecting a bit flip error in the mapping table address data, the step of correcting the error by flipping multiple bits of the mapping table address data bit by bit includes: First, flip all the bits of the low byte data bit by bit to obtain the new address; Each time, data is searched for in the memory based on the L2P mapping table obtained from the new address; Determine whether the reserved information of the found write data is consistent with the reserved information in the address data of the mapping table. If they are consistent, use the new address after error correction to overwrite the erroneous data.

9. The data error correction method for the cache medium according to claim 8, wherein, When the mapping table address data is of the second type, the high word data of the mapping table address data is the ID of the mapping table cache area.

10. The data error correction method for the cache medium according to claim 9, wherein, When it is determined that the reserved information of the found write data is inconsistent with the reserved information in the mapping table address data, the data error correction method of the cache medium further includes: If the error correction is still unsuccessful after all the low-byte data has been flipped, then the high-byte data is flipped bit by bit in sequence to obtain a new address; Obtain the length of the table entry information in the mapping table cache area indicated by the ID contained in the new address; Update the ID of the mapping table cache area with the longest entry information to the high-word data; The updated address is used to read the write data from the memory to determine whether the correct write data has been read. If the data is read correctly, the erroneous data is overwritten using the corrected address.

11. The data error correction method for the cache medium according to any one of claims 6-10, wherein, If error correction fails even after all data bits of the mapping table address data have been flipped, the data error correction method of the cache medium further includes: The new address obtained by flipping the flag bit is used to search for and write data in memory. Determine whether the reserved information of the found write data is consistent with the reserved information in the address data of the mapping table. If they are consistent, use the new address after error correction to overwrite the erroneous data.

12. The data error correction method for the cache medium according to claim 1, wherein, After detecting a bit-flipping error in the mapping table address data, and correcting the error by flipping multiple bits of the mapping table address data bit by bit, the method further includes: A restart operation is performed if the address data correction of the mapping table fails.

13. The data error correction method for the cache medium according to claim 1, wherein, In the second data operation state, the steps of retrieving the corresponding mapping table address data from the mapping table management data in the cache medium to write data to the memory and read data to determine whether a bit flip error has occurred in the mapping table address data include: The memory is written and read based on the L2P mapping table obtained from the mapping table address data; If no valid write data is read, or if the reserved information of the write data is inconsistent with the reserved information in the mapping table address data, it is determined that a bit flip error has occurred in the mapping table address data.

14. A solid-state drive, comprising: Cache media stores real-time usage data and mapping table management data; A processor that receives data, commands, and requests from a host, and performs a data error correction method for a cache medium as described in any one of claims 1-13; The memory, connected to the processor, stores write data and L2P mapping tables under the control of the processor.

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