30 results about "Rotation factor" patented technology

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The application relates to the technical field of signal processing, and discloses a code Doppler effect elimination method in a signal combination process. Before signal combination, a time domain cyclic shift is performed on the autocorrelation function before combination, or a frequency domain rotation factor compensation is performed on the FFT transformation of the autocorrelation function, and then IFFT transformation is performed to the time domain. The application solves the problem that the prior art lacks a technical scheme capable of efficiently and accurately eliminating the code Doppler effect.

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

The embodiment of the present specification provides an NTT acceleration chip. The chip comprises: a rotation factor calculation module comprising a plurality of pre-calculation units and a plurality of real-time calculation units, the plurality of pre-calculation units are used for performing, in parallel, calculation of initial rows of rotation factors and inter-row stepping factors by using primitive roots; the plurality of real-time calculation units are used for performing, in parallel, repeated iteration calculation of rotation factors of other rows according to the inter-row stepping factors based on the initial rows of rotation factors obtained by the plurality of pre-calculation units; a transposition module comprising a plurality of transposition units, which are used for performing, in parallel, transposition processing on an input sequence to obtain a transposed sequence; and an NTT calculation module comprising a plurality of butterfly calculation units, which are used for performing, in parallel, butterfly operation of each order and point number based on the rotation factors obtained by the rotation factor calculation module and the transposed sequence obtained by the transposition module to obtain an output sequence. The efficiency of NTT calculation can be improved.

The application provides an ML-DSA-oriented low-resource number theory transformation acceleration system and method. The system comprises a control addressing module, a first storage module, a second storage module and an operation module. The first storage unit and the second storage unit in the storage module are used for storing the coefficients of a polynomial, and the third storage unit and the fourth storage unit are used for storing rotation factors and inverse rotation factors. The control addressing module determines a plurality of target coefficient addresses and a plurality of target rotation factor addresses based on the current operation mode, the current operation round and the current operation count. The first operation unit and the second operation unit in the operation module read the coefficients and the rotation factors respectively, operate the read coefficients, and store the operation results to the target coefficient addresses. The addressing method is simple, the operation unit accesses multiple coefficients at a time, and the reading and writing efficiency is high.

The present application provides an NTT circuit, an NTT method, and an electronic device. The NTT circuit comprises a first storage module, a first operation module, a first rotation module, and a second storage module. The first storage module is configured to store J4 pieces of first data. The J4 pieces of first data is divided into J2 first data arrays. Each first data array comprises J×J pieces of first data. J is a positive integer. The first operation module is configured to execute an NTT operation on the basis of each first data array to obtain a first operation result. The first rotation module is configured to transform the first operation result on the basis of a first rotation factor to obtain a first transformation result. The first transformation result comprises J×J pieces of second data. The second storage module is configured to store J4 pieces of second data corresponding to the J2 first data arrays. By means of the present application, the computing resources required by an NTT operation are reduced, and power consumption is reduced.

The embodiment disclosed by the application belongs to the technical field of computing, and particularly relates to a method for performing FFT, a processor and a computing device. The method comprises the following steps: in response to an execution request of a fast Fourier transform (FFT) calculation of an application program, a processor decomposes the FFT calculation into multiple calculations; the processor sequentially executes multiple calculation stages, wherein, when a target calculation stage is executed, a rotation factor calculation is executed based on a vector operation unit, and a DFT calculation is executed based on a matrix operation unit; after the execution of the multiple calculation stages is completed, an execution result of the FFT calculation is determined based on an execution result of the last calculation stage, and the execution result is returned to the application program. According to the application, the processor can jointly implement the FFT calculation based on the vector operation unit and the matrix operation unit, and the efficiency of the processor in executing the FFT calculation can be improved.

The invention discloses an information transmission method and device, relates to the technical field of communication, and is used for reducing the PAPR of a PPDU transmitted under a 320MHz bandwidth. The information transmission method comprises: a transmitting end device generates a PPDU with a 320MHz bandwidth, a part of fields or all fields of the PPDU being rotated on the 320MHz bandwidth through a twiddle factor sequence, the 320MHz bandwidth comprising 16 20MHz, the twiddle factor sequence comprising 16 twiddle factors, each 20MHz corresponding to a twiddle factor; and the sending end equipment sends the PPDU. Exemplary twiddle factor sequences may be [1, 1, 1, 1, 1,-1, 1, 1,-1,-1, 1, 1,-1, 1,-1, 1,-1].

The embodiment of the application discloses a data transformation method and device and a storage medium, and belongs to the field of data processing. In the embodiment of the application, the first transformation matrix is obtained by transforming an original transformation matrix according to the symmetry of a rotation factor in NTT. Thus, part of the matrix elements in the first transformation matrix has symmetry, so that the data processing results corresponding to the part of the matrix elements in the first transformation matrix are obtained, the data processing results corresponding to other matrix elements are restored, and then each output data is obtained. That is, in the embodiment of the application, the data processing results corresponding to part of the matrix elements are obtained, and all transformation information can be represented, the complexity of data transformation is reduced, and the transformation speed is accelerated.

The application provides a Hawk algorithm acceleration method based on GPU multi-thread parallelism. The Hawk algorithm acceleration method based on GPU multi-thread parallelism comprises the following steps: (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallelization reconstruction and memory access optimization; (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion. The application realizes a coarse-grained parallel butterfly operator execution mode without complex address calculation, without shared memory synchronization, and without competition between threads, greatly improving the throughput efficiency on the GPU; meanwhile, the application unifies the parallel execution framework in the forward and inverse transformations of FFT / NTT, wherein the inverse transformation only needs to use the corresponding inverse rotation factor and perform simple normalization processing at the end to complete the overall recovery.

Method for encoding source data, method for decoding code words, corresponding devices and computer program. The invention relates to a method for encoding at least one block of source data, delivering at least one code word of size , said method implementing a step of encoding said source data using a parity matrix . According to the invention, said parity matrix is ​​obtained from a basic matrix expressed in the form: The extension matrix comprises at least two blocks of rows and at least one block of columns, with an integer between 1 and , each block of rows comprising at least one matrix obtained by applying a circular rotation coefficient to a diagonal matrix of size , with an integer between 0 and , said at least one block of columns comprising at least two matrices obtained by applying a distinct circular rotation coefficient to said diagonal matrix of size .Figure for abstract: Figure 5A.

The application provides a Falcon signature FFT acceleration method for a RISC-V architecture. The method comprises the following steps: S1, adopting a Union data processing mechanism to complete data type conversion, directly calling RISC-V native double-precision hardware floating point instructions for FFT complex number operation, and accurately controlling register allocation; S2, introducing a cache prefetch mechanism, storing batch of discrete distributed complex rotation factors in a continuous intermediate cache array in advance before executing the FFT core calculation loop, changing the discrete real-time data fetching mode, and sequentially addressing to complete rotation factor reading; S3, adopting multi-loop loop unrolling transformation for the innermost calculation loop of FFT, performing parallel processing on multiple groups of calculation units in single loop iteration, and reducing the proportion of jump branch instructions; S4, after completing the FFT operation, writing the operation result into a target storage area through an optimized instruction sequence. The method provided by the application solves the problems of low efficiency of instruction mapping, low memory access efficiency and insufficient hardware resource scheduling of the existing Falcon algorithm when running on a RISC-V platform.

The application discloses a method for reducing the loss of large dynamic FFT operation by truncation and number system conversion, and relates to the field of radar signal processing. Firstly, by selecting appropriate rotation factor quantization bits and complex multiplication truncation bits, the full frequency domain precision loss is ensured to be not more than a fixed value under the condition of small signal input; then, whether to retain the bit width increased by complex addition operation is judged according to the order corresponding to the number of FFT points required to be operated; finally, according to the operation bit width truncation rule, after completing the entire FFT operation, the FFT operation result represented by fixed-point numbers is converted into the FFT operation result represented by floating-point numbers. The application can effectively retain the spectrum information under the condition of small signal input, avoid the signal distortion caused by the truncation in the FFT processing process, greatly improve the dynamic range, and provide good data support for subsequent fine processing.

Embodiments of the present specification provide a method for constructing a processing circuit for a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes, for a K-point input coefficient sequence to be processed, determining a plurality of candidate decomposition points corresponding to a k-bit coefficient index. Then, starting from a low-bit decomposition point, for each candidate decomposition point, determining the minimum storage cost under each candidate decomposition point according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost evaluation function limits the storage cost to include the cost of a (n-p)th order first transform, the cost of a pth order second transform, and the local cost for inter-level rotation factor multiplication. According to the target decomposition mode, a corresponding memory for the rotation factor is allocated to form a processing circuit.

The invention relates to a method for encoding at least one block of K.Z c source data, delivering at least one codeword of size N.Z c , the method implementing a step of encoding the K.Z c source data using a parity matrix H. According to the invention, the parity matrix H is obtained from a base matrix BG' expressed in the form: (I). The extension matrix C comprises at least two blocks of L rows and at least one block of L columns, where L is an integer between 1 and K − 1, each block of L rows comprising at least one matrix (II) obtained by applying a circular rotation coefficient α to a diagonal matrix of size L X L, where α is an integer between 0 and L − 1, the at least one block of L columns comprising at least two matrices (II) obtained by applying a distinct circular rotation coefficient α to the diagonal matrix of size L X L.

The application relates to a rotation factor storage method, a reading method and a hardware accelerator for FFT operation. The hardware accelerator comprises a rotation factor storage unit for storing sine components or cosine components in rotation factor original data; an index calculation unit for mapping rotation factor original indexes into look-up table indexes of a rotation factor storage table and calculating sine component indexes and cosine component indexes; a folding judgment unit for judging whether the sine component indexes and the cosine component indexes exceed the index range of the rotation factor storage table; a data reading unit for respectively obtaining imaginary part readout values and real part readout values from the rotation factor storage table; and a sign correction unit for performing sign bit correction on the imaginary part readout values and the real part readout values to obtain real parts and imaginary parts of the rotation factors. The embodiment of the application reduces the storage resource occupation of the rotation factors, realizes the compatibility of a single rotation factor table to different point number FFTs, has high data reading precision and small hardware cost.

The invention provides a Hawk algorithm acceleration method based on GPU (Graphics Processing Unit) multi-thread parallel. The GPU multi-thread parallel-based Hawk algorithm acceleration method comprises the following steps of (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallel reconstruction and memory access optimization are carried out; and (4) carrying out FFT / iFFT structured parallel optimization and butterfly operator fusion. According to the method, a coarse-grained parallel butterfly operator execution mode which does not need complex address calculation, does not need shared memory synchronization and does not compete among threads is realized, and the throughput efficiency on the GPU is greatly improved; meanwhile, a parallel execution framework is unified in forward and reverse transformation of the FFT / NTT, and overall recovery can be completed only by using a corresponding reverse twiddle factor and performing simple normalization processing at the tail end in the reverse transformation.

The embodiment of the invention provides a method for executing target transformation and acceleration hardware. Target transformation comprises n rounds of transformation operation, and the method comprises the step of executing a non-first round of transformation operation by utilizing a qth circuit in acceleration hardware, which comprises the following steps: a bit exchange unit in the qth circuit exchanges two specified bits in each data position index of a (q-1) th round of output sequence to obtain a reordered first sequence; when the power distribution of the left twiddle factor in the q-th round is not zero, a left multiplication unit in the q-th circuit multiplies each data of the first sequence by each corresponding twiddle factor indicated by the power distribution of the left twiddle factor to obtain a second sequence; a butterfly operation unit in the qth circuit respectively carries out butterfly operation on specified data pairs in the first sequence or the second sequence to obtain a third sequence; and when the power distribution of the right twiddle factor in the q-th round is not zero, a right multiplication unit in the q-th circuit multiplies each data of the third sequence by each corresponding twiddle factor indicated by the power distribution of the right twiddle factor to obtain a fourth sequence.

The application discloses an anti-side channel attack NTT circuit for a lattice-based cryptographic algorithm, comprising: a control unit mainly controlling the enabling of the underlying components in the structure and the data flow between modules; a storage unit for storing coefficients, random rotation factor addresses and rotation factors; an address generation unit for calculating and generating the storage RAM address of the rotation factor participating in operation and the read address required by the coefficient storage unit; and a coefficient transposition unit for realizing the coefficient reading satisfying the index distance between all NTT stages. The anti-side channel attack NTT circuit for the lattice-based cryptographic algorithm reduces the increase of the modulus multiplication resource when masking the low-latency base-4 CT / GS butterfly unit, realizes the significant reduction of resource consumption while maintaining high security.

The application discloses a hardware accelerator for a key switching algorithm in a CKKS homomorphic encryption algorithm, and belongs to the field of privacy calculation and fully homomorphic encryption hardware acceleration. The hardware accelerator comprises an NTT / INTT circuit and a peripheral polynomial operation circuit. The NTT / INTT circuit is used for realizing domain transformation of a polynomial, and comprises a plurality of parallel butterfly operation cores and an NTT control module for generating a memory address and a data flow control. The butterfly operation core comprises a storage array, a calculation array and a peripheral digital circuit. The storage array is used for storing a rotation factor, and the calculation array is used for calculating a partial product of the rotation factor and polynomial coefficient multiplication. The hardware accelerator can realize highly parallel key switching operation, solves the problem of excessive fully pipelined data flow storage overhead caused by data dependency in other works, and effectively reduces the area and power consumption of the circuit.

Provided in the embodiments of the present application are a data processing method and a related apparatus. In the present application, a matrix multiplication operation is performed on a rotation factor matrix and an input signal by means of cube units, so as to accelerate in combination with the cube units a fast Fourier transform (FFT) operation performed on the input signal. The method comprises: on the basis of the length of a first input signal, generating a rotation factor matrix, wherein the rotation factor matrix comprises a plurality of rotation factors, which are used for performing an FFT operation on the first input signal; and performing a matrix multiplication operation on the rotation factor matrix and the first input signal, so as to obtain a first matrix-product matrix, wherein the first matrix-product matrix comprises a result of performing the FFT operation on the first input signal.

The embodiment of the application discloses a method, device and computing equipment for performing FFT calculation, and belongs to the technical field of computers. The method comprises the following steps: dividing the FFT calculation into multiple calculation stages based on the length of a data sequence to be calculated; for at least one target calculation stage in the multiple calculation stages, determining a merging matrix corresponding to the target calculation stage based on a base corresponding to each of the multiple calculation stages, and the execution order of the target calculation stage in the multiple calculation stages, wherein the merging matrix is the product of a discrete Fourier transform (DFT) coefficient matrix in the target calculation stage and a rotation factor; and determining the product of the input sequence of the target calculation stage and the merging matrix as the output sequence of the target calculation stage when the target calculation stage is executed. According to the application, the calculation amount corresponding to the calculation stage can be reduced, and the execution efficiency of the FFT calculation can be improved.

Embodiments of the present specification provide a method for storing or reading a rotation factor in a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes determining a target rotation factor to be stored, whose power is a result of a multiplication of a first factor of a first number of bits and a second factor of a second number of bits modulo a target value; and storing the target rotation factor by a two-level storage manner, the two-level storage manner including storing the target rotation factor at a first address in a rotation factor storage, wherein the rotation factor storage includes a first number of first storage units, the first number being a number of different modulo multiplication results generated by the first factor of the first number of bits and the second factor of the second number of bits; and storing an index value pointing to the first address at a second address in an index storage, wherein the index storage includes a target value of second storage units, the second address corresponding to the power of the target rotation factor; and the target value is greater than the first number.

A data security transmission system and method for a task supervision system, belonging to the field of digital communication technology. In the system, a segmentation module is configured to segment the data to be transmitted into two... K Bit data is gradually decomposed into 2 K‑N Group 2 N Bit data group, for 2 N The bit data group is reordered according to the encryption rules to generate 2 N Bit-encrypted data sequence; cyclic encryption rotation factor generation module generates N encryption rotation factors; calculation module includes N levels of calculation sub-modules, the nth level calculation sub-module includes 2 N‑n Two basic encryption units, the first level computation submodule has 2. N‑n Input 2 basic encryption units N The bit-encrypted data sequence uses the output of the basic encryption unit of the (n-1)th level computational submodule as the input of the basic encryption unit of the nth level computational submodule. Encryption operations are performed sequentially using encryption rotation factors until the Nth level computational submodule serially outputs the ciphertext data sequence. This invention effectively reduces the total number of transformation units used and avoids the complexity of cross-connections.

The invention is applicable to the field of digital signal processing, and discloses an FFT (Fast Fourier Transform) calculation method, system, equipment and medium based on CORDIC (Coordinated Rotation Digital Integrated Circuit) of an angle precoding circumference system, the method comprises the following steps: acquiring an input angle to be calculated, and obtaining a vector and a residual angle by inquiring a predefined distribution table; based on residual angle block coding, obtaining a non-scaling twiddle factor corresponding to the coded angle through Taylor expansion, and rotating the vector to obtain a rotated vector and a micro angle; obtaining a trigonometric function value corresponding to the input angle by combining approximate processing with multiply-add operation based on the rotated vector and the micro angle; and according to the received sampling sequence data, applying the trigonometric function value as a twiddle factor, and executing complex multiplication and data exchange in each level of butterfly operation unit of the FFT to obtain FFT spectrum data. The CORDIC algorithm with few iterations, high calculation precision and low hardware resource consumption is realized, and the FFT calculation efficiency and performance are improved.

The invention discloses a method, a device and a chip for number-theory transformation. The method for number-theoretical transformation comprises the following steps: setting and storing at least two sub-twiddle factor sets with a predetermined number for twiddle factor sets of transformation operation and inverse transformation operation for the number-theoretical transformation, the sum of the preset number of the sub twiddle factors in the sub twiddle factor set is smaller than the number of the twiddle factors in the twiddle factor set; and generating each twiddle factor in the set of twiddle factors by a predetermined combination calculation of sub-twiddle factors in the at least two sub-twiddle factor sets, where a first calculation time of a transform operation or an inverse transform operation of the number-theoretical transform is greater than or equal to a second calculation time of the predetermined combination calculation. In this way, the storage amount can be reduced on the premise that the calculation efficiency is not affected.

The present invention discloses a method for realizing multi-channel parallel single-bit frequency measurement based on FPGA, which belongs to the field of digital signal processing technology. The method of the present invention comprises: first, single-bit quantization is performed on 16 input signals; then, 32-point FFT parallel processing is performed on each quantized data; then, the 16-channel FFT results are multiplied by a rotation factor to construct a complete 512-point FFT; then, the symmetry of the FFT is utilized to calculate only the amplitude of the first 256 points, and an approximate algorithm is used to quickly calculate the amplitude to find the maximum point and its adjacent points; finally, the RIFE algorithm is used in combination with a lookup table method to correct the maximum point and accurately calculate the signal frequency. The present invention greatly reduces the use of multipliers, reduces hardware resource consumption and computational complexity, significantly improves the computing speed, and can quickly and accurately realize frequency measurement of multi-channel signals by means of parallel processing, approximate calculation, and a lookup table method.

The application discloses a hardware accelerator and a hardware acceleration method based on three-dimensional number theory transformation. The hardware accelerator comprises a control unit, a coefficient storage, a dimension switching rotation factor storage and a calculation component. The method comprises generating an address signal, a control signal, a polynomial coefficient and a dimension switching rotation factor, sequentially receiving the address signal, the control signal, the polynomial coefficient and the dimension switching rotation factor to perform three-dimensional number theory transformation, and outputting a transformation access result. The embodiment of the application can simplify the complex data dependency relationship between stages through a three-dimensional number theory transformation algorithm without additional hardware units, and realizes on-chip access without conflict. The application can be widely applied to the technical field of hardware acceleration.

The application discloses a kind of NTT hardware system and control method based on double coefficient folding storage and adaptive scheduling, it is related to post quantum cryptography hardware acceleration technical field.Its hardware system includes input layer and bit inversion module, double coefficient folding unit module, single BRAM storage module, adaptive conflict-free scheduling subsystem, rotation factor processing path and BFU butterfly computation unit;Its control method is compressed by double coefficient folding storage to splice logical coefficient, to realize high-bandwidth storage with the theoretical lower limit physical depth single body BRAM, and dynamically switches inner layer and interlayer access mode according to calculation level by adaptive conflict-free scheduling subsystem, eliminates variable step size memory conflict, realizes full-pipeline bubble-free operation.The hardware system of the application significantly reduces the on-chip storage area consumption, improves the calculation throughput and timing convergence, and is suitable for hardware acceleration implementation of post quantum cryptography algorithm.

Embodiments of the present application provide a homomorphic encryption bootstrapping method and device, a processor, a system on chip and a computing device. The homomorphic encryption bootstrapping method comprises: homomorphic encryption of a plaintext belonging to a plaintext space of a first variable type is performed using an RLWE key to obtain a first RLWE ciphertext; a plurality of rotation factors based on a polynomial ring in which the RLWE key is located are determined based on a plurality of RLWE encryption matrices of an LWE private key vector, the polynomial ring corresponding to a plaintext space of a second variable type; and rotation processing is sequentially performed on the first RLWE ciphertext based on the plurality of rotation factors to obtain a second RLWE ciphertext after homomorphic decryption. In the process of homomorphic encryption bootstrapping, the scheme of the embodiments of the present application realizes the transformation of the plaintext corresponding to the RLWE ciphertext from the plaintext space of the first variable type to the plaintext space of the second variable type, and improves the computing efficiency of the ciphertext computation.