55 results about "Rotation factor" patented technology

The embodiment of the invention provides a number-theory transformation processing device based on a post-quantum encryption algorithm. The device comprises a control unit, a ping-pong storage unit, a butterfly unit and a nonvolatile storage unit, the control unit is used for receiving the polynomial of the post-quantum encryption algorithm, splitting the polynomial into coefficients and writing the coefficients into the ping-pong storage unit; writing a preset twiddle factor into the nonvolatile storage unit; and calling the ping-pong storage unit and the nonvolatile storage unit to read and write data according to a preset processing flow of the post-quantum encryption algorithm, and calling the butterfly unit to calculate. According to the embodiment of the invention, the polynomial is split into coefficients through the control unit, the ping-pong storage unit and the nonvolatile storage unit are called to read and write data according to the preset processing flow of the post-quantum encryption algorithm, and the butterfly unit is called to calculate, so that the running speed of the algorithm on hardware is optimized; and meanwhile, the performance of the post-quantum encryption algorithm can be greatly improved.

The embodiment of the invention provides an NTT acceleration chip. The chip comprises a twiddle factor calculation module which comprises a plurality of pre-calculation units and a plurality of real-time calculation units, and the plurality of pre-calculation units are used for calculating a plurality of initial row twiddle factors and row-to-row stepping factors by parallel execution and utilization of primitive unit roots; the plurality of real-time calculation units are used for executing one row twiddle factors in the plurality of initial rows obtained by the plurality of pre-calculation units in parallel, and repeatedly and iteratively calculating twiddle factors of other rows according to the inter-row stepping factors; the transpose module comprises a plurality of transpose units and is used for performing transpose processing on the input sequence in parallel to obtain a transpose sequence; and the NTT calculation module comprises a plurality of butterfly calculation units and is used for executing butterfly operation of each order and point number according to the twiddle factor obtained by the twiddle factor calculation module and the transposition sequence obtained by the transposition module in parallel to obtain an output sequence. The NTT calculation efficiency can be improved.

The embodiment of the invention provides a method for executing FFT (Fast Fourier Transform), a processor, electronic equipment and a storage medium. The method comprises the following steps: acquiring a point number N corresponding to a to-be-executed FFT operation; dividing the FFT operation into M-level operation according to the point number N; dividing each level of FFT operation into at least one group of butterfly operations according to twiddle factors corresponding to each butterfly operation unit in the FFT operation; in each level of operation, according to the first input value, the second input value and the twiddle factor of each butterfly operation unit, executing each group of butterfly operation in sequence to obtain a butterfly operation output sequence; and determining a first input value, a second input value and a twiddle factor of each butterfly operation unit in the (m + 1) th-level operation according to the butterfly operation output sequence corresponding to the mth-level operation, and continuously executing each group of butterfly operations in the (m + 1) th-level operation until the execution of the M-level operations is finished, thereby obtaining a result sequence corresponding to the FFT operation. According to the embodiment of the invention, the operation cost of FFT can be reduced, and the operation efficiency is improved.

The invention discloses a streamlined design circuit of an NTT algorithm, and belongs to the technical field of integrated circuit design, the circuit comprises a streamlined butterfly unit, a data storage module, a butterfly address remapping module and a twiddle factor module, the circuit supports a forward NTT algorithm and a reverse NTT algorithm at the same time, supports operation of variable parameters on different domains, and adopts a streamlined method. Based on a single-port SRAM storage polynomial coefficient, a butterfly address remapping method is provided, and the method has the remarkable advantages of being small in circuit area and high in performance.

Embodiments disclosed in this application pertain to the field of computer technologies, and in particular, to a method for performing FFT, a processor, and a computing device. The method includes: A processor responds to an execution request of fast Fourier transform FFT calculation of an application, and decomposes the FFT calculation into a plurality of calculation stages. The processor sequentially executes the plurality of calculation stages, where when a target calculation stage is executed, a vector operation circuit performs rotation factor calculation, and a matrix operation circuit performs DFT calculation. After the execution of the plurality of calculation stages is completed, the processor determines an execution result of the FFT calculation based on an execution result of a last calculation stage, and returns the execution result to the application. vector operation circuit matrix operation circuit

The application relates to the technical field of signal processing, and discloses a code Doppler effect elimination method in a signal combination process. Before signal combination, a time domain cyclic shift is performed on the autocorrelation function before combination, or a frequency domain rotation factor compensation is performed on the FFT transformation of the autocorrelation function, and then IFFT transformation is performed to the time domain. The application solves the problem that the prior art lacks a technical scheme capable of efficiently and accurately eliminating the code Doppler effect.

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

The invention discloses a twiddle factor table generation method for number theory transformation, which is mainly based on decomposition of a polynomial on a finite field and comprises the steps of key data generation, polynomial decomposition and data selection, inverse number theory transformation data calculation, Montgomery domain conversion and the like. The method comprises the following steps of: decomposing five types of polynomials of an original three-term expression, square difference, square sum, cubic difference and cubic sum according to levels and a specific sequence, then selecting negative values of constant term parts of partial polynomials to form a rotation factor table of positive number theory transformation, and then calculating a rotation factor table used by inverse number theory transformation according to the rotation factor table of the positive number theory transformation, and finally, converting the twiddle factor table data to the Montgomery domain to obtain a final twiddle factor table. According to the technical scheme, the implementation efficiency of number theory transformation can be remarkably improved, and finer granularity and a wider range are provided for selection of lattice-based password parameters; and the efficiency of anti-quantum encryption, decryption and signature algorithms is improved.

The embodiment of the present specification provides an NTT acceleration chip. The chip comprises: a rotation factor calculation module comprising a plurality of pre-calculation units and a plurality of real-time calculation units, the plurality of pre-calculation units are used for performing, in parallel, calculation of initial rows of rotation factors and inter-row stepping factors by using primitive roots; the plurality of real-time calculation units are used for performing, in parallel, repeated iteration calculation of rotation factors of other rows according to the inter-row stepping factors based on the initial rows of rotation factors obtained by the plurality of pre-calculation units; a transposition module comprising a plurality of transposition units, which are used for performing, in parallel, transposition processing on an input sequence to obtain a transposed sequence; and an NTT calculation module comprising a plurality of butterfly calculation units, which are used for performing, in parallel, butterfly operation of each order and point number based on the rotation factors obtained by the rotation factor calculation module and the transposed sequence obtained by the transposition module to obtain an output sequence. The efficiency of NTT calculation can be improved.

The application provides an ML-DSA-oriented low-resource number theory transformation acceleration system and method. The system comprises a control addressing module, a first storage module, a second storage module and an operation module. The first storage unit and the second storage unit in the storage module are used for storing the coefficients of a polynomial, and the third storage unit and the fourth storage unit are used for storing rotation factors and inverse rotation factors. The control addressing module determines a plurality of target coefficient addresses and a plurality of target rotation factor addresses based on the current operation mode, the current operation round and the current operation count. The first operation unit and the second operation unit in the operation module read the coefficients and the rotation factors respectively, operate the read coefficients, and store the operation results to the target coefficient addresses. The addressing method is simple, the operation unit accesses multiple coefficients at a time, and the reading and writing efficiency is high.

The present application provides an NTT circuit, an NTT method, and an electronic device. The NTT circuit comprises a first storage module, a first operation module, a first rotation module, and a second storage module. The first storage module is configured to store J4 pieces of first data. The J4 pieces of first data is divided into J2 first data arrays. Each first data array comprises J×J pieces of first data. J is a positive integer. The first operation module is configured to execute an NTT operation on the basis of each first data array to obtain a first operation result. The first rotation module is configured to transform the first operation result on the basis of a first rotation factor to obtain a first transformation result. The first transformation result comprises J×J pieces of second data. The second storage module is configured to store J4 pieces of second data corresponding to the J2 first data arrays. By means of the present application, the computing resources required by an NTT operation are reduced, and power consumption is reduced.

The present invention discloses a calculation method and system for reducing the storage overhead of the rotation transformation in FFT. The method includes: Step 1, calculating n2 discrete Fourier transforms of length n1, where the on-chip cache of the processor can store at most the data required for calculating m discrete Fourier transforms of length n1, and m = on-chip cache of the processor / cache required for calculating the discrete Fourier transform of length n1; Step 2, calculating the rotation factor, performing the rotation transformation, and calculating n1 discrete Fourier transforms of length n2, where the on-chip cache of the processor can store at most the data required for calculating t discrete Fourier transforms of length n2. While maintaining a relatively low computational amount, the present invention effectively reduces the cache overhead required for calculating the rotation factor.

The embodiment disclosed by the application belongs to the technical field of computing, and particularly relates to a method for performing FFT, a processor and a computing device. The method comprises the following steps: in response to an execution request of a fast Fourier transform (FFT) calculation of an application program, a processor decomposes the FFT calculation into multiple calculations; the processor sequentially executes multiple calculation stages, wherein, when a target calculation stage is executed, a rotation factor calculation is executed based on a vector operation unit, and a DFT calculation is executed based on a matrix operation unit; after the execution of the multiple calculation stages is completed, an execution result of the FFT calculation is determined based on an execution result of the last calculation stage, and the execution result is returned to the application program. According to the application, the processor can jointly implement the FFT calculation based on the vector operation unit and the matrix operation unit, and the efficiency of the processor in executing the FFT calculation can be improved.

The present application discloses a method and device for encoding and reading rotation factors, a medium and a chip. The encoding device includes: a first acquisition module, used to obtain the operation information of the data to be processed, the operation information includes the sequence length of the data to be processed and the degree of parallelism during the forward number theory transformation; based on the operation information, determine the various rotation factors required for the data to be processed during the forward number theory transformation; exclude the rotation factors of the data to be processed in the first preset number of stages of the forward number theory transformation; an encoding module, used to construct the storage mapping relationship between the various rotation factors in the remaining stages and the various static random access memories for storing the rotation factors. In an embodiment of the present application, after the storage mapping relationship is constructed based on the encoding device, when storing the various rotation factors based on the storage mapping relationship, the redundant rotation factors in the first b-1 stages do not need to be stored, thereby reducing the storage space overhead of the rotation factors.

To reduce the storage capacity that a Fourier transformation device requires to store a twiddle factor.SOLUTION: A Fourier transformation device which performs fast Fourier transformation or inverse fast Fourier transformation of N points comprises a rotor 222 which performs a rotational operation and a rotation memory 28 which stores a twiddle factor. The rotation memory 28 includes a first rotation memory 43 which stores a plurality of first twiddle factors corresponding to rotation positions obtained by equally dividing 2π by N1 (where n1 is an integer equal to or larger than 3, and N1 is an integer of 2 raised to the power of n1), and a second rotation memory 44 which stores a plurality of second twiddle factors corresponding to rotation positions obtained by equally dividing 2π / N1 by N2, where N / N1 is N2 (n2 is an integer equal to or larger than 1, and N2 is an integer of 2 raised to the power of n2. The rotor 222 comprises a first complex multiplier 41 which has one of the plurality of first twiddle factors selectively set, and a second complex multiplier 42 which is connected to the first complex multiplier 41 in series, and has one of the plurality of second twiddle factors selectively set.SELECTED DRAWING: Figure 5

The invention relates to a method for processing a sensor signal (105). The method comprises the step of determining complex rotation factors (115) for a fast Fourier transform. The complex rotation factors (115) are determined using a processing rule (147), at least a subset of reserved complex rotation factors (145) from a total set of reserved complex rotation factors (145) stored in a non-volatile memory, and at least one signal characteristic derived from the sensor signal (105). The method further comprises the step of performing a fast Fourier transform on the sensor signal (105) using the determined complex rotation factors (115) to provide a processed version (125) of the sensor signal (105).

The present invention discloses a lattice cryptography modular multiplication method and a modular multiplier based on an improved Plantard algorithm. At the level of the modular multiplication method, by preprocessing the rotation factors, the post-processing overhead of the traditional modular multiplication method is eliminated. In terms of hardware implementation, shift-addition is used to replace complex multipliers, and combined with the dynamic bit-width truncation technology, the bit-width of the intermediate data is compressed from 39 bits to 21 bits, significantly reducing the consumption of logic resources, so that the modular multiplication operation in the lattice cryptography digital signature scheme can be completed quickly and efficiently.

The invention discloses an information transmission method and device, relates to the technical field of communication, and is used for reducing the PAPR of a PPDU transmitted under a 320MHz bandwidth. The information transmission method comprises: a transmitting end device generates a PPDU with a 320MHz bandwidth, a part of fields or all fields of the PPDU being rotated on the 320MHz bandwidth through a twiddle factor sequence, the 320MHz bandwidth comprising 16 20MHz, the twiddle factor sequence comprising 16 twiddle factors, each 20MHz corresponding to a twiddle factor; and the sending end equipment sends the PPDU. Exemplary twiddle factor sequences may be [1, 1, 1, 1, 1,-1, 1, 1,-1,-1, 1, 1,-1, 1,-1, 1,-1].

The present invention discloses a data encryption system based on a storage-computing integrated architecture, and relates to the field of data encryption. The data encryption system based on the storage-computing integrated architecture includes: a data receiving subsystem, a storage subsystem, an encryption subsystem, and an output subsystem; the data receiving subsystem is used to receive data to be encrypted and perform preprocessing; the storage subsystem is used to pre-store static parameters in the encryption algorithm, specifically a rotation factor array and a modulus; the encryption subsystem is used to call the static parameters in the encryption algorithm pre-stored in the storage subsystem to perform number theory transformation encryption processing on the pre-processed data to be encrypted. The present invention uses the storage-computing integrated architecture adopted by the encryption subsystem to perform the polynomial multiplication calculation with the largest overhead in the cryptographic algorithm at high speed and low power consumption, and combines number theory transformation and modular reduction operations at the same time, thereby solving the speed and power consumption bottleneck problems caused by data handling in the traditional cryptographic hardware architecture.

The embodiment of the application discloses a data transformation method and device and a storage medium, and belongs to the field of data processing. In the embodiment of the application, the first transformation matrix is obtained by transforming an original transformation matrix according to the symmetry of a rotation factor in NTT. Thus, part of the matrix elements in the first transformation matrix has symmetry, so that the data processing results corresponding to the part of the matrix elements in the first transformation matrix are obtained, the data processing results corresponding to other matrix elements are restored, and then each output data is obtained. That is, in the embodiment of the application, the data processing results corresponding to part of the matrix elements are obtained, and all transformation information can be represented, the complexity of data transformation is reduced, and the transformation speed is accelerated.

The present application is applicable to the field of data processing technology, and provides a method for implementing fast Fourier transform and inverse transform. In the embodiment of the present application, the data length of the data to be calculated is obtained; when the data length of the data to be calculated is less than or equal to half of the registers in the preset register group, the register group is discretized, and the data to be calculated and the first preset rotation factor are input into the discretized register group; the connection between the register group and the preset two-dimensional systolic array is reconstructed through re-discrete processing; the register group after re-discrete processing is butterfly operated according to the preset Fourier transform rule, and the fast Fourier transform result of the data to be calculated is determined according to the butterfly operation result, thereby improving the calculation speed when solving the fast Fourier transform result of the data.

The application provides a Hawk algorithm acceleration method based on GPU multi-thread parallelism. The Hawk algorithm acceleration method based on GPU multi-thread parallelism comprises the following steps: (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallelization reconstruction and memory access optimization; (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion. The application realizes a coarse-grained parallel butterfly operator execution mode without complex address calculation, without shared memory synchronization, and without competition between threads, greatly improving the throughput efficiency on the GPU; meanwhile, the application unifies the parallel execution framework in the forward and inverse transformations of FFT / NTT, wherein the inverse transformation only needs to use the corresponding inverse rotation factor and perform simple normalization processing at the end to complete the overall recovery.

The present application discloses a device and method for encoding and reading rotation factors, a medium and a chip. The encoding device includes: a first acquisition module, used to obtain the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation; determine the various rotation factors required for the data to be processed in each stage of the inverse number theory transformation; obtain the target storage rotation factor of each stage; an encoding module, used to construct a storage mapping relationship between the target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to preset conditions. After the encoding device in the present application constructs the storage mapping relationship, when storing each rotation factor based on the storage mapping relationship, it can exclude redundant rotation factors in each stage, thereby reducing the storage space overhead of the rotation factor.

Method for encoding source data, method for decoding code words, corresponding devices and computer program. The invention relates to a method for encoding at least one block of source data, delivering at least one code word of size , said method implementing a step of encoding said source data using a parity matrix . According to the invention, said parity matrix is ​​obtained from a basic matrix expressed in the form: The extension matrix comprises at least two blocks of rows and at least one block of columns, with an integer between 1 and , each block of rows comprising at least one matrix obtained by applying a circular rotation coefficient to a diagonal matrix of size , with an integer between 0 and , said at least one block of columns comprising at least two matrices obtained by applying a distinct circular rotation coefficient to said diagonal matrix of size .Figure for abstract: Figure 5A.

The invention relates to a fast Fourier transform method and device for improving the utilization rate of a storage space. The fast Fourier transform method comprises the following steps of: 1, writing input data into the storage space in an address close arrangement form; 2, calculating a twiddle factor, and storing the twiddle factor into a storage space; 3, FFT input data processing is carried out, specifically, step 31, FFT input data is subjected to data inverted-order storage; step 32, performing data operation, specifically, step 321, expanding the twiddle factors obtained in the step 2 to obtain a twiddle factor complete set; and step 322, performing butterfly operation, and obtaining output Fourier transform data after continuous traversal is completed. According to the method, the storage resources required by the input data and the output data are reduced by converting the floating point data format of the input data and adapting the adder and the multiplier of the computing resources; and the aim of saving memory resources is fulfilled on the premise of ensuring the calculation efficiency.

The application provides a Falcon signature FFT acceleration method for a RISC-V architecture. The method comprises the following steps: S1, adopting a Union data processing mechanism to complete data type conversion, directly calling RISC-V native double-precision hardware floating point instructions for FFT complex number operation, and accurately controlling register allocation; S2, introducing a cache prefetch mechanism, storing batch of discrete distributed complex rotation factors in a continuous intermediate cache array in advance before executing the FFT core calculation loop, changing the discrete real-time data fetching mode, and sequentially addressing to complete rotation factor reading; S3, adopting multi-loop loop unrolling transformation for the innermost calculation loop of FFT, performing parallel processing on multiple groups of calculation units in single loop iteration, and reducing the proportion of jump branch instructions; S4, after completing the FFT operation, writing the operation result into a target storage area through an optimized instruction sequence. The method provided by the application solves the problems of low efficiency of instruction mapping, low memory access efficiency and insufficient hardware resource scheduling of the existing Falcon algorithm when running on a RISC-V platform.

The application discloses a method for reducing the loss of large dynamic FFT operation by truncation and number system conversion, and relates to the field of radar signal processing. Firstly, by selecting appropriate rotation factor quantization bits and complex multiplication truncation bits, the full frequency domain precision loss is ensured to be not more than a fixed value under the condition of small signal input; then, whether to retain the bit width increased by complex addition operation is judged according to the order corresponding to the number of FFT points required to be operated; finally, according to the operation bit width truncation rule, after completing the entire FFT operation, the FFT operation result represented by fixed-point numbers is converted into the FFT operation result represented by floating-point numbers. The application can effectively retain the spectrum information under the condition of small signal input, avoid the signal distortion caused by the truncation in the FFT processing process, greatly improve the dynamic range, and provide good data support for subsequent fine processing.

An embodiment of the present invention provides a method, a processor, an electronic device, and a storage medium for performing FFT. The method includes: obtaining the number of points N corresponding to the FFT operation to be performed; dividing the FFT operation into M-level operations according to the number of points N; dividing each level of the FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to the respective butterfly operation units in the FFT operation; in each level of operation, sequentially performing each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; determining the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation according to the butterfly operation output sequence corresponding to the m-th level of operation, and continuing to perform each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are completed, obtaining a result sequence corresponding to the FFT operation. The embodiment of the present invention can reduce the operation cost of FFT and improve the operation efficiency.

The present invention relates to the field of wireless communication, and provides a computing unit and an FFT processor based on a coarse-grained reconfigurable architecture. The computing unit is used to perform one butterfly operation, and specifically includes: an input stage for providing the calculation data and rotation factors required for the operation; an addition stage for performing the first addition and subtraction operations on the calculation data; a multiplication stage for selecting, according to the rotation factors, to multiply the result of the first addition and subtraction operation by the rotation factors, perform the second addition and subtraction operation, or directly output; and an output stage for outputting the operation result of the multiplication stage. The present invention enables one butterfly operation to be completed only by using one computing unit, and reduces the precision loss as much as possible while ensuring that the data stream bit width remains unchanged.

Embodiments of the present specification provide a method for constructing a processing circuit for a target transform. The target transform is a discrete transform or its inverse transform that transforms an input coefficient sequence into an output coefficient sequence based on a rotation factor. The method includes, for a K-point input coefficient sequence to be processed, determining a plurality of candidate decomposition points corresponding to a k-bit coefficient index. Then, starting from a low-bit decomposition point, for each candidate decomposition point, determining the minimum storage cost under each candidate decomposition point according to a decomposition cost evaluation function through recursive index bit number decomposition for several levels, so as to determine a target decomposition mode of the k-bit coefficient index with the minimum storage cost. The decomposition cost evaluation function limits the storage cost to include the cost of a (n-p)th order first transform, the cost of a pth order second transform, and the local cost for inter-level rotation factor multiplication. According to the target decomposition mode, a corresponding memory for the rotation factor is allocated to form a processing circuit.