Multipath hybrid-based FFT reconfigurable butterfly arithmetic unit

Abstract

A FFT reconfigurable butterfly-shaped arithmetic unit with multiple mix bases is composed of a control unit, a first selection switch unit and an arithmetic unit. The control unit is used for generating an operation instruction according to the received data to be operated, wherein, the data to be operated comprises a digital signal to be processed, a rotation factor and a preset rotation factor coefficient; the first selection switch unit is configured to select a corresponding conduction mode according to an operation instruction. The operation unit is configured to perform butterfly operation on the data to be operated according to the conduction mode. By adopting the technical proposal of the invention, the utilization efficiency of the electronic components in the butterfly-shaped arithmetic unit is improved, the circuit hardware resources and power consumption are reduced, and the accuracy and real-time performance of the calculation data are improved.

Description

technical field [0001] The technical field of chip design of the present invention, in particular, relates to a multi-channel mixed-radix FFT reconfigurable butterfly operator. Background technique [0002] In digital signal processing, especially for long sequences, discrete Fourier transform (Discrete Fourier Transform, DTF) is a particularly important mathematical transformation. Digital signal processing can be carried out by using digital operations in frequency domain sampling, which greatly increases the flexibility of digital signal processing. For the DFT algorithm of general numbers, the operation is performed by converting the DFT of large points into DFT of small points to achieve the purpose of reducing the computational complexity. The industry usually uses Fast Fourier Transform (FFT) to realize DFT Transformation, the commonly used algorithms for calculating FFT are base 2FFT and base 4FFT, and the number of points is limited to the power of 2 or the power o...

AI Technical Summary

Problems solved by technology

For the DFT algorithm of general numbers, the operation is performed by converting the DFT of large points into DFT of small points to achieve the purpose of reducing the computational complexity. The industry usually uses Fast Fourier Transform (FFT) to realize DFT Transformation, the commonly used algorithms for calculating FFT are base 2FFT and base 4FFT, and the number of points is limited to the power of 2 or the power of 4, which limits the range of options for the number of question points

For some applications such as Synthetic Aperture Radar (SAR) signal processing, especially in the spotlight mode, due to the limitation of processing time and area, the points of each processing data cannot be extended to satisfy the base 2 or Base 4FFT algorithm, especially for large-point FFT, otherwise it will prolong the calculation time and consume more memory space

[0003] In the prior art, the non-power-of-two point number FFT transformation is usually carried out bit sequence zero padding, so that the sequence length after zero padding meets the processing range of the FFT / IFFT processor; Perform FFT / IFFT calculations, but this approach introduces noise, reduces accuracy, and may cause loss to the calculation performance of the chip

Especially in the fixed-point FFT and IFFT in the prior art, in order to prevent data overflow, the input of each stage of butterfly operation needs to be divided by the number of input data, for the FFT or IFFT whose base number is greater than 2, this will cause the loss of each stage of input data There are too many bits, and the calculation accuracy error is large, which affects the performance of the communication system

Images