50 results about "Instruction selection" patented technology

The invention discloses a tool calling method based on a large language model, and the method comprises the steps: obtaining a question text which comprises task information; obtaining a matched first candidate tool set in the question text and a preset tool library; screening the first candidate tool set on the basis of locally available current hardware resources and / or available current online resources of a cloud application program interface (API) to obtain a second candidate tool set; determining a target tool matched with the task information from a second candidate tool set based on a large language model, and generating a tool calling instruction based on the target tool; selecting a called target tool based on the tool calling instruction, and obtaining an output result of the target tool; based on the question text and the output result, reply text corresponding to the large language model is obtained. According to the method, the tool with a higher matching degree can be obtained in combination with the resource occupation conditions of the tools of multiple platforms, and efficient utilization of resources and dynamic scheduling of task tools are realized.

The invention discloses a method and device for generating a management decision, equipment and a storage medium, and the method comprises the steps: collecting related data of a property management system, and obtaining a long text data set; cleaning and preprocessing the long text data set by using an RAG technology to obtain preprocessed property management data; constructing a property manager agent; performing reasoning analysis on the property management data through the property manager agent to generate a management decision; wherein the property manager agent construction comprises the following steps: setting a task; calling a large language model to process the task; executing an instruction output by the large language model to obtain a historical processing result; wherein the instruction comprises an analysis instruction, a selection execution tool and an execution tool sequence; and storing the historical processing result by utilizing a cache processing mechanism. The property manager intelligent agent not only can improve the efficiency and quality of property management, but also can improve the life experience of residents.

To provide a business information processing system that enables users to efficiently carry out business in a situation where a plurality of business systems exist within an organization. [Solution] The business information processing system includes a language model 11 that has been machine-learned to output a response when an output instruction is input in natural language, multiple business support systems 13, and an API 14 that is an interface to the business support systems. When an output instruction or an output request is input to the language model 11, the language model 11 selects the API 14 required for the output instruction or output in accordance with the output instruction, and sends a request to the API 14.

Provided is a secure execution of a first instruction by processing means of an electronic system, comprising fetching (S1) said first instruction in an execution pipeline of the processing means, determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack, and executing (S4) said selected second instructions instead of said first instruction.

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

A parameterized instruction selection method is applied to optimizing a compiling process executed by a compiler. According to the parameterized instruction selection method, a corresponding machine instruction set is generated for instructions in a to-be-compiled code in advance during compiling, so that one or more corresponding machine instructions which can be selected by each instruction in the code during compiling are indicated on the basis of the machine instruction set; according to the method, the compiler does not select a default machine instruction for an instruction in a code any more, the compiler is guided to select different machine instruction combinations in the compiling process, so that multiple different target files are obtained, finally, the target file with the optimal execution performance is selected by executing the multiple target files, the flexibility of the instruction selection process is improved, and the user experience is improved. And compiling to obtain the target file with higher execution performance.

The invention discloses a programmable instruction distribution system, belongs to the technical field of general graphic processing units, and aims to solve the technical problems that when branch instruction segments and loop instruction segments are processed, a large number of invalid operations exist in a GPGPU instruction pipeline, a plurality of clock cycles are occupied, the execution efficiency and parallel performance of a GPGPU are reduced, and the execution efficiency of the GPGPU is reduced. According to the technical scheme, the system comprises an instruction splitting unit and an instruction replaying unit; the instruction splitting unit is used for splitting the complete instruction segment into a plurality of sub instruction segments and completing rapid distribution of a specific instruction segment; the instruction splitting unit comprises an instruction selection switch and a programmable instruction queue; wherein the instruction selection switch is used for generating a corresponding branch instruction section from a programmable instruction queue according to an instruction mask, and distributing a branch instruction; the instruction replay unit is used for recording the distributed instruction segments and controllably replaying the corresponding instruction segments; the instruction replay unit includes register redirection logic, an instruction counter, and an instruction record queue.

The invention discloses a method for realizing automatic generation of an RPA process through reinforcement learning, and the method comprises the following steps: 1, training a multi-modal large model, and enabling the multi-modal large model to have the task process decomposition capability based on page screenshot and task description; 2, training a process supervision reward model to enable the process supervision reward model to judge whether the next generation step is correct or not according to the page screenshot, the task description and the context; 3, performing reinforcement learning training on the multi-modal large model by using a process supervision reward model to obtain a task process decomposition model; and step 4, generating detailed RPA steps based on the trained task process decomposition model, then calling a general large model API to convert each RPA step into an actual RPA instruction, and forming a complete RPA process by the RPA instructions. According to the method, the illusion generated by the model in the process generation is greatly reduced, the task process decomposition capability of the model is improved, and the RPA instruction selection generation accuracy is enhanced.

A parameterization instruction selection method, applied to optimizing a compilation process executed by a compiler. In the parameterization instruction selection method, during compiling, corresponding machine instruction sets are pre-generated for instructions in a code to be compiled, and one or more corresponding machine instructions that can be selected by each instruction in the code during compiling are indicated on the basis of the machine instruction sets, so that a compiler does not select a default machine instruction for the instruction in the code any more, and the compiler is guided to select different machine instruction combinations during compiling, so as to obtain a plurality of different target files; finally, a target file having optimal execution performance is selected by executing the plurality of target files. Thus, the flexibility of an instruction selection process is improved, and the target file having higher execution performance is obtained by means of compiling.

The invention discloses an instruction processing method, device and equipment and a computer readable storage medium, and belongs to the technical field of information. The method comprises the steps that a first storage unit corresponding to a first instruction bundle needing to be processed is determined in a processor, the first instruction bundle comprises a first instruction, the first instruction carries a first identifier of the first instruction bundle, and the processor further comprises a calculation unit corresponding to the first storage unit; under the condition that the number of idle units in the first storage unit is not smaller than the occupied number of the storage units of the first instruction bundle and the calculation units corresponding to the idle units meet the calculation requirement of the first instruction bundle, the first instruction is stored in the idle units, and the calculation units are used for calculating the selected instruction based on the first identifier. When the first instruction needs to be selected for calculation, the first instruction can be selected according to the first identifier, the storage position of the first instruction in the storage unit does not affect instruction selection, different instruction bundles can be stored in a staggered mode, the storage flexibility is high, and the utilization rate of the storage unit is high.

The application relates to an RPA process design system based on a VS Code plug-in and belongs to the technical field of process automation. The system comprises a text editing module, a graphical parameter configuration module, an engineering management module and an execution adaptation module. The text editing module loads preset instruction libraries and method signature libraries, receives structured instructions, performs format checking and parameter completion, analyzes and generates a memory instruction sequence list; the graphical parameter configuration module listens to the instruction selection state, generates a parameter form, verifies the validity of input parameters, generates instruction-parameter data and stores the data into a to-be-processed data pool; the engineering management module generates a standard directory structure, performs version control and conflict detection; and the execution adaptation module extracts data and converts the data into an executable script and performs verification. The system can efficiently realize the design, management and execution of an RPA process, and improves the convenience and accuracy of robot process automation design.

The embodiment of the invention belongs to the technical field of research and development design, is applied to a code test scene, and relates to a code test method, device and equipment and a storage medium thereof. Starting an integrated test tool; screening out a to-be-tested target class; traversing methods in the target class, and generating test index data of the target structure; receiving a second execution instruction; and selecting a target test interface, calling the target test interface, and screening out the to-be-tested method from the test index data for testing. According to the code testing method, all the target classes in the code are screened through the screening component, the test index data of the target structure are generated according to the relation between the classes and the method names, and then the test index data of the target structure are obtained through the interface type of the target test interface. Different test modes are combined with the test index data to test the target code, so that the method is more scientific and comprehensive, test omission is avoided, and the test coverage rate before online is ensured as much as possible.

1. The name of the design product: graphical user interface of instruction issuing function operation of electronic equipment. 2. The use of the design product: an electronic device. 3. The design points of the design product: in the graphical user interface. 4. The picture or photo that best shows the design points: design 1 interface change state diagram 2. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: for the operation of the instruction issuing function of the vehicle intelligent networked platform. 7. The human-computer interaction mode of the graphical user interface: the user touches the "instruction issuing" button of design 1 front view, enters design 1 interface change state diagram 1, the user touches and checks the target vehicle in the vehicle list, enters design 1 interface change state diagram 2, the user touches the drop-down icon of the instruction selection module, enters design 1 interface change state diagram 3, the user touches the selected target instruction selection, enters design 1 interface change state diagram 4, the user touches the drop-down icon of the instruction type module, enters design 1 interface change state diagram 5, the user touches the selected target instruction type, enters design 1 interface change state diagram 6, the user touches the drop-down icon of the instruction name module, enters design 1 interface change state diagram 7, the user touches the selected target instruction name, enters design 1 interface change state diagram 8, the user touches the "start execution" button, enters design 1 interface change state diagram 9. The user touches the "instruction issuing" button of design 2 front view, enters design 2 interface change state diagram 1, the user touches and checks the target vehicle in the vehicle list, enters design 2 interface change state diagram 2, the user touches the drop-down icon of the instruction selection module, enters design 2 interface change state diagram 3, the user touches the selected target instruction selection, enters design 2 interface change state diagram 4, the user touches the drop-down icon of the instruction type module, enters design 2 interface change state diagram 5, the user touches the selected target instruction type, enters design 2 interface change state diagram 6, the user can set the target parameter value in the instruction parameter module, the user touches the drop-down icon of the instruction name module, enters design 2 interface change state diagram 7, the user touches the selected target instruction name, enters design 2 interface change state diagram 8, the user touches the "start execution" button, enters design 2 interface change state diagram 9. 8. Other circumstances that need to be explained: the text and / or numbers in each view interface can be replaced, and the number of characters does not constitute a limitation on the replacement characters.

The invention discloses a Chinese programming centralized control software development method, and relates to the technical field of stage control, in particular to a method for improving creativity implementation efficiency, which comprises the following steps: constructing a special Chinese programming instruction set for a stage, creating a Chinese instruction conforming to stage terminologies and natural language habits; and designing a stage visual programming interface: establishing a visual operation platform adaptive to stage function partitions, setting light, sound equipment, a mechanical device, a curtain instruction area, a global process arrangement area and a stage effect real-time preview area, presenting Chinese instructions in a visual component form, and realizing instruction selection, parameter setting, process arrangement and effect preview. According to the stage centralized control system development method based on simplified Chinese programming, the problems that an existing stage control system is large in development difficulty and high in use and training cost are solved, and stage workers can conveniently and efficiently create a unique stage effect.

The application discloses a load switching circuit, a load switching method and a household device, wherein a receiving module, a control module, a resistive load module and an inductive load module are included. The receiving module acquires an instruction signal; the receiving module sends the instruction signal to the control module; the control module determines a load module corresponding to the instruction signal according to the instruction signal, selectively controls the resistive load module or the inductive load module to work, receives a control signal transmitted by the control module through the receiving module, and transmits the control signal to the resistive load module and the inductive load module; according to specific instructions of the control signal, it is determined whether the resistive load module or the inductive load module works, different load type modules work according to user requirements, and the problem that different loads require different topological circuit requirements is overcome.

Provided in the present disclosure are an operation control method and apparatus for a cloud game, and a computer device and a storage medium, which are applied to a cloud game client. The method comprises: in response to an operation instruction selection of a first user for a target cloud game, determining a selected target operation instruction subset in an operation instruction set, wherein the operation instruction set comprises at least one operation instruction subset associated with the target cloud game; and receiving and presenting game video stream data which is obtained in response to a target operation instruction of the target operation instruction subset.

The application provides a pipeline instruction distribution method, comprising the following steps: calculating the load time of each pipeline, and sorting the pipelines according to the load time, and setting the pipeline priority according to the sorting result; calculating the waiting time of each instruction, and sorting the instructions according to the waiting time, and setting the instruction priority according to the sorting result; and distributing the instructions to the corresponding pipelines according to the instruction priority and the pipeline priority. The pipeline instruction distribution method provided by the application can realize the dynamic balance of the waiting time and the instruction selection range by several simple judgment logics according to the current real-time instruction emission condition and the pipeline load execution condition, and can realize the instruction scheduling in a short time by using as few hardware resources as possible, and complete the load balance in the asymmetric pipeline.

The invention belongs to the field of aircraft flight control system design, and particularly relates to a double-trim switch instruction selection method and system, and the method comprises the steps: obtaining the direction relation of two trim switch signals according to the collected pilot and copilot trim switch signals, and judging the validity of two trim switch instructions; and selecting the trimming switch instructions according to the validity and the sequence of the two trimming switch instructions. According to the technical scheme, multiple states of the trim switches are considered, effectiveness judgment and instruction selection logic of the two trim switch signals are designed, the trim use requirement of an aircraft can be met, the situation of non-instruction trim caused by switch faults is avoided, and the safety of flight control is improved.

The invention relates to a method for realizing an LD (Load) assembly instruction of a special processor chip based on an LLVM (Load-Load) rear end, and aims at a special architecture of an LD instruction in an instruction set of the special processor chip, a set of complete mapping mechanism from an intermediate representation to a target machine instruction is constructed by newly establishing a rear end processing flow of an LLVM compiling framework, and the LD (Load) assembly instruction of the special processor chip is obtained. And conversion from a high-level language to a chip special assembly instruction is realized. In the legalization stage of the rear end of the LLVM, unified architecture adaptation processing is carried out on global address access and a vector / scalar loading mode through a user-defined ISelLowing mechanism and instruction selection. According to the method, the intermediate language representation is converted into the target machine instruction for the special processor chip by utilizing the LLVM rear end, and according to the method, a developer can directly realize algorithm logic in a high-level language stage without manually writing a bottom assembly code, so that the development complexity is reduced, and the portability and maintainability of the code are improved.

The invention discloses a hybrid instruction set architecture-oriented instruction selection optimization method. The method comprises the following steps of: obtaining an IR tree of a source application program; traversing the IR tree, and recording the minimum cost of a sub-tree taking each node as a root in a node cost table (costTable); the IR tree is traversed, and an instruction value of each node is recorded in an instruction table; traversing the IR tree, matching each node with a pattern of a target platform instruction, and updating the minimum cost and instruction value corresponding to each node in a node cost table (costTable) and an instruction table (instructionTable) according to a matching result; and traversing the IR tree, generating a target code according to the updated instruction value of each node in the instruction table, and obtaining a target platform instruction of the source application program. According to the method, the global optimal code is generated by locally selecting the optimal instruction combination.

The invention provides a task execution method, device and system based on a plurality of container arrangement clusters, and relates to the computer technology, the method comprises the following steps: obtaining a plurality of task execution requests; each task execution request comprises a mirror image file, indication information and a to-be-run instruction; classifying the to-be-run instruction based on the mirror image file and the indication information; selecting a to-be-run instruction of a target category, and selecting a target container arrangement cluster and a target working node for the to-be-run instruction of the target category; sending a mirror image file and indication information corresponding to the to-be-run instruction of the target category to a target container arrangement cluster, so that the target container arrangement cluster creates a target execution unit on a target working node based on the mirror image file and the indication information; and injecting the to-be-run instruction of the target category into the execution unit to enable the execution unit to run the to-be-run instruction of the category. Therefore, the task execution performance of the task execution system is improved, and the task execution efficiency and reliability are improved.

The application discloses a method for dynamically adjusting a gene sequencing imaging process. The method comprises the following steps: obtaining a target technical route at a technical route interface; the computer system stores a plurality of technical routes, a corresponding process flow of each technical route, and processing steps of the process flow; and target instruction selection is performed by displaying technical route options, process flow options, and processing step options on a first interface of a man-machine interaction interface. The method for dynamically adjusting the gene sequencing imaging process based on the computer system can flexibly select a complete experimental process flow according to experimental parameters and equipment conditions, reduces new function development caused by different process flows, avoids data deviation and quality problems caused by experimental errors and operation negligence, saves manpower, time and cost, and improves the reliability and efficiency of experiments.

The invention discloses a register-sensitive instruction selecting and sorting method based on tree pattern matching, which is used for performing expression tree construction and optimization on instructions in a control flow diagram, and selecting and sorting the instructions in combination with a Sethi-Ullman algorithm and an iburg instruction selector. According to the method, the expression tree of the instruction is merged and optimized, so that the pressure of a register is reduced, the instruction selection and sorting efficiency is improved, and the execution performance of a program is optimized. Compared with the prior art, the method has the advantages that register resources can be utilized more effectively, register conflicts in the instruction selection and sorting process are reduced, and the execution efficiency and performance of a program are improved.

The invention relates to an RPA process design system based on a VS Code plug-in, and belongs to the technical field of process automation. The system comprises a text editing module, a graphical parameter configuration module, a project management module and an execution adaptation module. The text editing module loads a preset instruction library and a method signature library, receives the structured instruction, performs format verification and parameter completion, and analyzes to generate a memory instruction sequence list; the graphical parameter configuration module monitors an instruction selection state, generates a parameter form, performs validity verification on input parameters, generates instruction-parameter data and stores the instruction-parameter data in a to-be-processed data pool; the project management module generates a standard directory structure and performs version control and conflict detection; and the execution adaptation module extracts the data, converts the data into executable scripts and verifies the executable scripts. According to the system, the design, management and execution of the RPA process can be efficiently realized, and the convenience and accuracy of the automatic design of the robot process are improved.

The application discloses a kind of compiling implementation method and device for ARM processor supporting POSIT floating point format, the method includes: in compiling front end, the extension of POSIT type is carried out to lexical and syntax analysis, semantic analysis extension and intermediate representation generation extension, lexical and syntax analysis extension includes the keyword of newly added POSIT type, semantic analysis extension includes the semantic checking rule of increasing for POSIT type, intermediate representation generation extension includes the corresponding LLVM IR instruction of generating for the various operation operations of POSIT type;In compiling middle end, the IR type system extension of POSIT type is carried out, IR instruction set extension and optimization channel extension;In compiling back end, instruction selection and mapping, register allocation and call convention and instruction scheduling and emission are configured for POSIT type.The application can significantly improve the comprehensiveness, usability and compiler performance of compiling.

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

The present invention relates to a dual-start control method and system for a generator set. The steps of the control method include: the first control system receives an input signal; the first control system outputs an instruction to the second control system according to the input signal; the second control system selects a start mode according to the instruction for starting the first start group and / or the second start group; at least one set of data signals is fed back from the first start group and / or the second start group to the second control system, and the second control system exchanges signals with the first control system according to the data signals to determine whether the first start group and / or the second start group is started. The present invention can configure multiple sets of starting devices for the engine set, automatically switch different start modes, and then detect the start group and judge its opening and closing state, ensure that each start group starts smoothly after receiving the start instruction, so as to achieve the purpose of power supply and reduce the losses caused to customers due to inability to start.

The present invention discloses a programmable instruction distribution system, belonging to the technical field of general-purpose graphics processing units. The technical problem to be solved by the present invention is that there are a large number of invalid operations in the GPGPU instruction pipeline when processing branch instruction segments and loop instruction segments, occupying multiple clock cycles and reducing the execution efficiency and parallel performance of the GPGPU. The technical solution is as follows: The system includes an instruction splitting unit and an instruction replay unit; the instruction splitting unit is used to split a complete instruction segment into multiple sub-instruction segments to complete the fast distribution of specific instruction segments; the instruction splitting unit includes an instruction selection switch and a programmable instruction queue; wherein, the instruction selection switch is used to generate corresponding branch instruction segments from the programmable instruction queue according to an instruction mask and distribute the branch instructions; the instruction replay unit is used to record the distributed instruction segments and controllably replay the corresponding instruction segments; the instruction replay unit includes a register redirection logic, an instruction counter, and an instruction recording queue.

The invention provides a memory management method and a memory controller. The method includes: generating, via a processor, an access task including physical address information; setting the access task information to an instruction integration module; the instruction integration module generates a target access instruction for starting or not starting a cache mode according to the access task information; generating a next access task in parallel during instruction generation; and executing the target access instruction to implement the access task. According to the method, the instruction selection logic is packaged into the hardware interface and parallel processing is realized, so that the firmware processing time is shortened, and the read-write performance of the storage equipment is improved.

This invention discloses an automatic generation method for instruction matching templates based on LLVM intermediate representation, relating to the field of computer technology. It includes the following steps: Step 1, obtaining and parsing the LLVM IR instruction description file to generate a directed acyclic graph (DAG) of instruction operation behavior; Step 2, performing instruction behavior legalization processing on the DAG, analyzing types and operations incompatible with the target architecture in the DAG, and replacing them with operation sequences supported by the target architecture. This invention automatically generates instruction selection rules matching the target machine instruction set by analyzing the function semantic features, operand dependencies, and target architecture instruction set constraints of LLVM IR. These rules are used in the code generation stage of the LLVM compiler backend, solving the problems of low development efficiency, poor cross-hardware platform adaptability, and compiler code performance degradation caused by manual coding errors in existing technologies that involve manually writing instruction matching templates.