23 results about "Instruction selection" patented technology

To provide a business information processing system that enables users to efficiently carry out business in a situation where a plurality of business systems exist within an organization. [Solution] The business information processing system includes a language model 11 that has been machine-learned to output a response when an output instruction is input in natural language, multiple business support systems 13, and an API 14 that is an interface to the business support systems. When an output instruction or an output request is input to the language model 11, the language model 11 selects the API 14 required for the output instruction or output in accordance with the output instruction, and sends a request to the API 14.

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

The application relates to an RPA process design system based on a VS Code plug-in and belongs to the technical field of process automation. The system comprises a text editing module, a graphical parameter configuration module, an engineering management module and an execution adaptation module. The text editing module loads preset instruction libraries and method signature libraries, receives structured instructions, performs format checking and parameter completion, analyzes and generates a memory instruction sequence list; the graphical parameter configuration module listens to the instruction selection state, generates a parameter form, verifies the validity of input parameters, generates instruction-parameter data and stores the data into a to-be-processed data pool; the engineering management module generates a standard directory structure, performs version control and conflict detection; and the execution adaptation module extracts data and converts the data into an executable script and performs verification. The system can efficiently realize the design, management and execution of an RPA process, and improves the convenience and accuracy of robot process automation design.

1. The name of the design product: graphical user interface of instruction issuing function operation of electronic equipment. 2. The use of the design product: an electronic device. 3. The design points of the design product: in the graphical user interface. 4. The picture or photo that best shows the design points: design 1 interface change state diagram 2. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: for the operation of the instruction issuing function of the vehicle intelligent networked platform. 7. The human-computer interaction mode of the graphical user interface: the user touches the "instruction issuing" button of design 1 front view, enters design 1 interface change state diagram 1, the user touches and checks the target vehicle in the vehicle list, enters design 1 interface change state diagram 2, the user touches the drop-down icon of the instruction selection module, enters design 1 interface change state diagram 3, the user touches the selected target instruction selection, enters design 1 interface change state diagram 4, the user touches the drop-down icon of the instruction type module, enters design 1 interface change state diagram 5, the user touches the selected target instruction type, enters design 1 interface change state diagram 6, the user touches the drop-down icon of the instruction name module, enters design 1 interface change state diagram 7, the user touches the selected target instruction name, enters design 1 interface change state diagram 8, the user touches the "start execution" button, enters design 1 interface change state diagram 9. The user touches the "instruction issuing" button of design 2 front view, enters design 2 interface change state diagram 1, the user touches and checks the target vehicle in the vehicle list, enters design 2 interface change state diagram 2, the user touches the drop-down icon of the instruction selection module, enters design 2 interface change state diagram 3, the user touches the selected target instruction selection, enters design 2 interface change state diagram 4, the user touches the drop-down icon of the instruction type module, enters design 2 interface change state diagram 5, the user touches the selected target instruction type, enters design 2 interface change state diagram 6, the user can set the target parameter value in the instruction parameter module, the user touches the drop-down icon of the instruction name module, enters design 2 interface change state diagram 7, the user touches the selected target instruction name, enters design 2 interface change state diagram 8, the user touches the "start execution" button, enters design 2 interface change state diagram 9. 8. Other circumstances that need to be explained: the text and / or numbers in each view interface can be replaced, and the number of characters does not constitute a limitation on the replacement characters.

The application discloses a load switching circuit, a load switching method and a household device, wherein a receiving module, a control module, a resistive load module and an inductive load module are included. The receiving module acquires an instruction signal; the receiving module sends the instruction signal to the control module; the control module determines a load module corresponding to the instruction signal according to the instruction signal, selectively controls the resistive load module or the inductive load module to work, receives a control signal transmitted by the control module through the receiving module, and transmits the control signal to the resistive load module and the inductive load module; according to specific instructions of the control signal, it is determined whether the resistive load module or the inductive load module works, different load type modules work according to user requirements, and the problem that different loads require different topological circuit requirements is overcome.

The application provides a pipeline instruction distribution method, comprising the following steps: calculating the load time of each pipeline, and sorting the pipelines according to the load time, and setting the pipeline priority according to the sorting result; calculating the waiting time of each instruction, and sorting the instructions according to the waiting time, and setting the instruction priority according to the sorting result; and distributing the instructions to the corresponding pipelines according to the instruction priority and the pipeline priority. The pipeline instruction distribution method provided by the application can realize the dynamic balance of the waiting time and the instruction selection range by several simple judgment logics according to the current real-time instruction emission condition and the pipeline load execution condition, and can realize the instruction scheduling in a short time by using as few hardware resources as possible, and complete the load balance in the asymmetric pipeline.

The invention belongs to the field of aircraft flight control system design, and particularly relates to a double-trim switch instruction selection method and system, and the method comprises the steps: obtaining the direction relation of two trim switch signals according to the collected pilot and copilot trim switch signals, and judging the validity of two trim switch instructions; and selecting the trimming switch instructions according to the validity and the sequence of the two trimming switch instructions. According to the technical scheme, multiple states of the trim switches are considered, effectiveness judgment and instruction selection logic of the two trim switch signals are designed, the trim use requirement of an aircraft can be met, the situation of non-instruction trim caused by switch faults is avoided, and the safety of flight control is improved.

The invention relates to a method for realizing an LD (Load) assembly instruction of a special processor chip based on an LLVM (Load-Load) rear end, and aims at a special architecture of an LD instruction in an instruction set of the special processor chip, a set of complete mapping mechanism from an intermediate representation to a target machine instruction is constructed by newly establishing a rear end processing flow of an LLVM compiling framework, and the LD (Load) assembly instruction of the special processor chip is obtained. And conversion from a high-level language to a chip special assembly instruction is realized. In the legalization stage of the rear end of the LLVM, unified architecture adaptation processing is carried out on global address access and a vector / scalar loading mode through a user-defined ISelLowing mechanism and instruction selection. According to the method, the intermediate language representation is converted into the target machine instruction for the special processor chip by utilizing the LLVM rear end, and according to the method, a developer can directly realize algorithm logic in a high-level language stage without manually writing a bottom assembly code, so that the development complexity is reduced, and the portability and maintainability of the code are improved.

The application discloses a method for dynamically adjusting a gene sequencing imaging process. The method comprises the following steps: obtaining a target technical route at a technical route interface; the computer system stores a plurality of technical routes, a corresponding process flow of each technical route, and processing steps of the process flow; and target instruction selection is performed by displaying technical route options, process flow options, and processing step options on a first interface of a man-machine interaction interface. The method for dynamically adjusting the gene sequencing imaging process based on the computer system can flexibly select a complete experimental process flow according to experimental parameters and equipment conditions, reduces new function development caused by different process flows, avoids data deviation and quality problems caused by experimental errors and operation negligence, saves manpower, time and cost, and improves the reliability and efficiency of experiments.

The invention discloses a register-sensitive instruction selecting and sorting method based on tree pattern matching, which is used for performing expression tree construction and optimization on instructions in a control flow diagram, and selecting and sorting the instructions in combination with a Sethi-Ullman algorithm and an iburg instruction selector. According to the method, the expression tree of the instruction is merged and optimized, so that the pressure of a register is reduced, the instruction selection and sorting efficiency is improved, and the execution performance of a program is optimized. Compared with the prior art, the method has the advantages that register resources can be utilized more effectively, register conflicts in the instruction selection and sorting process are reduced, and the execution efficiency and performance of a program are improved.

The invention relates to an RPA process design system based on a VS Code plug-in, and belongs to the technical field of process automation. The system comprises a text editing module, a graphical parameter configuration module, a project management module and an execution adaptation module. The text editing module loads a preset instruction library and a method signature library, receives the structured instruction, performs format verification and parameter completion, and analyzes to generate a memory instruction sequence list; the graphical parameter configuration module monitors an instruction selection state, generates a parameter form, performs validity verification on input parameters, generates instruction-parameter data and stores the instruction-parameter data in a to-be-processed data pool; the project management module generates a standard directory structure and performs version control and conflict detection; and the execution adaptation module extracts the data, converts the data into executable scripts and verifies the executable scripts. According to the system, the design, management and execution of the RPA process can be efficiently realized, and the convenience and accuracy of the automatic design of the robot process are improved.

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

This invention discloses an automatic generation method for instruction matching templates based on LLVM intermediate representation, relating to the field of computer technology. It includes the following steps: Step 1, obtaining and parsing the LLVM IR instruction description file to generate a directed acyclic graph (DAG) of instruction operation behavior; Step 2, performing instruction behavior legalization processing on the DAG, analyzing types and operations incompatible with the target architecture in the DAG, and replacing them with operation sequences supported by the target architecture. This invention automatically generates instruction selection rules matching the target machine instruction set by analyzing the function semantic features, operand dependencies, and target architecture instruction set constraints of LLVM IR. These rules are used in the code generation stage of the LLVM compiler backend, solving the problems of low development efficiency, poor cross-hardware platform adaptability, and compiler code performance degradation caused by manual coding errors in existing technologies that involve manually writing instruction matching templates.

This invention discloses a gas turbine control system and verification method with a dual-controller parallel collaborative architecture, comprising: introducing a programmable logic controller (PLC) as an auxiliary control device into the system. The original gas turbine controller is still responsible for implementing the gas turbine's start-up, sequential control, main control, and protection control functions. The PLC, which operates in parallel and collaboratively with the original gas turbine controller, supports the input of third-party control algorithms. An instruction selection module is used to determine the actual input speed controller calculation instruction signal to the gas turbine; a minimum value selector is used to filter the actual input fuel flow signal to the gas turbine; the gas turbine body simulation model and data analysis module are both used to determine changes in the gas turbine's operating performance and to realize online parameter adjustment of the third-party control algorithm in the PLC. The data acquisition module is mainly used to acquire the gas turbine's state parameter signals. This invention solves the problems of high risk and difficulty in implementation of full-physical testing in the current development of gas turbine control algorithms.

A multi-thread processor can include logic that can be implemented in a form of physical logic gates, a plurality of hardware threads, one or more execution units that can execute one or more instructions, a least a level 1 cache that can be for data, and selection logic. Each hardware thread of the plurality of hardware threads can fetch instructions from a software thread of execution assigned to a corresponding hardware thread of the plurality of hardware threads. The selection logic can include one or more fair ready-schedulers. Each fair ready-scheduler of the one or more fair ready-schedulers can select instructions that are ready for execution from among the plurality of hardware threads. A distribution of which a hardware thread is chosen can be consistent with a pattern expected from choosing a ready instruction according to a uniform probability distribution.

The invention discloses a compiler rear-end instruction selection method for an AI chip in-memory computing acceleration unit, and belongs to the technical field of compilers. Aiming at the requirement that the in-memory computing architecture breaks through the computing power and energy efficiency bottleneck, the key technical problems of an in-memory computing acceleration unit in the aspects of scalar instruction matching, mapping of a special instruction and an LLVM built-in function, skipping instruction label offset and hardware constraint matching and the like are mainly solved by relying on LLVM unified intermediate representation (IR) and a modular Pass optimization architecture. Through customized instruction format definition, exclusive Intrinsic mapping and skipping relative offset processing, LLVM IR is generated through front-end analysis of a C code, after instruction conversion optimization, accurate adaptation of an instruction is completed by a customized rear end, and finally a target assembly code is generated. According to the method, the adaptability to the target architecture is ensured, the data scheduling and operation cooperation capability of the acceleration unit is improved, and key support is provided for high-performance deployment of the AI chip.

A method, apparatus and product are provided for using classical control flow in quantum programming. A quantum program that comprises a sequence of instructions including compilable instructions and a non-compilable instruction is received. A first subset of the compilable instructions is selected based on the non-compilable instruction. The first subset is compiled to obtain a first quantum circuit, which is executed using a quantum execution platform. An outcome of the execution is determined. A second subset of the compilable instructions, different from the first subset, is selected. The second subset is compiled to obtain a second quantum circuit executable by the quantum execution platform. In another aspect, compilable instructions are selected based on the type and position of a non-compilable instruction. The selected instructions are compiled to obtain an executable quantum circuit.

A processing unit leverages a decode stage's pool of instructions, thereby expanding available instruction choices and eliminating the need for expensive OoO techniques to identify reordering opportunities. The processing unit introduces instruction reordering by presenting an alternative instruction to the warp scheduler through the existing interface rather than offering the oldest instruction in each warp. The result is a simple and efficient OoO engine that operates predominantly in the processing unit's front end.

In situations where multiple business systems exist within an organization, this system provides a business information processing system that enables users to efficiently perform their tasks. [Solution] The business information processing system comprises a language model 11 trained to output responses when output instructions are input in natural language, a plurality of business support systems 13, and an API 14 which is an interface to the business support systems. When an output instruction or output request is input to the language model 11, the language model 11 selects the API 14 necessary for the output instruction or the output according to the output instruction and sends a request to the API 14.

The present application relates to embedded application, specifically relates to the compiler optimization method for embedded application based on digital signal processor, register configuration C code is translated into OR instruction and AND instruction of intermediate expression IR, through instruction selection processing to OR instruction and AND instruction to BST instruction and BCLR instruction specific to digital signal processor, reach optimization purpose, the C code of cycle, judgment, call, return is translated into these jump instruction of JMP, JN, JNC, CALL, RET, through instruction replacement to the delay slot NOP after the jump instruction of digital signal processor, reach optimization purpose, the technical scheme provided by the present application can effectively overcome the defects of the prior art, such as the need for multiple instructions to implement bit assignment and low code execution efficiency.

A parameterization instruction selection method, applied to optimizing a compilation process executed by a compiler. In the parameterization instruction selection method, during compiling, corresponding machine instruction sets are pre-generated for instructions in a code to be compiled, and one or more corresponding machine instructions that can be selected by each instruction in the code during compiling are indicated on the basis of the machine instruction sets, so that a compiler does not select a default machine instruction for the instruction in the code any more, and the compiler is guided to select different machine instruction combinations during compiling, so as to obtain a plurality of different target files; finally, a target file having optimal execution performance is selected by executing the plurality of target files. Thus, the flexibility of an instruction selection process is improved, and the target file having higher execution performance is obtained by means of compiling.

In situations where multiple business systems exist within an organization, this system provides a business information processing system that enables users to efficiently perform their tasks. [Solution] The business information processing system comprises a language model 11 trained to output responses when output instructions are input in natural language, a plurality of business support systems 13, and an API 14 which is an interface to the business support systems. When an output instruction or output request is input to the language model 11, the language model 11 selects the API 14 necessary for the output instruction or the output according to the output instruction and sends a request to the API 14.

The invention provides a communication control method and device, equipment and a storage medium. Relates to the technical field of computers. The method comprises: receiving a function control instruction, the function control instruction being used for controlling an embedded subscriber identity module eSIM function of a terminal device, the function control instruction being any one of the following instructions: a first activation instruction, a selection instruction and a first closing instruction, the selection instruction being used for controlling the terminal device to activate or close the eSIM function through a user instruction; according to the function control instruction, a first function field is updated, and the first function field is used for determining whether an eSIM function is activated or not; and according to the first function field, updating the system attribute and the driving node to obtain an eSIM function state, the eSIM function state including an on state and an off state. According to the method provided by the invention, the flexibility of switching the eSIM function is improved.