11 results about "Instruction selection" patented technology

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

The application relates to an RPA process design system based on a VS Code plug-in and belongs to the technical field of process automation. The system comprises a text editing module, a graphical parameter configuration module, an engineering management module and an execution adaptation module. The text editing module loads preset instruction libraries and method signature libraries, receives structured instructions, performs format checking and parameter completion, analyzes and generates a memory instruction sequence list; the graphical parameter configuration module listens to the instruction selection state, generates a parameter form, verifies the validity of input parameters, generates instruction-parameter data and stores the data into a to-be-processed data pool; the engineering management module generates a standard directory structure, performs version control and conflict detection; and the execution adaptation module extracts data and converts the data into an executable script and performs verification. The system can efficiently realize the design, management and execution of an RPA process, and improves the convenience and accuracy of robot process automation design.

The invention relates to a method for realizing an LD (Load) assembly instruction of a special processor chip based on an LLVM (Load-Load) rear end, and aims at a special architecture of an LD instruction in an instruction set of the special processor chip, a set of complete mapping mechanism from an intermediate representation to a target machine instruction is constructed by newly establishing a rear end processing flow of an LLVM compiling framework, and the LD (Load) assembly instruction of the special processor chip is obtained. And conversion from a high-level language to a chip special assembly instruction is realized. In the legalization stage of the rear end of the LLVM, unified architecture adaptation processing is carried out on global address access and a vector / scalar loading mode through a user-defined ISelLowing mechanism and instruction selection. According to the method, the intermediate language representation is converted into the target machine instruction for the special processor chip by utilizing the LLVM rear end, and according to the method, a developer can directly realize algorithm logic in a high-level language stage without manually writing a bottom assembly code, so that the development complexity is reduced, and the portability and maintainability of the code are improved.

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

This invention discloses an automatic generation method for instruction matching templates based on LLVM intermediate representation, relating to the field of computer technology. It includes the following steps: Step 1, obtaining and parsing the LLVM IR instruction description file to generate a directed acyclic graph (DAG) of instruction operation behavior; Step 2, performing instruction behavior legalization processing on the DAG, analyzing types and operations incompatible with the target architecture in the DAG, and replacing them with operation sequences supported by the target architecture. This invention automatically generates instruction selection rules matching the target machine instruction set by analyzing the function semantic features, operand dependencies, and target architecture instruction set constraints of LLVM IR. These rules are used in the code generation stage of the LLVM compiler backend, solving the problems of low development efficiency, poor cross-hardware platform adaptability, and compiler code performance degradation caused by manual coding errors in existing technologies that involve manually writing instruction matching templates.

A multi-thread processor can include logic that can be implemented in a form of physical logic gates, a plurality of hardware threads, one or more execution units that can execute one or more instructions, a least a level 1 cache that can be for data, and selection logic. Each hardware thread of the plurality of hardware threads can fetch instructions from a software thread of execution assigned to a corresponding hardware thread of the plurality of hardware threads. The selection logic can include one or more fair ready-schedulers. Each fair ready-scheduler of the one or more fair ready-schedulers can select instructions that are ready for execution from among the plurality of hardware threads. A distribution of which a hardware thread is chosen can be consistent with a pattern expected from choosing a ready instruction according to a uniform probability distribution.

The invention discloses a compiler rear-end instruction selection method for an AI chip in-memory computing acceleration unit, and belongs to the technical field of compilers. Aiming at the requirement that the in-memory computing architecture breaks through the computing power and energy efficiency bottleneck, the key technical problems of an in-memory computing acceleration unit in the aspects of scalar instruction matching, mapping of a special instruction and an LLVM built-in function, skipping instruction label offset and hardware constraint matching and the like are mainly solved by relying on LLVM unified intermediate representation (IR) and a modular Pass optimization architecture. Through customized instruction format definition, exclusive Intrinsic mapping and skipping relative offset processing, LLVM IR is generated through front-end analysis of a C code, after instruction conversion optimization, accurate adaptation of an instruction is completed by a customized rear end, and finally a target assembly code is generated. According to the method, the adaptability to the target architecture is ensured, the data scheduling and operation cooperation capability of the acceleration unit is improved, and key support is provided for high-performance deployment of the AI chip.

A method, apparatus and product are provided for using classical control flow in quantum programming. A quantum program that comprises a sequence of instructions including compilable instructions and a non-compilable instruction is received. A first subset of the compilable instructions is selected based on the non-compilable instruction. The first subset is compiled to obtain a first quantum circuit, which is executed using a quantum execution platform. An outcome of the execution is determined. A second subset of the compilable instructions, different from the first subset, is selected. The second subset is compiled to obtain a second quantum circuit executable by the quantum execution platform. In another aspect, compilable instructions are selected based on the type and position of a non-compilable instruction. The selected instructions are compiled to obtain an executable quantum circuit.

In situations where multiple business systems exist within an organization, this system provides a business information processing system that enables users to efficiently perform their tasks. [Solution] The business information processing system comprises a language model 11 trained to output responses when output instructions are input in natural language, a plurality of business support systems 13, and an API 14 which is an interface to the business support systems. When an output instruction or output request is input to the language model 11, the language model 11 selects the API 14 necessary for the output instruction or the output according to the output instruction and sends a request to the API 14.

The present application relates to embedded application, specifically relates to the compiler optimization method for embedded application based on digital signal processor, register configuration C code is translated into OR instruction and AND instruction of intermediate expression IR, through instruction selection processing to OR instruction and AND instruction to BST instruction and BCLR instruction specific to digital signal processor, reach optimization purpose, the C code of cycle, judgment, call, return is translated into these jump instruction of JMP, JN, JNC, CALL, RET, through instruction replacement to the delay slot NOP after the jump instruction of digital signal processor, reach optimization purpose, the technical scheme provided by the present application can effectively overcome the defects of the prior art, such as the need for multiple instructions to implement bit assignment and low code execution efficiency.

In situations where multiple business systems exist within an organization, this system provides a business information processing system that enables users to efficiently perform their tasks. [Solution] The business information processing system comprises a language model 11 trained to output responses when output instructions are input in natural language, a plurality of business support systems 13, and an API 14 which is an interface to the business support systems. When an output instruction or output request is input to the language model 11, the language model 11 selects the API 14 necessary for the output instruction or the output according to the output instruction and sends a request to the API 14.