2 results about "Instruction selection" patented technology

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

This invention discloses an automatic generation method for instruction matching templates based on LLVM intermediate representation, relating to the field of computer technology. It includes the following steps: Step 1, obtaining and parsing the LLVM IR instruction description file to generate a directed acyclic graph (DAG) of instruction operation behavior; Step 2, performing instruction behavior legalization processing on the DAG, analyzing types and operations incompatible with the target architecture in the DAG, and replacing them with operation sequences supported by the target architecture. This invention automatically generates instruction selection rules matching the target machine instruction set by analyzing the function semantic features, operand dependencies, and target architecture instruction set constraints of LLVM IR. These rules are used in the code generation stage of the LLVM compiler backend, solving the problems of low development efficiency, poor cross-hardware platform adaptability, and compiler code performance degradation caused by manual coding errors in existing technologies that involve manually writing instruction matching templates.