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Multi-granularity parallel FFT (Fast Fourier Transform) computing device

A computing device, multi-granularity technology, applied in complex mathematical operations and other directions, can solve problems such as difficulty in implementing parallel FFT algorithms, complex reading and writing address calculations, etc., to reduce chip power consumption and reduce access times.

Active Publication Date: 2012-04-11
BEIJING SMART LOGIC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this patent requires a dedicated memory, data buffer and selector, and the calculation of read and write addresses is complex, making it difficult to implement parallel FFT algorithms with different data lengths and different read and write granularities.

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  • Multi-granularity parallel FFT (Fast Fourier Transform) computing device

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Embodiment Construction

[0035] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0036] In this specification, for the convenience of description, we first introduce the overall structure of the multi-granularity parallel FFT calculation device of the present invention, and then describe each component included therein.

[0037] Multi-granularity parallel FFT computing device

[0038] Figure 4 It is a structural diagram of a specific embodiment of the multi-granularity parallel FFT computing device of the present invention, which includes three multi-granularity parallel memories, a butterfly computing device 404, a state control unit 405, a data reverse network 406 and a first selector 407 . Here, the three multi-granularity parallel memories are respectively referred to as the first memory 401 , th...

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Abstract

The invention discloses a multi-granularity parallel FFT (Fast Fourier Transform) computing device which comprises three memorizers, a butterfly computation device, a state control unit, a data inverted sequence network and a first selector, wherein the three memorizers are multi-granularity parallel memorizers and used for storing butterfly group data and rotation factors corresponding to the butterfly group data, and the butterfly computation device is used for completing the computation of one butterfly group according to the butterfly group data output from the first selector and the rotation factors corresponding to the butterfly group data and being output from one memorizer and writing a computation result to other two memorizers. By using specific read-write granularity, the multi-granularity parallel FFT computing device can be used for reading the butterfly group data and the rotation factors corresponding to the butterfly group data in parallel from the multi-granularity parallel memorizers without generating memorizer conflict and needing additional steps for sequencing read-write data.

Description

technical field [0001] The invention relates to parallel storage, parallel reading and writing and parallel calculation of fast Fourier transform (FFT) data in the field of integrated circuit design. Background technique [0002] Signal processing systems often need to convert signal content in the time domain and frequency domain, and the Fast Fourier Transform algorithm (FFT) can perform signal conversion between the time domain and the frequency domain. Compared with other conversion algorithms, the fast Fourier transform algorithm has the advantages of uniform structure and less calculation, so it is widely used in signal processing systems. [0003] The FFT algorithm inputs N data and outputs N data; it is generally called the forward transform from the time domain to the frequency domain, and the inverse transform from the frequency domain to the time domain. There are many ways to implement the FFT algorithm, but they are all evolved from the Cooley-Tukey algorithm. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 王东琳谢少林蒿杰林啸汪涛尹磊祖
Owner BEIJING SMART LOGIC TECH CO LTD
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