Method for managing reconfigurable on-chip unified memory aiming at instructions

Abstract

The invention discloses a method for implementing managing a reconfigurable on-chip unified memory aiming at instructions by utilizing a virtual memory mechanism. Through the method, the parameters of the Cache part and the SPM (Scratch-PadMemory) part in the reconfigurable unified memory can be dynamically adjusted in the program running process to adapt to the requirements for memory architecture in different program execution stages. The method is characterized by analyzing the memory access behaviors in different program running stages, obtaining phase change behavior diagrams of the instruction parts and carrying out mathematical abstraction on the phase change behavior diagrams, obtaining the reconfigurable memory configuration information in each program stage and selecting the program instruction parts needing to be optimized by adopting integer nonlinear programming (INLP) according to the energy consumption objective function and the performance objective function and mapping the code segments which have severe conflicts and are frequently accessed in the Cache into the SPM part as much as possible by virtue of a virtual memory management mechanism, thus not only reducing the external memory access energy consumption caused by repeatedly filling Cache, reducing the extra energy consumption caused by compare logic in the Cache and improving the system performance.

Description

technical field [0001] The invention relates to a reconfigurable on-chip unified memory, in particular to a dynamic management of the reconfigurable on-chip unified memory by using a virtual memory mechanism, and specifically provides a circuit and a dynamic management method of the memory. Background technique [0002] With the development of microelectronics technology, the embedded computing platform based on SoC (System-on-a-Chip) is becoming more and more mature. However, due to the increasing gap between processor speed and external memory speed, the SoC memory subsystem has become the bottleneck of system performance, power consumption and cost. Therefore, how to optimize the architecture and management strategy of the storage subsystem has always been a hot spot in embedded research. [0003] Cache and SPM (Scratch-Pad Memory) are the most common traditional on-chip memories. Cache is managed by hardware, transparent to software in most cases, and can automatically...

AI Technical Summary

Problems solved by technology

However, the shortcomings of Cache, such as high power consumption, large footprint, and unpredictable program execution time, have always limited its wide application in embedded systems.

Most of the research on reconfigurable architecture is on reconfigurable Cache. During the running of the program, the parameters of the Ca

Images