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Device and method for implementing FFT and IFFT operation

An out-of-device, butterfly computing technology, which is applied in the field of communication technology and signal processing, can solve the problems of slow data processing speed and achieve the effect of improving the computing speed

Inactive Publication Date: 2011-04-27
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The application of the above-mentioned rake receivers requires processing a large amount of data. If all data processing is completed in the time domain, the amount of data processed by the hardware will be very large, and the amount of data processed by the hardware in the frequency domain is relatively large. It should be small, so the processed data is converted from the time domain to the frequency domain, taking into account the full utilization of the computing speed and hardware resources. In the prior art, the FFT / IFFT processing devices all serially process multiple data, so that resulting in slow data processing

Method used

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  • Device and method for implementing FFT and IFFT operation
  • Device and method for implementing FFT and IFFT operation
  • Device and method for implementing FFT and IFFT operation

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Embodiment Construction

[0026] An embodiment of the present invention provides a device for realizing FFT and IFFT calculations, including: an FFT / IFFT control unit, which is used to input two channels of data to be calculated and twiddle factors into the ALU calculation unit, and store the ALU output calculation results in the corresponding In the RAM, and use the state machine to control the switching of each stage of the FFT / IFFT butterfly operation; the ALU operation unit is used to perform the FFT / IFFT butterfly operation on the two channels of data to be operated; the RAM read / write control unit is used for the The plurality of RAMs perform read and write control, wherein the plurality of RAMs store the results of each stage of FFT / IFFT butterfly operation of the ALU operation unit; the twiddle factor reading unit is used to calculate the results required for each stage of butterfly operation. The storage address of the twiddle factor in the twiddle factor storage unit.

[0027] The specific im...

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Abstract

The invention discloses a device and a method for implementing fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operation. The device comprises an FFT / IFFT control unit, an arithmetic logical unit (ALU) operation unit, a random access memory (RAM) read / write control unit and a rotation factor reading unit, wherein the FFT / IFFT control unit is used for inputting two paths of data and rotation factors to be operated into the ALU operation unit, storing the ALU output calculation results into corresponding RAMs respectively and controlling the switching of butterfly operation of each stage of FFT / IFFT by using a state machine; the ALU operation unit is used for performing FFT / IFFT butterfly operation on the two paths of data to be operated respectively; the RAM read / write control unit is used for performing read and write control on a plurality of RAMs, wherein the plurality of RAMs store the FFT / IFFT butterfly operation results of each stage; and the rotation factor reading unit is used for calculating the storage address of the rotation factor required for calculating the butterfly operation of each stage in a rotation factor storage unit. The device improves the speed of FFT and IFFT in the prior art.

Description

technical field [0001] The invention relates to the field of communication technology and signal processing, in particular to a device and method for realizing FFT and IFFT operations. Background technique [0002] The wireless channel in the real environment has two characteristics: time-varying characteristics and fading characteristics. Since the delay of each reflected wave of the wireless signal is different, the signal received at the UE end is actually a superposition of multipath signals. According to the characteristics of the scrambling code, the cross-correlation value of the two-path signals with a delay within one chip is not zero, and the asynchronous OVSF (Orthogonal Variable Spreading Factor) codes are not completely positive. Therefore, there is mutual interference between wireless signals on different paths. In HSDPA, because HS-PDSCH adopts multi-code transmission, the spreading factor is fixed and low, and the signal-to-noise ratio is high, so the inter-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 王经纬
Owner SANECHIPS TECH CO LTD
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