133 results about "Complex multiplier" patented technology

The invention provides a transmission device having adaptive digital predistortion, which has a transmission path and a feedback path. The transmission path contains a predistortion unit which takes a derived control signal (LS) and baseband signals applied to the input side as a basis for calculating the address of a predistortion coefficient (KOEFF1) stored in a memory and logically combines this predistortion coefficient with the applied baseband signals in a complex multiplication unit. The use of complex coefficients and of the complex multipliers allows compensation both for AM / AM distortion and for AM / PM distortion in an amplifier device connected downstream of the predistortion unit. Usefully, the feedback path of the transmission device with digital adaptive predistortion can also be implemented using the reception device in a transceiver.

The present invention discloses an optimal hardware implementation of the FFT / IFFT operation that minimizes the number of clock cycles required to compute the FFT / IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT / IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module. A map module is provided for receiving outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs. In a preferred embodiment, the N-point FFT / IFFT operation is performed in N clock cycles using(N32+1)complex multipliers. In a specific implementation, a system comprising 3 complex multipliers is used to compute a 64-point FFT / IFFT operation in 64 clock cycles. Advantageously, the total number of clock cycles required to complete the FFT / IFFT operation is minimized while at the same time minimizing the number of complex multipliers needed.

A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.

A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.

A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodiment, the design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the Fourier transform coefficient matrix and the radix-4 butterfly. The resulting design provides an array comprised of a plurality of smaller base-4 matrices that can simply be added or removed to provide scalability of the design for applications involving different transform lengths to be calculated. In this embodiment, the systolic array size provides greater flexibility because it can be applied for use with any transform length which is an integer multiple of sixteen.