6 results about "Complex multiplier" patented technology

The present application relates to a kind of multi-mode noise interference signal generation method, belong to signal interference technical field, solve the problem that existing cannot dynamically flexibly generate the interference signal of multiple modulation modes and the high development complexity.For method includes: according to noise kind and interference mode, obtain first noise sequence, second noise sequence, third noise sequence, noise interference bandwidth and center frequency;Carrier signal is generated based on center frequency;First noise sequence and noise interference bandwidth are passed into first multiplier, then the output result and carrier signal are passed into adder, and first complex signal is output by direct digital synthesizer;First complex signal and second noise sequence are passed into complex multiplier, and second complex signal is output;Second complex signal and third noise sequence are passed into second multiplier, and noise interference signal is output.The generation of multi-mode noise interference signal dynamically flexibly is realized.

The invention discloses a multiply-accumulate operation method and device, a neural network processing device and electronic equipment, and the method comprises the steps: encoding input activation data into encoding activation data, and encoding original weight data into a weight unit after encoding processing; a multiplication result can be obtained only by selecting a shift operation in the storage array, a complex multiplier circuit is replaced, and the calculation power consumption is remarkably reduced; the second intermediate result is obtained by carrying out shift accumulation on the first intermediate result, and accurate compensation is carried out by utilizing the compensation code based on calculation, so that the result correctness is ensured, the additional cycle overhead and the complex circuit generated by processing unsigned data or symbol extension in the traditional scheme are avoided, and the accuracy of the result is improved. Therefore, on the basis of improving the calculation throughput rate, the calculation power is effectively enhanced, the power consumption is optimized, and finally the energy efficiency ratio and the overall processing efficiency of the multiply-accumulate operation are comprehensively improved.

The invention provides a flow analysis system signal baseline estimation method and system, equipment and a medium, all calculations are carried out in an FPGA (Field Programmable Gate Array) in parallel and finished in an assembly line without software delay, and the method and the system can be directly used for triggering subsequent real-time signal processing or cell sorting decisions; through the triple mechanisms of hardware pre-filtering, extreme value elimination and recursive smoothing, various noises are effectively inhibited, and the baseline estimation variance is significantly reduced; an adder, a comparator and a register are mainly used in the algorithm, a complex multiplication divider or a large number of storage units are not needed, FPGA resource occupation is small, and power consumption is low. The provided stable and accurate double-baseline value can be used as the estimation input of a noise covariance matrix in a weighted least square (WLS) spectrum unmixing algorithm, and the unmixing precision and the signal-to-noise ratio of multicolor fluorescence analysis are directly improved; due to pure digital hardware implementation, the method can be easily transplanted to different types of flow cytometers or other optical particle analysis equipment.

This application discloses a multiply-accumulate operation method, apparatus, neural network processing apparatus, and electronic device. The multiply-accumulate operation method encodes input activation data into encoded activation data and original weight data into encoded weight units, enabling the multiplication result to be obtained in the memory array simply by selecting a shift operation, replacing complex multiplier circuits and significantly reducing computational power consumption. By shifting and accumulating the first intermediate result to obtain the second intermediate result, and using computation-based compensation codes for precise compensation, the correctness of the result is ensured while avoiding the additional cycle overhead and complex circuitry caused by processing unsigned data or sign extension in traditional schemes. This improves computational throughput while effectively enhancing computing power and optimizing power consumption, ultimately comprehensively improving the energy efficiency ratio and overall processing efficiency of the multiply-accumulate operation.

A system (1) for estimating a frequency of a complex input signal, wherein said system (1) comprises: - at least one frequency generator module (2) for generating a multi-frequency reference signal; - a single complex multiplier module (3) for multiplying in a time-sharing manner the reference signal with the input signal; - at least one coherent accumulate-and-dump filter (4) configured to accumulate an output signal of the a complex multiplier module (3); - at least one non-coherent accumulate-and-dump filter (5) configured to accumulate an output signal of the at least one coherent accumulate-and-dump filter (4); and - at least one max-finder module (6) configure to estimate a maximum value of an output signal of the at least one non-coherent accumulate-and-dump filter (5). The invention also relates to method estimating a frequency of a complex input signal by using components of said system (1).

The technical scheme of the invention discloses a deep optimization multiplier formal verification method based on a graph neural network and a reference library. According to the invention, a reference design which is most similar to the structure of the multiplier to be verified can be automatically selected from a large-scale reference library, and verification technologies such as SCA or SAT are adaptively selected so as to avoid invalid or high-cost verification attempts; and a high verification success rate and acceptable operation time can be still maintained under complex architectures such as Booth coding and the like and a deep optimization scene. According to the invention, the deep learning technology and the formal verification technology are innovatively combined, the high-level structure representation of the multiplier circuit is learned through the graph neural network, the internal association between the structural similarity and the verification difficulty is established, the intelligent selection of the verification method and the accurate matching of the reference circuit are realized, and the verification efficiency is improved. Therefore, the verification efficiency and success rate of the complex multiplier are remarkably improved.