227 results about "Negation" patented technology

The invention discloses a microblog sentiment analysis method based on large-scale corpus characteristic learning. The method is characterized in that microblog texts is used to train a neural network based on Word2Vec, the neural network completes training by inputting the microblog texts, the neural network maps the input microblog to a corresponding word vector according to grammar contents, emotional tendency of current contents, and whether words are denied or not, and a matrix formed by word vectors corresponding to the words in the microblog is obtained. Synthesis of word vectors is performed on the matrix, so as to further obtain a feature vector corresponding to the microblog. Through applying the feature vector to training and prediction of a sentiment classification device, a relatively accurate microblog sentiment analysis is obtained. Compared with the prior art, the method is low in cost and high in analysis accurate rate, and is especially suitable for large-scale corpus, and is fast in training speed. Combining with grammar contents and emotional tendency, the method effectively processes negation relations, and improves accurate rate of sentiment analysis.

The adaptive speed to changes in a primary source noise is increased through a noise detecting means feeding parallel multi-passband means and multi-transverse adaptive filter means, where each adaptive filter has its own individual adaptive step size means adjusted automatically according to the signal strength at each passband output. The output from each of the multi-adaptive filter means drives a secondary canceling source generating means where each multi-adaptive filter means is automatically adjusted to produce minimum sound in its passband at an error detecting means. Alternatively, the output from the noise detecting means is negated through a negation means, passed through a plant neutralization inverse means and an inverse delay means before driving the secondary source generating means. The secondary source output is aligned and match in amplitude to that of the primary sources, through a delay buffer means and an amplitude regulator means, which are adjusted successively until the output at the error detector means is a minimum.

A system and method for product configuration represents a product using a configuration model having numerical clauses. Features of the product are associated with literals in the numerical clauses. The numerical clauses may specify a number of literals to determine whether the numerical clause is satisfied, satisfiable, or unsatisfiable. Numerical clauses represent constraints that govern the configuration of the product. Resolving numerical clauses and user choices involves one or more inference procedures. In one embodiment, unit clauses represent user choices, and a configuration engine asserts the unit clause and performs numerical unit resolution between the unit clause and all numerical clauses containing the complement (generally a negation) of the unit clause. Complementary literals are eliminated from the current state of the configuration model. In one embodiment, if the uneliminated literals in a numerical clause causes the clause to be satisfied, the uneliminated literals are recursively asserted. The configuration engine then performs numerical unit resolution between the recursively asserted, uneliminated literals and numerical clauses containing the complements of the uneliminated literals. Numerical clauses may also function as literals. Numerical clauses may include negations of consumer literals and positive provider literals. If a user chooses a consumer feature, by knowing the consumer and provider weights, the configuration engine can determine which provider literals should be included, excluded, or remain selectable. Embodiments of the invention can implement a logic-based truth maintenance system and numerical unit resolution.

The invention relates to a method for embedding and extracting water spot from English text in the field of text copyright protection technique. It has the following steps: changing the copyright information into binary bit string, reading in the text and filtering special characters and indent and then operating the character string and copyright person's private key to obtain integer number Z, if Z can divide embedding ratio exactly, the next sentence is water spot information sentence, using Z to do negation with copyright information binary bit string to ascertain the information bit of bided embedding water spot, using Z to do negation with the number of the characters of water spot information sentence to ascertain the location of the water spot information bit so that 0, 1 which can represent the relation of the adjacent alpha codes are uniform with bided embedding water spot information bit until finish text. The process of extracting water spot information is a reverse process of embedding it.

The invention provides an 8*8 S box applicable to hardware realization and a circuit realization method thereof. The S box is compounded by using an inversion operation on a finite field GF (((22)2)2) and affine transformation of GF (2)8 and has stronger nonlinearity, difference transmission probability, snowslide performance, algebra complexity and other cryptological properties. Compared with other Galois fields comprising 28 elements, the field GF (((22)2)2) selected by the invention can reduce the complexity of the inversion operation, and the selection of polynomials generated by various levels of field extension further reduces the expense of subfield operations. The invention also provides a hardware realization mode of the S box, the entire calculation process of the S box can be fully converted into the operations of XOR, AND and negation of bits, and the hardware realization mode can be realized by using a simple logic gate circuit. The entire process does not require table lookup, so that the overall realization expense of hardware is reduced.

The invention discloses a memristor-based nonvolatile multivalued logic device and an operating method thereof. The method provides an operating method for negation and dextrorotation of three-valued logic and multivalued T gate logic, which realizes an exhaustive set of multivalued logic, such as three-valued logic based on the multi-resistance state transition characteristic of a memristor. All the logic operation results are stored in the device in a nonvolatile resistance state, such that a logic operation function and a data storage function are realized simultaneously in the device, i.e., storage and calculation are fused; therefore, a device basis is laid for going beyond the limitation from an information device Moore's law and breaking through the Von Neumann bottleneck in a computer architecture. The memristor-based multivalued logic device disclosed by the invention can be applied to a novel solid-state memory, a logic-arithmetic unit, a programmable gate array, an on-chip system and other fields as a basic unit, and provides a new path for boosting novel computer architecture.

The embodiment of the invention provides a startup and shutdown machine circuit. The circuit comprises a key module, an input module, a charging and discharging control module, a non-gate module, a trigger module and a startup and shutdown control module, wherein the key module is used for inputting key signals, the input module is used for outputting pulse signals according to the key signals and control signals output by an MCU, the charging and discharging control module is used for performing charging and discharging control and controlling the logic state of the non-gate module to be turned over, the non-gate module is used for performing negation on the pulse signals output by the input module, the trigger module is used for outputting startup and shutdown signals to the startup and shutdown control module according to the pulse signals after negation, and the startup and shutdown control module is used for outputting power supply signals to a terminal according to startup and shutdown signals so as to control the terminal to be started up or shut down. The circuit can achieve the aims of starting up and shutting down the terminal in the key pressing process and storing data in the shutting down process, and due to the fact that each module in the startup and shutdown machine circuit is composed of some independent simple components, and a single chip microcomputer is not needed, the cost of the startup and shutdown machine circuit is reduced.

The invention provides an RAM internal storage detection method. The method includes the steps that it is determined that data in an RAM internal storage area to be detected are true codes; one's complement codes generated after negation is conducted on the true codes are stored into a backup internal storage area; if same data exist in the true codes and the one's complement codes, it is judged that physical damages exist in the data in the true codes, or else negation operation is conducted on the one's complement codes read from the backup internal storage area, a CRC algorithm is utilized to check data on which the negation operation is conducted, and then backup CRC check codes are generated; original CRC check codes corresponding to the true codes and the backup CRC check codes are compared, whether the original CRC check codes corresponding to the true codes and the backup CRC check codes are consistent or not is judged, if yes, it is judged that a data line relevant to the RAM internal storage area to be detected is not damaged or the data in the true codes are not tampered, and if not, it is judged that the data line relevant to the RAM internal storage area to be detected is damaged or the data in the true codes are tampered. Consequently, by the adoption of the RAM internal storage detection method and device, the reason for causing incorrect data storage can be detected.

The invention discloses a combined electronic air purification device. The combined electronic air purification device comprises an anode plate and a cathode plate, wherein the anode plate is connected with a positive high-voltage power supply; the cathode plate is connected with a negative high-voltage power supply; dust collection and ventilation holes are distributed in the anode plate; the cathode plate is provided with electric discharge pins which are arranged at the parts corresponding to the dust collection and ventilation holes in the anode plate and extend into the dust collection and ventilation holes, so that the electric discharge pins on the cathode plate discharge negative electricity, and dust and ions in air around the electric discharge pins are provided with negative charge, and are adsorbed on the anode plate. The method integrates the characteristics of high-voltage static electricity sterilization and dust collection, plasma sterilization and dust collection and multi-point negative ion emission, prevents the problems that the static electricity generated in the high-voltage static electricity method is harmful to the health of people, and dust particles are difficult to collect in plasma purification, achieves the effect of emitting negation ions by a plurality of electric discharge pins, and can be used for purifying air with high efficiency.

The invention discloses a strategy conflict solution method and device. The method includes the steps of receiving a first control strategy, resolving the first control strategy into m first rules, receiving a second control strategy, resolving the second control strategy into n second rules, conducting negation on each first rule to obtain a first reversed rule, conducting negation on each second rule to obtain a second reversed rule, generating a corresponding first execution rule through each first reversed rule and the corresponding second reversed rule according to the rule synthesis principle, deleting the invalid rules, enabling the rest of the first execution rules to serve as the valid first execution rules, conducting negation on each valid first execution rule, and then converting the valid first execution rules into forwarding table items corresponding to a first forwarding device according to the protocol supported by the first forwarding device. By means of the method, strategy conflicts can be solved.

The invention provides a large scale phased array difference beam forming system based on sub-array division, and aims to provide a difference beam forming device that can approach to the performanceof array element level difference beams and mono-pulse tracking precision. The system comprises N*M serially connected radio frequency processing modules corresponding to antenna array elements, a digital pretreatment module, a primary sub-array inner beam forming module, and a secondary difference beam sub-array cross-regional splitting and weighting-synthesizing module. The system comprises a designed azimuth dimension and pitching dimension sub-array cross-regional splitting unit and following cascaded units: a sub-array symmetrical positive azimuth difference beam weighting processing unit, a sub-array symmetrical negative azimuth difference beam weighting processing unit, a sub-array symmetrical positive pitching difference beam weighting processing unit, a sub-array symmetrical negative pitching difference beam weighting processing unit, and an azimuth difference and azimuth difference beam synthesizing unit. An add-subtract treatment is carried out in an azimuth-pitching coordinate area division symmetrical negation mode to obtain the azimuth difference and pitching difference beams.

The invention relates to an SEU (single event upset)-resistant fast refreshing circuit and method applied to an FPGA (field programmable gate array) and based on ECCs (error correcting codes). The method comprises steps as follows: for any one frame address generated by a frame address generation module, a read-write control module reads data frames through an ICAP (internal configuration access port) of the FPGA, only reads frame data of the current frame address every time and writes the read data frame into a frame caching module; after a frame synchronization signal received by a working state control and error analysis module from a frame ECC interface of the FPGA becomes higher from lower, the ECCs of the current data frame are read, and the upset position in the data frame is calculated; a frame error correction module reads a segment of SEU data from the frame caching module according to the upset position and performs negation on the upset position, correct data after error correction is obtained and is written into the frame caching module again, the correct data frame is written into the current frame address of the FPGA again by the read-write control module, and accordingly, SEU-resistant error correction of the FPGA is completed.

The invention discloses a real-time GNSS/INS (global navigation satellite system/inertial navigation system) combined navigation signal simulator based on a PXI (PCI extensions for instrumentation) bus and relates to a real-time GNSS/INS combined navigation signal simulator in the navigation field. The simulator comprises a time-frequency signal processing unit, a user signal generating unit, the PXI bus, a PXI slot-0 controller, a rubidium clock and the like; the user signal generating unit is composed of multiple frequency-point signal generating modules, a radiofrequency signal combiner, a power divider, a power attenuator and the like. The PXI bus technique is used in system structuring, configurability and extensibility are excellent, the simulator is imparted multi-navigation system multi-frequency GNSS/INS navigation signal simulation capacity by selecting parts, especially the multi-user GNSS/INS combined negation signal simulation output capacity, and the need of the navigation field for real-time testing of GNSS, INS and GNSS/INS combined navigation signals is fully met.

The invention discloses a method and device for improving robustness of signaling frame transmission. The method includes the steps that before forward error correction encoding, a scrambled signaling frame is repeated, or repeating and negation are carried out, or a position filling 0 in the signaling frame is changed after repetition, the position filling 0 in the signaling frame can be changed after repeating and negation, and accordingly a new signal frame is generated. The device comprises a processing system, the processing system is used for repeating the scrambled signaling frame, or carrying out repeating and negation, or changing the position filling 0 in the signaling frame after repetition or changing the position filling 0 in the signaling frame after repeating and negation to generate the new signaling frame before forward error correction encoding and to transmit the new signaling frame to an encoding module of a transmitter; a receiver receives the signaling frame, decodes the signaling frame, and then restores a signaling frame b of an L bit according to the method of repetition or repeating and negation and the position filling 0 in sending. According to the method, diversity gain brought due to the fact that the signaling frame with a short bit is mapped into forward error correction encoding and input with a long bit, and reliability of signaling frame transmission is improved.

A method and apparatus for complex multiplication includes steps of: (a) receiving a complex multiplicand having a real value and an imaginary value (704); (b) generating a negation of the real value of the complex multiplicand (706); (c) generating a negation of the imaginary value of the complex multiplicand (708); (d) receiving a complex multiplier (710); and (e) selecting a phasor constant having a value wherein a complex product of the complex multiplicand times the complex multiplier times the phasor constant has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand (712).

The embodiment of the invention discloses an encoding method, a decoding method, a related device and a storage medium. The encoding method comprises the following steps: acquiring a first bit streamof original encoded data; performing a preset logic operation according to the first bit stream to obtain a second bit stream, with the number of bits of the second bit stream being greater than the number of bits of the first bit stream; whether the logic values of the last two bits in the second bit stream are the same or not is judged, if so, subjecting the logic value of at least one of the last two bits to negation processing, and acquiring a third bit stream; and inverting the target bit in the third bit stream, and inserting the inverted target bit as a flag bit into the first bit of the third bit stream to obtain target coded data. According to the embodiment of the invention, the problem of no code in the channel transmission process of the information is solved, so that the signal transmission quality is improved.

The invention discloses an ultra-lightweight RFID mutual authentication method, and belongs to the technical field of RFID. With a negation cyclic displacement operation processing tag and data stored by a rear-end database, secret data are greatly hidden. According to the authentication method, tag authentication is firstly performed, then a stage of mutual authentication is performed, and information stored by a reader-writer and an electronic tag is updated after success of mutual authentication so that forward security is guaranteed. New and old authentication information stored by the electronic tag is combined with resistance replay aggression data M which are designed in the authentication process by utilizing secret key information of the new and old authentication information so that non-synchronous aggression and replay aggression are effectively resisted.

The invention relates to a data transmission method, user equipment, a base station and a data transmission system, and the method comprises the following steps: determining the corresponding relationship between TB number and code word number of the user equipment; sending downlink control messages of DCI and TB to the user equipment, wherein the DCI comprises the corresponding relationship between the TB number of the TB which needs to be received by the UE and the code word number; receiving a confirmation ACK message or a negation NACK message fed back by the user equipment, wherein, the ACK or the NACK comprises cyclic redundancy check CRC results of various TB; and confirming the receiving state to the TB according to the CRC results of the various TB. The invention can reduce the TB number-code word number conversion problem in the prior art, as well as the problem that as a network side caches the corresponding relationship between the TB number of the TB which needs to be received by all UE and the code word number, a memory is occupied.

The invention discloses a method and system for determining a geometric outline area on an image, and the position of a predetermined geometric outline area on the image can be more accurately determined. The method for determining the geometric outline area on the image includes the steps of conducting gray processing for an original image to obtain a first processing image; respectively conducting open operation processing and closing operation processing for the first image to obtain a second processing image and a third processing image respectively; conducting margin calculation for the second and third processing images to obtain a fourth processing image; conducting binarization calculation for the fourth processing image to obtain a fifth processing image; conducting binarization calculation for the second processing image to obtain a sixth processing image; conducting negation operation processing for the sixth processing image to obtain a seventh processing image; conducting AND operation for the fifth processing image and the seventh processing image to obtain an eighth processing image; conducting contour extraction operation for the eighth processing image to obtain a contour with a predetermined geometry; and restoring position information of the contour to the first processing image to obtain a contour area with the predetermined geometry on the first processing image. The invention is suitable for use in occasions requiring accurate positioning of geometric contour area on an image.

The invention discloses a conventional aircraft model-based lateral-directional controller area design method, which is used for solving the technical problem of incapability of directly determining the whole stability of a given flight area by the conventional controller design method. According to the method, a trimming control plane, an angle of incidence of airflow and an angle of sideslip for the stable circling under a given turning radius when the altitude and mach number of a control target are given are obtained through aerodynamic force and a moment equation, the area stability of a system is determined by adopting a phase plane analysis model, and the structure and parameters of a feedback controller are determined on the basis of the area stability to directly control the lateral-directional movement of an aircraft, so that inaccurate approximation such as the negation of aerodynamic action in the moment equation is avoided, the controller can ensure the stability of the aircraft in the whole design area, and the problems of instable and unsafe flight and the like caused by the analysis model can be reduced and even solved.