S box applicable to hardware realization and circuit realization method thereof

An implementation method and circuit technology, applied in the field of information security, to achieve the effects of reducing complexity, strong nonlinearity, and reducing overhead

Inactive Publication Date: 2011-01-05
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the two transformations between the original domain and the composite domain, and a series of GF introduced by the invers

Method used

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  • S box applicable to hardware realization and circuit realization method thereof
  • S box applicable to hardware realization and circuit realization method thereof
  • S box applicable to hardware realization and circuit realization method thereof

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0035] The present invention will be further described below in conjunction with specific examples.

[0036] S box of the present invention is as follows to the processing procedure of 8 bit data:

[0037] 1. The input 8-bit data As a parallel connection of two 4-bit data, record the upper 4 bits as , the lower 4 bits are , , in the sense of finite fields, the representations are respectively , .

[0038] 2. in In (the same below) calculation

[0039] 3. Calculate , (can be parallelized);

[0040] 4. Calculate

[0041] 5. in Zhongqiu inverse of

[0042] 6. Calculate , ;

[0043] 7. Will and paralleled into an 8-bit number , its high and low 4 bits are and 4 bits of

[0044] (The results obtained from the calculation process from step 1 to step 7 satisfy )

[0045] 8. Calculate ;(function The calculation formula has been given above).

[0046] 9. Output 8-bit data

[0047] The above operation involves the domain The op...

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Abstract

The invention provides an 8*8 S box applicable to hardware realization and a circuit realization method thereof. The S box is compounded by using an inversion operation on a finite field GF (((22)2)2) and affine transformation of GF (2)8 and has stronger nonlinearity, difference transmission probability, snowslide performance, algebra complexity and other cryptological properties. Compared with other Galois fields comprising 28 elements, the field GF (((22)2)2) selected by the invention can reduce the complexity of the inversion operation, and the selection of polynomials generated by various levels of field extension further reduces the expense of subfield operations. The invention also provides a hardware realization mode of the S box, the entire calculation process of the S box can be fully converted into the operations of XOR, AND and negation of bits, and the hardware realization mode can be realized by using a simple logic gate circuit. The entire process does not require table lookup, so that the overall realization expense of hardware is reduced.

Description

technical field [0001] The invention belongs to the field of information security, and in particular relates to a non-linear transformation suitable for hardware implementation in block cipher algorithms—the structure of an S-box, and an efficient hardware implementation method thereof, which does not involve any table look-up operation. Background technique [0002] Generally, a block cipher includes an obfuscation layer and a diffusion layer, and the obfuscation layer can be composed of several juxtaposed and independent substitution functions—S-boxes. The S-box can essentially be regarded as a vector-valued Boolean function with multiple outputs: [0003] [0004] and called the S box, it will be a bits of data mapped to a bits of data. As the core component to provide obfuscation, S-boxes mostly use random permutation or non-linear functions over finite fields. At present, the S-box has become the only nonlinear module of many block cipher algorithms, and its ...

Claims

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Application Information

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IPC IPC(8): H04L9/00
Inventor 郑志明王钊邱望洁王文华张筱高莹刘建伟
Owner BEIHANG UNIV
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